Trace Design for Bump-on-Trace (BOT) Assembly
A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small.
This application is a continuation U.S. patent application Ser. No. 15/456,134, filed on Mar. 10, 2017, entitled “Trace Design for Bump-on-Trace (BOT) Assembly,” which is a continuation of U.S. patent application Ser. No. 14/143,648, filed Dec. 30, 2013, entitled “Trace Design for Bump-on-Trace (BOT) Assembly,” which application is incorporated herein by reference in its entirety.
BACKGROUNDIn a package such as a flip chip Chip Scale Package (fcCSP), an integrated circuit (IC) or die is mounted to a substrate (e.g., a printed circuit board (PCB) or other integrated circuit carrier) through a bump on trace (BOT) interconnection. The BOT interconnection employs solder to electrically couple the bump of the IC to the trace of the substrate.
In light of the demand for ever smaller packages, attempts are often made to reduce the distance between adjacent bumps, which is known as the bump pitch. One way to reduce the bump pitch is by reducing the distance between neighboring metal traces.
Unfortunately, reducing the distance between neighboring metal traces may lead to undesirable or detrimental consequences. For example, if the neighboring metal traces are too close to each other, a solder bridge may form during reflow when the BOT interconnection is established.
For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTSThe making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.
The present disclosure will be described with respect to embodiments in a specific context, namely a package incorporating a bump-on-trace (BOT) interconnection. The concepts in the disclosure may also apply, however, to other packages, interconnection assemblies, or semiconductor structures.
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As shown, the BOT assembly 10 is employed to electrically (and, in some embodiments, structurally) couple a die 14 (in
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In an embodiment, the landing trace 18 and the conductive pillar 20 may take a variety of suitable shapes. In other words, the landing trace 18 and the conductive pillar 20 are not limited to the shape illustrated in
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In an embodiment, the solder feature 22 engages and abuts both of the sidewalls 28 of the landing trace 18. In an embodiment, the solder feature 22 also engages and abuts the end surface 26 of the landing trace 18. The solder feature 22 may be a solder paste, a solder ball, or another suitable fusible metal alloy used to join components and having a melting point below that of the components.
Because the conductive pillar 20 extends at least to, and may overhang, the distal end 24 of the landing trace 18 as shown in
Because the volume of solder is shared between the two sidewalls 28 of the landing trace 18, the distance between the solder feature 22 and the neighboring trace 30 is decreased relative to when most or all of the solder feature 22 collects along only the sidewall 28 of the landing trace 18 facing the neighboring trace 30. Therefore, the pitch between the landing trace 18 and the neighboring trace 30 can be reduced to, for example, provide for a smaller overall package 10.
In an embodiment, the volume of solder is shared between the two sidewalls 28 and the end surface 26 of the landing trace 18. In such an embodiment, the distance between the solder feature 22 and the neighboring trace 30 may be even further decreased relative to when the solder feature 22 collects along only the sidewall 28 of the landing trace 18 facing the neighboring trace 30.
In an embodiment, the landing trace 18 may be made smaller than the neighboring trace 30 from the outset. In such circumstances, the portion 38 of the landing trace 18 depicted by dashed lines in
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In an embodiment, the landing trace 18 and the neighboring trace 30 may be initially formed with the same length and, thereafter, the portion 38 may be removed to provide the landing trace 18 with a shorter length. The portion 38 of the landing trace 18 may be removed by, for example, etching. The portion 38 of the landing trace may also be suitably removed by a laser cut, laser burn, selective etching process, a mechanical cut, etc.
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In an embodiment, the length, L, of the landing trace 18 within the periphery 32 of the conductive pillar 20 is about 20% to about 100% of the diameter, R, of the conductive pillar 20. The 20% lower limit was selected because the total assembly process variation is around 20% of the diameter, R, of the conductive pillar 20. Therefore, in order to ensure that the conductive pillar 20 has a suitable joint on the landing trace 18, the length, L, of the landing trace 18 is suggested to be 20% or more of the diameter, R, of the conductive pillar 20. If not, an electric open may be encountered after the assembly process because the conductive pillar 20 does not contact on landing trace 18. In an embodiment, the conductive pillar 20 is positioned such that the length, L, of the landing trace 18 within the periphery 32 of the conductive pillar 20 is less than 100% of the diameter, R, of the conductive pillar 20. In other words, the equation ⅕ R≤L≤R is satisfied.
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From the foregoing, those of ordinary skill in the art will recognize that the BOT assembly 10 controls or minimizes solder extrusion. Moreover, the BOT assembly 10 enables solder to more uniformly disperse over the landing trace. Therefore, the potential for the formation of a solder bridge is reduced in fine bump pitch packages. In other words, undesirable solder bridging between adjacent traces in a fine pitch bump (I/O) design is inhibited or prevented. In addition, BOT assembly 10 provides a more robust and reliable electrical interconnection for the package 12 by changing existing trace pattern design without substantial additional process cost.
An embodiment method of forming a bump-on-trace (BOT) assembly includes forming a landing trace on a substrate, positioning a conductive pillar over the landing trace such that the conductive pillar extends at least to an end of the landing trace, and reflowing a solder feature between the landing trace and the conductive pillar to electrically couple the landing trace to the conductive pillar.
An embodiment method of forming a bump-on-trace (BOT) assembly includes forming a landing trace on a substrate, removing a portion of the landing trace to generate an augmented wetting area, and applying solder over the augmented wetting area of the landing trace to electrically couple the landing trace to a conductive pillar.
An embodiment bump-on-trace (BOT) interconnection for a package includes a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace, and a solder feature electrically coupling the landing trace and the conductive pillar.
An embodiment structure includes a substrate and a landing trace on the substrate. The landing trace has a first side and a second side opposite to the first side. The landing trace has a plurality of indents extending into the first side in a plan view. The second side is free of indents in the plan view.
An embodiment structure includes a substrate and a landing trace on the substrate. The landing trace has a first sidewall and a second sidewall opposite to the first sidewall. The first sidewall has a plurality of indents in a plan view. An entirety of the second sidewall is a planar sidewall.
An embodiment structure includes a substrate and a landing trace on the substrate. The landing trace includes a first portion, a second portion, and a third portion connecting the first portion to the second portion in a plan view. A first sidewall of the first portion is collinear with a first sidewall of the second portion in the plan view. A second sidewall of the first portion is collinear with a second sidewall of the second portion and a second sidewall of the third portion in the plan view. The first sidewall of the third portion has a plurality of indents in the plan view. An entirety of the second sidewall of the third portion is a planar sidewall.
While the disclosure provides illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments, will be apparent to persons of ordinary skill in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.
Claims
1. A structure comprising:
- a substrate; and
- a landing trace on the substrate, the landing trace having a first side and a second side opposite to the first side, the landing trace having a plurality of indents extending into the first side in a plan view, the second side being free of indents in the plan view.
2. The structure of claim 1, further comprising a solder feature over the landing trace, the solder feature extending into the plurality of indents.
3. The structure of claim 2, wherein solder feature is in physical contact with the plurality of indents.
4. The structure of claim 2, further comprising a conductive pillar over the solder feature, the conductive pillar overlapping with the plurality of indents in the plan view.
5. The structure of claim 4, wherein a width of the solder feature is greater than a width of the conductive pillar.
6. The structure of claim 4, wherein a width of the landing trace is less than a width of the conductive pillar.
7. The structure of claim 1, wherein the plurality of indents have a comb pattern in the plan view.
8. A structure comprising:
- a substrate; and
- a landing trace on the substrate, the landing trace having a first sidewall and a second sidewall opposite to the first sidewall, the first sidewall having a plurality of indents in a plan view, an entirety of the second sidewall being a planar sidewall.
9. The structure of claim 8, further comprising a solder feature over the landing trace, the solder feature filling the plurality of indents.
10. The structure of claim 9, wherein a width of the solder feature is greater than a width of the landing trace.
11. The structure of claim 9, wherein the solder feature is in physical contact with the second sidewall of the landing trace.
12. The structure of claim 9, further comprising a conductive pillar over the solder feature, the conductive pillar overlapping with the plurality of indents in the plan view.
13. The structure of claim 12, wherein a width of the solder feature is greater than a width of the conductive pillar.
14. The structure of claim 8, wherein the plurality of indents have a comb pattern in the plan view.
15. A structure comprising:
- a substrate; and
- a landing trace on the substrate, the landing trace comprising: a first portion; a second portion; and a third portion connecting the first portion to the second portion in a plan view, a first sidewall of the first portion being collinear with a first sidewall of the second portion in the plan view, a second sidewall of the first portion being collinear with a second sidewall of the second portion and a second sidewall of the third portion in the plan view, the first sidewall of the third portion having a plurality of indents in the plan view, an entirety of the second sidewall of the third portion being a planar sidewall.
16. The structure of claim 15, wherein the plurality of indents have a comb pattern in the plan view.
17. The structure of claim 15, further comprising a solder feature over the third portion of the landing trace, the solder feature overlapping with the plurality of indents in the plan view.
18. The structure of claim 17, wherein the solder feature is in physical contact with the plurality of indents.
19. The structure of claim 17, further comprising a conductive pillar over the solder feature, the conductive pillar overlapping with the plurality of indents in the plan view.
20. The structure of claim 19, wherein the conductive pillar is in physical contact with the solder feature.
Type: Application
Filed: Apr 22, 2019
Publication Date: Aug 15, 2019
Inventors: Yen-Liang Lin (Taichung), Chen-Shien Chen (Zhubei), Tin-Hao Kuo (Hsinchu)
Application Number: 16/390,953