SEMICONDUCTOR STRUCTURE
A semiconductor structure includes a substrate, a gate structure disposed over the substrate, a source/drain structure disposed in the substrate at two sides of the gate structure, and a conductive plug. The source/drain structure includes an epitaxial layer and a dual metal silicide on the epitaxial layer. The epitaxial layer includes a first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is greater than a lattice constant of the first semiconductor material. The dual metal silicide includes the first semiconductor material, the second semiconductor material, a first metal material and a second metal material. An atomic size of the second metal material is greater than an atomic size of the first metal material. The conductive plug penetrates the dual metal silicide.
This application is a continuation of U.S. patent application Ser. No. 15/881,159, filed on Jan. 26, 2018, entitled of “SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME”, which claims the benefit of U.S. Provisional Patent Application Ser. No. 62/585,810 filed Nov. 14, 2017, the entire disclosure of which is hereby incorporated by reference.
BACKGROUNDIn the fabrication of integrated circuit devices, logic products are often produced using silicide operations in order to obtain higher circuit performance. In silicidation, a refractory metal layer is deposited on a silicon wafer or a silicon layer and then annealed. The underlying silicon reacts with the refractory metal layer to produce a silicide overlying the gate electrode and source and drain regions. The silicided gate and source/drain regions have lower resistance than non-silicided regions, especially in smaller geometries, and hence, higher circuit performance.
As the dimensions within integrated circuits have grown ever smaller, solutions have had to be found to problems relating to misalignment of successive mask patterns relative to one another during operation. Therefore approaches such as salicide (self-aligned silicide) operation is developed to take advantage of the fact that certain metals react when heated in contact with silicon to form conductive silicides but do not react with silicon oxide. Thus, oxide spacers on the vertical walls of the gate pedestal could be used to provide the necessary small, but well-controlled, separation between the source and drain contacts and the gate contact.
Although the salicide operation made possible significant reductions in device size, as devices shrank even further, other issue emerges. For example, as the devices become smaller, the source/drain regions become shallower and salicide induces damage to the subjacent junctions. For example, metal spiking, where the metal diffuses unevenly into the silicon wafer or silicon layer is induced. Consequently, junction leakage is likely to occur. There is therefore a need in the semiconductor processing art to develop a method for forming improved salicides having reduced parasitic electrical leakage while maintaining a low sheet resistance.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper”, “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As used herein, the terms such as “first”, “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first”, “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.
As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be deemed to be “substantially” the same or equal if a difference between the values is less than or equal to ±10% of an average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, “substantially” parallel can refer to a range of angular variation relative to 0° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, “substantially” perpendicular can refer to a range of angular variation relative to 90° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.
A prevalent way of reducing contact resistance between polysilicon gates and source/drain regions and interconnect lines is by forming a metal silicide atop the source/drain regions and the gate electrodes prior to application of the conductive film for formation of the various conductive interconnect lines. Presently, In some embodiments, a metal layer, such as titanium (Ti), is blanketly deposited over the semiconductor substrate, specifically over exposed source/drain and gate electrode regions, and the wafer is then subjected to one or more annealing steps, for example at a temperature of 800° C. or higher for titanium. This annealing operation causes the metal to selectively react with the exposed silicon of the source/drain regions and the gate electrodes, thereby forming a metal silicide (e.g., TiSi2).
A thin silicide layer is more resistive than a thicker silicide layer of the same material. The formation of a thick silicide layer, however, may cause a high junction leakage current and low reliability, particularly when forming ultra-shallow junctions, due to the metal spiking issue. In some embodiments, such spiking issue is even worse when the metal silicide is formed on an epitaxial structure such as silicon germanium (SiGe), which may have defects such as vacancies, clustering and voids. In some embodiments spiking along the vacancy or void defect in the epitaxial SiGe structure is referred to as Ti/Ge extrusion or piping.
The present disclosure therefore provides a method for manufacturing a semiconductor structure that is able to mitigate the metal spiking or extrusion issue. In some embodiments, the present disclosure provides large-sized metal ions deposited or implanted before anneal. Such large-sized metal ions obstruct diffusing paths and thus suppress metal diffusion or extrusion. Accordingly, metal spiking is mitigated.
In some embodiments, Ge concentration in the epitaxial structure 410 may be increased to increase stress. In some embodiments, the epitaxial structure 410 can include a multi-layered structure, and each layer of the multi-layered structure includes a different Ge concentration that is upwardly increased from a bottom of the recess. Further, depending on a specification requirement of the transistor device 420, a suitable range of Ge concentration could be drawn to yield an optimum level of performance. In some embodiments, high Ge concentration in the epitaxial structure 410 may incorporate boron (B) to provide the required semiconductor doping to form the PFET, and to lower sheet resistance and thus improve contact resistance in the SiGe source/drain 426.
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It should be noted that although the embodiments are described with respect to illustrative examples in a specific context, such as boron doped, epitaxial growth, SiGe embedded stressors for source/drain in PFET, the method for manufacturing the semiconductor structure 10 may also be applied, however, to other semiconductor devices, including other stressor materials.
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It should be noted that although the embodiments are described with respect to illustrative examples in a specific context, such as boron doped, epitaxial growth, SiGe embedded stressors for source/drain in PFET, the method for manufacturing the semiconductor structure 20 may also be applied, however, to other semiconductor devices, including other stressor materials.
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It should be noted that although the embodiments are described with respect to illustrative examples in a specific context, such as boron doped, epitaxial growth, SiGe embedded stressors for source/drain in PMOS transistors, the method for manufacturing the semiconductor structure 30 may also be applied, however, to other semiconductor devices, including other stressor materials.
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By reducing the formation of meta-stable C49 TiSiX, the quaternary metal silicide layer 630 shows improved performance in post back-end-of-line (BEOL) thermal or electrode migration test. It is noteworthy that such improvement is achieved in a relatively lower anneal temperature. As mentioned above, the temperature of the anneal 442/542/642 is lower than 600° C., which is much lower than the anneal whose temperature is about 800° C. in some embodiments. Further, since tungsten has higher melting point, tungsten remains relatively stable and thus is able to obstruct Ti spiking. In the epitaxial structure 610, which includes dislocation and vacancy defect, such Ti-spiking obstruction is more appreciable. Additionally, TiSiGe diffusion or extrusion along the vacancy is also obstructed by tungsten. In other words, tungsten can suppress TiSiGe diffusion/extrusion and Ti-spiking, and thus quaternary metal silicide layer 630 includes improved stability and reliability. Further, it is found the quaternary metal silicide layer 630 is more stable, and has lower resistance due to less oxidation.
Further, in some embodiments that boron is over-doped in the epitaxial structure for improving contact resistance in the epitaxial structure, interstitials or vacancies are created. Consequently, TiSiGe diffusion and/or Ti-spiking are even worse in those embodiments. Additionally, boron may tend to out-diffuse into the transistor channel region, therefore stability and reliability of the transistor device is adversely impacted. However, by forming the quaternary metal silicide layer 630 including the second metal that improving silicide reliability and stability, boron over-doping is no longer in need. Thus the boron out-diffuse, TiSiGe diffusion and/or Ti-spiking issues are all mitigated.
Accordingly, the present disclosure provides methods for manufacturing a semiconductor structure 10, 20 and 30 including a quaternary metal silicide layer 450/550/650 over the epitaxial structure 410/510/610. By providing the quaternary metal silicide layer 450/550/650 including the second metal material whose atomic size is greater than the first metal material, diffusion/extrusion or spiking defects and boron out-diffusion issue are all mitigated. And thus stability and reliability of the metal silicide layers 450/550/650 and the transistors 420/520/620 are improved. Further, in some embodiments, as semiconductor technology pushes to 10 nanometers (N10) and below scale, such improvements are more appreciable.
In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate, a gate structure disposed over the substrate, a source/drain structure disposed in the substrate at two sides of the gate structure, and a conductive plug. The source/drain structure includes an epitaxial layer and a dual metal silicide on the epitaxial layer. The epitaxial layer includes a first semiconductor material and a second semiconductor material. In some embodiments, a lattice constant of the second semiconductor material is greater than a lattice constant of the first semiconductor material. The dual metal silicide includes the first semiconductor material, the second semiconductor material, a first metal material and a second metal material. In some embodiments, an atomic size of the second metal material is greater than an atomic size of the first metal material. In some embodiments, the conductive plug penetrates the dual metal silicide.
In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate, a gate structure disposed over the substrate, a source/drain structure disposed in the substrate at two sides of the gate structure, and a conductive plug. The source/drain structure includes an epitaxial layer and a dual metal silicide on the epitaxial layer. The dual metal silicide includes a first metal material and a second metal material. In some embodiments, the conductive plug penetrates the dual metal silicide. In some embodiments, a bottom most surface of the conductive plug is lower than a bottom most surface of the dual metal silicide.
In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate, a gate structure disposed over the substrate, an epitaxial source structure and an epitaxial drain structure disposed in the substrate at two sides of the gate structure, and a dual metal silicide on each of the epitaxial source structure and the epitaxial drain structure. In some embodiments, each of the epitaxial source structure and the epitaxial drain structure includes a first semiconductor material, a second semiconductor material, and a lattice constant of the second semiconductor material is greater than a lattice constant of the first semiconductor material. In some embodiments, the dual metal silicide includes TiW silicide, TiTa silicide, TiNb silicide or TiAu silicide.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A semiconductor structure comprising:
- a substrate;
- a gate structure disposed over the substrate;
- a source/drain structure disposed in the substrate at two sides of the gate structure, wherein the source/drain structure comprises: an epitaxial layer comprising a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material being greater than a lattice constant of the first semiconductor material; and a dual metal silicide on the epitaxial layer, wherein the dual metal silicide comprises the first semiconductor material, the second semiconductor material, a first metal material and a second metal material, and an atomic size of the second metal material is greater than an atomic size of the first metal material; and
- a conductive plug penetrating the dual metal silicide.
2. The semiconductor structure of claim 1, wherein a bottom most surface of the conductive plug is lower than a bottom most surface of the dual metal silicide.
3. The semiconductor structure of claim 1, wherein the dual metal silicide comprises TiXSiGe.
4. The semiconductor structure of claim 3, wherein “X” of the dual metal silicide comprises W, Ta, Pt, Nb, or Au.
5. The semiconductor structure of claim 1, wherein a concentration of the second metal material is less than a concentration of the first metal material.
6. The semiconductor structure of claim 1, further comprising a spacer disposed over sidewalls of the gate electrode, wherein the dual metal silicide is in contact with the epitaxial layer, the contact plug and the spacer.
7. The semiconductor structure of claim 1, further comprising a contact etch stop layer (CESL) disposed over the substrate, and the dual metal silicide is in contact with the dual metal silicide.
8. A semiconductor structure comprising:
- a substrate;
- a gate structure disposed over the substrate;
- a source/drain structure disposed in the substrate at two sides of the gate structure, wherein the source/drain structure comprises: an epitaxial layer; and a dual metal silicide on the epitaxial layer and comprising a first metal material and a second metal material; and
- a conductive plug penetrating the dual metal silicide,
- wherein a bottom most surface of the conductive plug is lower than a bottom most surface of the dual metal silicide.
9. The semiconductor structure of claim 8, wherein the epitaxial layer comprises a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is greater than a lattice constant of the first semiconductor material.
10. The semiconductor structure of claim 9, wherein a concentration of the second semiconductor material is increased upwardly from a bottom surface to a top surface of the epitaxial layer.
11. The semiconductor structure of claim 9, wherein the dual metal silicide further comprises the first semiconductor material and the second semiconductor material.
12. The semiconductor structure of claim 8, wherein an atomic size of the second metal material is greater than an atomic size of the first metal material.
13. The semiconductor structure of claim 12, wherein the dual metal silicide comprises TiXSiGe.
14. The semiconductor structure of claim 13, wherein “X” of the dual metal silicide comprises W, Ta, Pt, Nb, or Au.
15. The semiconductor structure of claim 8, wherein a concentration of the second metal material is less than a concentration of the first metal material.
16. The semiconductor structure of claim 15, wherein the concentration of the second metal material is between about 1% and about 30%.
17. A semiconductor structure comprising:
- a substrate;
- a gate structure disposed over the substrate;
- an epitaxial source structure and an epitaxial drain structure disposed in the substrate at two sides of the gate structure, wherein each of the epitaxial source structure and the epitaxial drain structure comprises a first semiconductor material, a second semiconductor material, and a lattice constant of the second semiconductor material is greater than a lattice constant of the first semiconductor material; and
- a dual metal silicide on each of the epitaxial source structure and the epitaxial drain structure, wherein the dual metal silicide comprises TiW silicide, TiTa silicide, TiNb silicide or TiAu silicide.
18. The semiconductor structure of claim 17, further comprising:
- a conductive plug penetrating the dual metal silicide; and
- a contact etch stop layer (CESL) disposed over the substrate and in contact with the dual metal silicide.
19. The semiconductor structure of claim 17, wherein a concentration of W, a concentration of Ta, a concentration of Nb, and a concentration of Au is less than a concentration of Ti.
20. The semiconductor structure of claim 19, wherein the concentration of W, the concentration of Ta, the concentration of Nb, and the concentration of Au is between about 1% and about 30%.
Type: Application
Filed: Nov 15, 2019
Publication Date: Mar 12, 2020
Patent Grant number: 11177172
Inventors: YAN-MING TSAI (MIAOLI COUNTY), WEI-YIP LOH (HSINCHU CITY), YU-MING HUANG (TAINAN CITY), HUNG-HSU CHEN (TAINAN CITY), CHIH-WEI CHANG (HSIN-CHU)
Application Number: 16/685,948