FABRICATION OF A VERTICAL TRANSISTOR WITH SELF-ALIGNED BOTTOM SOURCE/DRAIN
A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, including forming a doped layer on a substrate, forming one or more vertical fins on the doped layer, forming a protective layer on the one or more vertical fins, wherein the protective layer has a thickness, and forming at least one isolation trench by removing at least a portion of the protective layer on the doped layer, wherein the isolation trench is laterally offset from at least one of the one or more vertical fins by the thickness of the protective layer.
The present invention generally relates to the fabrication of vertical fin field effect transistors (vertical finFETs) with self-aligned source/drains, and more particularly to the use of the thickness of a conformally deposited layer to control lateral positioning of bottom source/drains and isolation trenches.
Description of the Related ArtA Field Effect Transistor (FET) typically has a source, a channel, and a drain, where current flows from the source to the drain, and a gate that controls the flow of current through the channel. Field Effect Transistors (FETs) can have a variety of different structures, for example, FETs have been fabricated with the source, channel, and drain formed in the substrate material itself, where the current flows horizontally (i.e., in the plane of the substrate), and finFETs have been formed with the channel extending outward from the substrate, but where the current also flows horizontally from a source to a drain. The channel for the finFET can be an upright slab of thin rectangular Si, commonly referred to as the fin with a gate on the fin, as compared to a MOSFET with a single gate in the plane of the substrate. Depending on the doping of the source and drain, an n-FET or a p-FET may be formed.
Examples of FETs can include a metal-oxide-semiconductor field effect transistor (MOSFET) and an insulated-gate field-effect transistor (IGFET). Two FETs also may be coupled to form a complementary metal oxide semiconductor (CMOS), where a p-channel MOSFET and n-channel MOSFET are coupled together.
With ever decreasing device dimensions, forming the individual components and electrical contacts become more difficult. An approach is therefore needed that retains the positive aspects of traditional FET structures, while overcoming the scaling issues created by forming smaller device components.
SUMMARYIn accordance with an embodiment of the present principles, a method is provided of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain. The method includes the step of forming a doped layer on a substrate, forming one or more vertical fins on the doped layer, forming a protective layer on the one or more vertical fins, wherein the protective layer has a thickness, and forming at least one isolation trench by removing at least a portion of the protective layer on the doped layer, wherein the isolation trench is laterally offset from at least one of the one or more vertical fins by the thickness of the protective layer.
The method further includes the step of forming a gate structure on at least one of the one or more vertical fins, and forming a contact gap through the gate structure to one of the two or more doped layer regions.
In accordance with an embodiment of the present principles, a method is provided of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain. The method includes the step of forming a doped layer on a substrate, forming a plurality of vertical fins on the doped layer, wherein there is a distance between at least two adjacent vertical fins forming an intervening space, forming a protective layer on the one or more vertical fins, wherein the protective layer has a thickness equal to or greater than half the distance between the at least two adjacent vertical fins, such that the protective layer fills the intervening space, and forming at least one isolation trench by removing at least a portion of the protective layer on the doped layer, wherein the protective layer filling the intervening space prevents formation of the at least one isolation trench in the intervening space.
In accordance with another embodiment of the present principles, a vertical fin field effect transistor (vertical finFET) having a self-aligned bottom source/drain is provided. The vertical finFET includes one or more doped layer regions on a substrate, one or more vertical fins formed on one of the one or more doped layer regions, wherein the one of the one or more doped layer regions forms a bottom source drain for the one or more vertical fins, one or more dielectric spacer(s) on the substrate, wherein at least one of the one or more dielectric spacer(s) is offset from at least one of the one or more vertical fins by a width, W1, that defines a boundary along a side of one of the one or more doped layer regions, and a metal contact between the at least one of the one or more dielectric spacer(s) and the at least one of the one or more vertical fins, wherein the metal contact is on the one of the one or more doped layer regions and in electrical contact with the one of the one or more doped layer regions.
The vertical finFET further includes a gate structure on the one or more vertical fins formed on the one of the one or more doped layer regions, and a gap liner, wherein the gap liner is between the gate structure and the at least one of the one or more dielectric spacer(s) offset from the at least one of the one or more vertical fins, and the gap liner physically and electrically separates the metal contact from the gate structure.
These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein:
Principles and embodiments of the present disclosure relate generally to the fabrication of vertical fin field effect transistor (vertical finFET) devices with the vertical fins self-aligned with an underlying doped region. The lateral positioning of the vertical fins relative to the perimeter of a doped region in the substrate may be determined by the thickness of a masking layer formed on the vertical walls of the fins, where the layer thickness can define a lateral offset.
In various embodiments, the doped region forming a bottom source/drain for a finFET device with the same number of vertical fins has approximately the same dimensions because the thickness of a masking layer defines the lateral offset of the periphery of the doped region.
Principles and embodiments of the present disclosure also relates to the formation of isolation trenches in regions of the substrate between vertical fins that are not pinched off by a masking layer. In various embodiments, a portion of a doped region and underlying substrate may be removed to form an isolation trench between masked vertical fins, while other portions of the doped region remain unetched due to a greater vertical thickness of the masking layer between the top of the masking layer and the substrate.
Exemplary applications/uses to which the present principles can be applied include, but are not limited to: NAND gates, NOR gates, XOR gates, static random access memory (SRAM), inverters, etc.
It is to be understood that the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps may be varied within the scope of the present invention.
Referring now to the drawings in which like numerals represent the same or similar elements and initially to
In one or more embodiments, a substrate 110 may be a semiconductor or an insulator with an active surface semiconductor layer. The substrate may be crystalline, semi-crystalline, microcrystalline, or amorphous. The substrate may be essentially (i.e., except for contaminants) a single element (e.g., silicon), primarily (i.e., with doping) of a single element, for example, silicon (Si) or germanium (Ge), or the substrate may include a compound, for example, Al2O3, SiO2, GaAs, InP, SiC, or SiGe. The substrate may also have multiple material layers, for example, a semiconductor-on-insulator substrate (SeOI), a silicon-on-insulator substrate (SOI), germanium-on-insulator substrate (GeOI), or silicon-germanium-on-insulator substrate (SGOI). The substrate may also have other layers forming the substrate, including high-k oxides and/or nitrides. In one or more embodiments, the substrate 110 may be a silicon wafer, a silicon germanium wafer, or III-V semiconductor wafer. In an embodiment, the substrate may be a single crystal silicon (Si), silicon germanium (SiGe), or III-V semiconductor (e.g., GaAs) wafer, or have a single crystal silicon (Si), silicon germanium (SiGe), or III-V semiconductor (e.g., GaAs) surface/active layer.
In various embodiments, the surface of the wafer or active layer may be processed to form a thermal oxide and/or doped region. The surface may have a predetermined crystal orientation for epitaxial growth of subsequent layers.
In one or more embodiments, a doped layer 120 may be formed on the substrate 110. The doped layer may be formed by epitaxial growth of a semiconductor layer on the substrate with in-situ doping to preserve the crystallinity and crystallographic orientation of the substrate. In various embodiments, an epitaxially grown doped layer may be doped with boron, where the doped layer may be SiGe to form a p-type FET. In various embodiments, an epitaxially grown doped layer may be doped with phosphorus, arsenic, indium, or combinations thereof, where the doped layer may be Si to form an n-type FET. In various embodiments, carbon may also be added to the doped layer.
In various embodiments, a doped layer 120 may be formed by ex-situ doping, for example, by ion implantation, plasma doping, gas phase doping, solid phase doping, or liquid phase doping, to the substrate 110 or an active layer on a substrate. In various embodiments, the doping concentration may be in the range of about 1×1019/cm3 to about 2×1021/cm3, although other doping concentrations are contemplated.
In various embodiments, the doped layer 120 may have a thickness in the range of about 10 nm to about 100 nm, or in the range of about 20 nm to about 50 nm, or in the range of about 30 nm to about 40 nm, although other thicknesses are contemplated.
In one or more embodiments, a channel layer 130 may be formed on the doped layer 120, where the channel layer 130 may be a semiconductor layer. In various embodiments, a channel layer 130 may be formed on a crystalline doped layer 120 by epitaxial growth of an intrinsic semiconductor material. In various embodiments, the channel layer may be an intrinsic silicon or silicon-germanium (SiGe) material grown on a doped SiGe doped layer 120.
In various embodiments, the channel layer 130 may have a thickness in the range of about 20 nm to about 100 nm, or in the range of about 30 nm to about 80 nm, or in the range of about 40 nm to about 60 nm, although other thicknesses are contemplated. The channel layer thickness may determine the height of vertical fins subsequently formed on the doped layer 120.
In one or more embodiments, a hardmask layer 140 may be formed on an exposed surface of the channel layer 130. A photo mask layer 150 may be formed on the exposed surface of the hardmask layer 140. In various embodiments, the hardmask layer may be an oxide, for example, silicon oxide (SiO), a nitride, for example, a silicon nitride (SiN), or an oxynitride, for example, silicon oxynitride (SiON), or combinations thereof. In various embodiments, the hardmask layer 140 may be silicon nitride (SiN), for example, Si3N4. The hard mask 140 layer may be formed by a thermal process, such as, for example, oxidation or nitridation of the semiconductor channel layer 130. A combination of the various deposition and/or growth processes may also be used to form hardmask layer 140.
In various embodiments, a photo mask layer 150 may be a temporary resist (e.g., polymethyl methacrylate (PMMA)) that may be deposited on the hardmask layer 140, patterned, and developed to expose portions of the hardmask layer 140. The photo mask layer 150 may be a positive resist or a negative resist.
In various embodiments, the hardmask layer 140 may have a thickness in the range of about 20 nm to about 80 nm, or in the range of about 30 nm to about 60 nm, or in the range of about 40 nm to about 50 nm, although other thicknesses are contemplated.
In one or more embodiments, the photo mask layer 150 may be patterned and developed to form photo mask blocks 151 covering at least a portion of the surface of the hardmask layer 140. Portions of the photo mask layer 150 may be removed to form the photo mask blocks 151 and expose underlying portions of the hardmask layer 140. The photo mask blocks 151 may protect the covered portion of the hardmask layer 140, while exposed portions of the hardmask layer 140 may be etched to form hardmask fin templates on the channel layer 130. One or more photo mask blocks 151 may define the width, length, and pitch of the one or more hardmask fin templates and thereby, the width, length, and pitch of the one or more vertical fins formed in the channel layer 130.
In one or more embodiments, the photo mask blocks 151 may have a width in the range of about 6 nm to about 20 nm, or may have a width in the range of about 8 nm to about 15 nm, or may have a width in the range of about 10 nm to about 12 nm. The photo mask blocks 151 may have a length in the range of about 100 nm to about 1000 nm, or in the range of about 100 nm to about 500 nm, or in the range of about 100 nm to about 400 nm, or in the range of about 100 nm to about 200 nm.
In various embodiments, there may be a pitch between adjacent photo mask blocks 151 in the range of about 15 nm to about 200 nm, or in the range of about 30 nm to about 100 nm, or in the range of about 30 nm to about 50 nm, or about 42 nm.
In one or more embodiments, the hardmask layer 140 may be etched to form one or more hardmask fin template(s) 141, where the photo mask blocks 151 defined the width, length, and location of the hardmask fin template(s) 141 on the channel layer 130. In various embodiments, the hardmask fin template(s) 141 may be formed by a dry plasma etch.
In one or more embodiments, the photo mask blocks 151 may be removed to expose the top surface(s) of the one or more hardmask fin template(s) 141. The photo mask blocks 151 may be removed by known stripping methods.
In one or more embodiments, the pattern of the hardmask fin template(s) 141 may be transferred to the channel layer 130. Portions of the channel layer 130 between hardmask fin template(s) 141 may be removed to form a plurality of vertical fins 131 on the doped layer 120. In various embodiments, one or more vertical fin(s) 131 may be formed by an anisotropic etch that removes channel layer material not covered by a hardmask fin template 141, where the vertical fin(s) 131 may have approximately vertical sidewalls and endwalls. The channel layer material may be removed down to the interface of the channel layer 130 with the doped layer 120, where the doped layer may be exposed between adjacent hardmask fin template(s) 141 and vertical fins 131. In various embodiments, an anisotropic etch may be a dry plasma etch, for example, a reactive ion etch (RIE).
In one or more embodiments, the vertical fin(s) 131 may have a width in the range of about 4 nm to about 20 nm, or may have a width in the range of about 6 nm to about 15 nm, or may have a width in the range of about 8 nm to about 12 nm.
In various embodiments, a sidewall image transfer (SIT) technique may be used to form one or more vertical fins 131 on the doped layer 120. In a typical SIT process, spacers are formed on the sidewall of a sacrificial mandrel. The sacrificial mandrel is removed and the remaining upright spacers are used as hardmask fin template(s) 141 to etch the top semiconductor layer and form one or more vertical fins 131. The upright spacers are then removed after the semiconductor vertical fins 131 have been formed.
In one or more embodiments, a protective layer 160 may be formed on the one or more hardmask fin template(s) 141 and one or more vertical fins 131 to protect the vertical fins 131 during subsequent etching processes. The protective layer 160 may cover the hardmask fin templates 141 and vertical fins 131, and fill in spaces between particular vertical fins 131 having a predetermined pitch. In various embodiments, the predetermined pitch may be about twice the intended thickness of the protective layer 160 formed on the vertical fin sidewalls.
In various embodiments, the materials and layers may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), or any of the various modifications thereof, for example plasma-enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), electron-beam physical vapor deposition (EB-PVD), and plasma-enhanced atomic layer deposition (PE-ALD). The depositions may be epitaxial processes, and the deposited material may be crystalline. In various embodiments, formation of a layer may be by one or more deposition processes, where, for example, a conformal layer may be formed by a first process (e.g., ALD, PE-ALD, etc.) and a fill may be formed by a second process (e.g., CVD, electrodeposition, PVD, etc.).
In one or more embodiments, the protective layer 160 may be conformally formed on at least the sidewalls of the vertical fin(s) 131, for example, by ALD, where the thickness of the protective layer may be controlled within a tolerance of the thickness of approximately one monolayer. In various embodiments, the protective layer 160 may be conformally formed on at least the sidewalls of the vertical fin(s) 131 by CVD or a combination of CVD and ALD.
In one or more embodiments, the protective layer 160 may have a thickness, W1, in the range of about 5 nm to about 50 nm, or in the range of about 10 nm to about 30 nm, or in the range of about 15 nm to about 25 nm. The thickness of the protective layer 160 on the sidewall(s) and/or endwall(s) of the vertical fin(s) 131 may form an offset equal to the thickness, W1, where the offset may determine the distance of an unmasked region from a vertical fin 131 for subsequent processing.
In one or more embodiments, the thickness, W1, of the protective layer 160 conformally formed on the vertical fins may be approximately half the distance, D1, between the facing sidewalls of two adjacent vertical fins (D1≤2×W1), where two or more vertical fins may have a pitch predetermined to locate the vertical fins 131 on the same bottom source/drain. In various embodiments, the distance, D1, between the sidewalls of the vertical fin(s) 131 may be in the range of about 10 nm to about 100 nm, or in the range of about 10 nm to about 60 nm, or in the range of about 20 nm to about 50 nm, or in the range of about 30 nm to about 50 nm. In various embodiments, the distance, D1, between the sidewalls of the vertical fin(s) 131 the thickness, W1, of the protective layer 160 conformally formed on the vertical fins may be such that the space between adjacent vertical fins 131 is filled with the protective layer 160, such that the doped layer 120 is pinched off between the particular vertical fins 131. In various embodiments, the thickness, W1, of the protective layer 160 may be greater than ½ of the distance, D1, (W1>½ D1), so a lateral offset of an isolation region may be independent of the distance, D1, between the sidewalls of the vertical fin(s) 131 and the fin pitch.
In one or more embodiments, a distance, D2, may be between the facing sidewalls of two adjacent vertical fins 131, where D2>(2×W1), where two or more vertical fins may have a pitch predetermined to locate the vertical fins 131 on different doped layer regions 121 after formation of an isolation trench 170. In various embodiments, D2 may be approximately twice the thickness, W1, of the conformal protective layer 160 plus the width, D3, of an isolation trench positioned between the two adjacent vertical fins 131, (D2=(2×W1)+D3).
In various embodiments, one or more intervening vertical fin(s) 131 may be removed, for example, by a fin-cut process, to increase the distance between adjacent vertical fins 131, so a distance, D2, is greater than 2×D1. An intervening vertical fin 131 may be removed to create a greater distance between two adjacent vertical fins 131 for forming an isolation trench in the location of the removed vertical fin 131.
In one or more embodiments, an isolation trench 170 may be formed between two adjacent vertical fins 131 having a pitch greater than the pitch of two adjacent vertical fins 131 forming a multi-fin vertical finFET. In various embodiments, the isolation trench 170 may be self-aligned with vertical fins 131 by the conformally deposited protective layer 160, where the thickness of the protective layer 160 determines the position of the isolation trench 170 relative to the adjacent vertical fins.
In one or more embodiments, an isolation trench 170 may be formed by a reactive ion etch (RIE), where a portion of the protective layer 160 on the surface of the doped layer 120 is removed, such that the doped layer 120 forms two doped layer regions 121 separated by the isolation trench 170. The isolation trench 170 may extend into the substrate to electrically separate the doped layer 120 into two doped layer regions 121 that may act as bottom source/drains for a vertical finFET. In various embodiments, one or more isolation trenches may be formed through a doped layer to form two or more doped layer regions.
In various embodiments, adjacent doped layer regions 121 may be separated by the distance, D3, in the range of about 10 nm to about 200 nm, or in the range of about 25 nm to about 100 nm, or in the range of about 40 nm to about 60 nm, where the widths for the isolation trenches may be in the range of about 10 nm to about 200 nm, or in the range of about 25 nm to about 100 nm, or in the range of about 40 nm to about 60 nm. Other widths for the isolation trenches are also contemplated. The widths of the isolation trenches 170 may be the same or different.
In one or more embodiments, a dielectric spacer 181 may be formed in one or more isolation trenches 170. The dielectric spacer 181 may be formed by a blanket deposition that fills in the isolation trenches 170. The dielectric spacer 181 may be separated from vertical fin(s) 131 by the width, W1, of protective layer blocks 161. In various embodiments, the dielectric spacer 181 may extend above the top surface(s) of the protective layer blocks 161 and/or hardmask fin template(s) 141. The excess dielectric spacer material above the top surface(s) may be removed by a planarization process, for example, chemical-mechanical polishing (CMP) after the deposition.
In one or more embodiments, the dielectric spacer 181 may be a nitride, for example, silicon nitride (SiN), or an oxynitride, for example, silicon oxynitride (SiON).
In one or more embodiments, protective layer blocks 161 may be removed from between the vertical fins 131 and hardmask fin template(s) 141, where the protective layer blocks 161 may be removed by a selective dry or wet etch. Removal of the protective layer blocks 161 exposes portions of the doped layer regions 121 below the vertical fin(s) 131.
In one or more embodiments, a bottom spacer 190 may be formed on the doped layer segments, where the bottom spacer 190 may be formed by an anisotropic deposition. In various embodiments, the bottom spacer 190 may be formed by a directional deposition such as a high density plasma (HDP) deposition, which deposits more material on the horizontal surfaces than on the vertical sidewalls. An etchback process may be performed to remove any spacer material formed on the sidewalls of the vertical fins 131. The spacer material remaining on the surface of the doped layer regions 121 between the vertical fin(s) 131 becomes the bottom spacer 190. In various embodiments, the bottom spacer 190 can be formed by filling the trenches with a dielectric material and then removing a portion of the bottom spacer material, and leaving a portion of the dielectric material as the bottom spacer 190.
In various embodiments, the bottom spacer 190 may be a silicon oxide, silicon nitride, silicon oxynitride, SiOCN, SiBCN, etc.
In one or more embodiments, a gate dielectric layer 200 may be formed on the exposed surface(s) of the bottom spacer(s) 190 and the sidewall(s) of one or more vertical fin(s) 131.
In various embodiments, the gate dielectric layer 200 may be a high-K dielectric material that may include, but is not limited to, metal oxides such as hafnium oxide (e.g., HfO2), hafnium silicon oxide (e.g., HfSiO4), hafnium silicon oxynitride (HfwSixOyNz), lanthanum oxide (e.g., La2O3), lanthanum aluminum oxide (e.g., LaAlO3), zirconium oxide (e.g., ZrO2), zirconium silicon oxide (e.g., ZrSiO4), zirconium silicon oxynitride (ZrwSixOyNz), tantalum oxide (e.g., TaO2, Ta2O5), titanium oxide (e.g., TiO2), barium strontium titanium oxide (e.g., BaTiO3—SrTiO3), barium titanium oxide (e.g., BaTiO3), strontium titanium oxide (e.g., SrTiO3), yttrium oxide (e.g., Y2O3), aluminum oxide (e.g., Al2O3), lead scandium tantalum oxide (Pb(ScxTa1-x)O3), and lead zinc niobate (e.g., PbZn1/3Nb2/3O3). The high-k material may further include dopants such as lanthanum and/or aluminum. The stoichiometry of the high-K compounds may vary.
In various embodiments, the gate dielectric layer 200 may have a thickness in the range of about 1.5 nm to about 2.5 nm.
In various embodiments, a work function layer 210 may be formed on the vertical fin(s) 131. The work function layer 210 may be deposited on at least a portion of the bottom spacer 190 and/or gate dielectric layer 200 to form part of a gate structure on the vertical fins 131. The work function layer may be formed by atomic layer deposition (ALD), and/or chemical vapor deposition (CVD).
In various embodiments, the work function layer 210 may be a conductive nitride, including but not limited to titanium nitride (TiN), hafnium nitride (HfN), hafnium silicon nitride (HfSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN); a carbide, including but not limited to titanium carbide (TiC), tantalum carbide (TaC), hafnium carbide (HfC), and combinations thereof. The stoichiometry of the work function layer compounds may vary.
In various embodiments, the work function layer 210 may have a thickness in the range of about 3 nm to about 11 nm, or may have a thickness in the range of about 5 nm to about 8 nm.
In one or more embodiments, a gate metal fill 220 may be formed on the work function layer 210, where the gate metal fill 220 may be a layer conformally deposited or blanket deposited on the work function layer 210. The gate metal fill may be formed by PVD. In various embodiments, the gate metal fill 220 may be tungsten (W), cobalt (Co), or a combination thereof. The gate structure may be recessed to define the gate length of the vertical FinFET. The gate metal fill 220 may form part of a gate structure, where the gate structure may be on a vertical fin 131.
In one or more embodiments, a portion of the gate metal fill 220 may be masked. The top surfaces of the work function layer 210 and the gate dielectric layer 200 may also be covered by a mask. An exposed portion of the gate metal fill 220 may be removed to form a contact gap between the gate metal fill 220 and the dielectric spacer 181. A portion of the work function layer 210 exposed by the removal of the portion of the gate metal fill 220, a portion of the gate dielectric layer 200, and a portion of the bottom spacer 190 may also be removed to extend the contact gap at least to the top surface of the doped layer region 121. The contact gap may extend into the doped layer region 121. The width of the gate metal fill 220 may be reduced to form the gate structure on the vertical fin(s) 131.
In one or more embodiments, a gap liner 225 may be formed at least on the sidewalls of the contact gap. The gap liner 225 may be conformally deposited on the sidewalls of the dielectric spacer 181 and gate metal fill 220 to a predetermined thickness. The gap liner 225 may also be deposited on the exposed surface of the doped layer region 121. The gap liner may electrically isolate the gate metal fill 220 from a subsequently formed metal contact.
In various embodiments, the gap liner 225 may be a silicon nitride (SiN), where the gap liner 225 may be the same material as the dielectric spacer 181 and a different material than the doped layer region 121, such that the doped layer region 121 may act as an etch stop.
In one or more embodiments, at least a portion of the gap liner 225 on the top surface of the doped layer region 121 may be removed to expose the surface of the doped layer region 121. A sacrificial spacer 240 may be formed in the contact gap, where the sacrificial spacer 240 may be formed on a remaining portion of the gap liner 225, and on the surface of the doped layer region 121.
In various embodiments, the sacrificial spacer 240 may be silicon oxide (SiO) and/or carbon doped silicon oxide (SiCO).
In one or more embodiments, the height of the gate metal fill 220, gate dielectric layer 200, and work function layer 210, may be reduced to create a recess between the top surface of a vertical fin 131 and components of the gate structure. The height of the gate metal fill 220, gate dielectric layer 200, and work function layer 210, may be reduced by RIE. In various embodiments, a top spacer 230 may be formed in the recess between the top surfaces of the gate metal fill 220, gate dielectric layer 200, and work function layer 210, where the top spacer electrically isolates the gate structure from the channel formed by the vertical fin 131 and a top source/drain formed on one or more vertical fin(s) 131.
In various embodiments, the top spacer 230 may be a silicon nitride (SiN), where the top spacer 230 may be formed a similar process used to form the bottom spacer 190.
In one or more embodiments, the hardmask fin template(s) 141 may be removed from one or more vertical fin(s) 131, where removal of the one or more hardmask fin template(s) 141 may expose the top surface of one or more vertical fin(s) 131. The hardmask fin template(s) 141 may be removed, for example, by a selective wet etch that leaves the top surfaces of the top spacer(s) 230 and vertical fin(s) 131 exposed.
In various embodiments, a top source/drain 250 may be formed on one or more of the vertical fin(s) 131, where the top source/drain 250 may be epitaxially grown on the top surface of the one or more of the vertical fin(s) 131. The top source/drain 250 may be doped in-situ to form an n-type or a p-type finFET in conjunction with the doping of the doped layer regions 121 forming a bottom source/drain, substrate 110 (e.g., counter-doped well), and/or vertical fin 131.
In various embodiments, the top source/drain 250 may be Si, SiGe, and/or carbon doped Si (Si:C), where the top source/drain 250 and doped layer regions 121 may be doped with boron and/or gallium to form a p-type FET, and phosphorus, arsenic, and/or indium, to form an n-type FET.
In one or more embodiments, a dielectric cover layer 260 may be formed on the top source/drain 250, top spacer 230, and sacrificial spacer 240, where the dielectric cover layer 260 may be an interlayer dielectric (ILD) separating metal contacts and metal-filled vias. In various embodiments, the dielectric cover layer 260 may be a silicon oxide. In a non-limiting example, the dielectric cover layer 260 may be a silicon oxide (SiO) layer deposited on silicon oxide (SiO) sacrificial spacer(s) 240 and silicon nitride dielectric spacer(s) 181, such that the silicon oxide dielectric cover layer 260 and silicon oxide sacrificial spacer(s) 240 may be selectively etched to form one or more contact vias 270.
In one or more embodiments, a mask may be formed, patterned, and developed on the top surface of the dielectric cover layer 260 to expose portions of the dielectric cover layer 260 for subsequent etching. One or more contact vias 270 may be formed in the dielectric cover layer 260 by removing exposed portions of the dielectric cover layer. The contact vias 270 may extend through the dielectric cover layer 260 to the top source/drain(s) 250, doped layer region(s) 121, and/or gate metal fill 220 to form electrical contacts for back end of line (BEOL) connections.
In various embodiments, the contact vias 270 may extend to one or more sacrificial spacer(s) 240, and one or more sacrificial spacer(s) 240 may be selectively removed to form electrical contacts to the doped layer regions 121 forming a bottom source/drain.
In one or more embodiments, a metal contact 280 may be formed in one or more of the contact vias 270, where the metal contacts 280 may be a metal fill deposited in the contact vias 270. The metal contacts 280 may form electrical connections to the doped layer regions 121, the top source/drain 250, and/or the gate metal fill 220.
In various embodiments, the metal contacts 280 may be tungsten (W), copper (Cu), molybdenum (Mo), cobalt (Co), nickel (Ni), titanium (Ti), or a combination thereof.
In various embodiments, a conductive liner 285, such as TiN, TaN, may be formed on the sidewalls of the contact vias 270 prior to formation of the metal contacts 280. The conductive liner 285 may suppress electro-migration and/or diffusion of the metal contact material.
In various embodiments, the dielectric cover layer 260 may act as an interlayer dielectric (ILD) to electrically isolate the metal contacts 280 formed in each of the contact vias 270. The ILD in conjunction with the dielectric spacer 181 may physically and electrically separate neighboring vertical finFETs.
In various embodiments, the gap liner 225 may physically and electrically separate a metal contact 280 formed in a contact via 270 from a gate metal fill 220, where the gap liner 225 may prevent an electrical short between an electrical contact to a bottom source/drain and an adjacent gate structure.
In various embodiments, two or more contact vias 270 and metal contacts 280 may be formed to doped layer regions 121 to increase the contact area between the electrical contact to a bottom source/drain, and thereby reduce the resistance between the metal contacts 280 and the bottom source/drain of a finFET device.
In one or more embodiments, a gate contact 289 may be formed by a metal contact 280 to a gate metal fill 220 (where the gate contact 289 is behind the plane shown in
In various embodiments, the dielectric cover layer 260 in conjunction with the dielectric spacer 181 may physically and electrically separate the contact vias 270 and metal contacts 280, including the gate contact 289.
It is to be understood that the present invention is described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps may be varied within the scope of the present invention.
It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
The present embodiments may include a design for an integrated circuit chip, which may be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer may transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
Methods as described herein may be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
Reference in the specification to “one embodiment” or “an embodiment” of the present principles, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the FIGs. will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGs. For example, if the device in the FIGs. is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.
While exemplary embodiments have been shown for a particular device, it should be understood that a plurality of such devices may be arranged and/or fabricated on a substrate to form integrated devices that may be integrated onto a substrate, for example through very large scale integration to produce complex devices such a central processing units (CPUs) and application specific integrated circuits (ASICs). The present embodiments may be part of a device or circuit, and the circuits as described herein may be part of a design for an integrated circuit chip.
Having described preferred embodiments of a method and device (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.
Claims
1. A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, comprising:
- forming a gate dielectric layer on a vertical fin and a bottom spacer on a doped layer region, wherein the vertical fin and the doped layer region are between a pair of dielectric spacers;
- forming a work function layer on the gate dielectric layer;
- forming a gate metal fill on the work function layer;
- removing a portion of the gate metal fill, work function layer, gate dielectric layer, and bottom spacer to form a contact gap that exposes a top surface of the doped layer region; and
- forming a gap liner on the top surface of the doped layer region, sidewalls of the pair of dielectric spacers, and a sidewall of the gate metal fill.
2. The method of claim 1, further comprising removing at least a portion of the gap liner on the top surface of the doped layer region.
3. The method of claim 2, further comprising forming a sacrificial spacer in the contact gap on a remaining portion of the gap liner and on the surface of the doped layer region.
4. The method of claim 3, further comprising forming a recess between the top surface of the vertical fin and the gate metal fill, work function layer, and gate dielectric layer, and forming a top spacer in the recess.
5. The method of claim 4, further comprising forming a top source/drain on the vertical fin.
6. The method of claim 5, further comprising forming a dielectric cover layer on the top source/drain, top spacer, and sacrificial spacer.
7. The method of claim 6, further comprising removing a portion of the dielectric cover layer, and removing the sacrificial spacer to form a contact via.
8. The method of claim 7, further comprising forming a metal contact in the contact via.
9. The method of claim 8, wherein the gap liner electrically isolates the gate metal fill from the metal contact.
10. A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, comprising:
- forming a gate dielectric layer on a vertical fin and a bottom spacer on a doped layer region, wherein the vertical fin and the doped layer region are between a pair of dielectric spacers;
- forming a work function layer on the gate dielectric layer;
- forming a gate metal fill on the work function layer;
- removing a portion of the gate metal fill, work function layer, gate dielectric layer, and bottom spacer to form a contact gap that exposes a top surface of the doped layer region;
- forming a gap liner on the top surface of the doped layer region, sidewalls of the pair of dielectric spacers, and a sidewall of the gate metal fill by a conformal deposition; and
- removing at least a portion of the gap liner on the top surface of the doped layer region.
11. The method of claim 10, further comprising forming a sacrificial spacer in the contact gap on a remaining portion of the gap liner and on the surface of the doped layer region.
12. The method of claim 11, wherein the sacrificial spacer is selected from the group consisting of silicon oxide (SiO) and carbon doped silicon oxide (SiCO).
13. The method of claim 12, wherein the gap liner is silicon nitride (SiN).
14. The method of claim 13, wherein the material of the bottom spacer is selected from the group consisting of a silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), and silicon borocarbonitride (SiBCN).
15. A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, comprising:
- forming a gate dielectric layer on a pair of vertical fins and a bottom spacer on a doped layer region, wherein the pair of vertical fins and the doped layer region are between a pair of dielectric spacers;
- forming a work function layer on the gate dielectric layer;
- forming a gate metal fill on the work function layer;
- removing a portion of the gate metal fill, work function layer, gate dielectric layer, and bottom spacer to form a contact gap that exposes a top surface of the doped layer region; and
- forming a gap liner on the top surface of the doped layer region, sidewalls of the pair of dielectric spacers, and a sidewall of the gate metal fill.
16. The method of claim 15, wherein the pair of vertical fins are separated by a distance in the range of about 10 nm to about 100 nm.
17. The method of claim 15, wherein the doped layer region is silicon germanium (SiGe) doped with boron to form a p-type FET.
18. The method of claim 17, further comprising forming a single top source/drain on the pair of vertical fins, wherein the top source/drain is silicon germanium (SiGe) doped with boron to form a p-type FET.
19. The method of claim 18, wherein the dielectric spacer is silicon nitride (SiN) or silicon oxynitride (SiON).
20. The method of claim 18, further comprising forming a dielectric cover layer on the top source/drain and sacrificial spacer, and removing a portion of the dielectric cover layer, and removing the sacrificial spacer to form a contact via.
Type: Application
Filed: Nov 13, 2019
Publication Date: Mar 12, 2020
Inventors: Kangguo Cheng (Schenectady, NY), Xin Miao (Guilderland, NY), Wenyu Xu (Albany, NY), Chen Zhang (Guilderland, NY)
Application Number: 16/682,687
