SINGLE DIFFUSION CUT FOR GATE STRUCTURES
The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures composed of semiconductor material; a plurality of replacement gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of replacement gate structures; and a single diffusion break between the diffusion regions of the adjacent replacement gate structures, the single diffusion break being filled with an insulator material. In a first cross-sectional view, the single diffusion break extends into the semiconductor material and in a second cross-sectional view, the single diffusion break is devoid of semiconductor material of the plurality of fin structures.
The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture.
BACKGROUNDAs semiconductor processes continue to scale downwards, e.g., shrink, the desired spacing between features (i.e., the pitch) also becomes smaller. To this end, in the smaller technology nodes it becomes ever more difficult to fabricate features due to the critical dimension (CD) scaling and process capabilities.
For example, in the fabrication of FinFET structures, single diffusion breaks become very attractive in standard cell scaling. The processes for fabricating the single diffusion breaks, though, are very challenging in advanced technologies. By way of illustration, conventionally, multiple Rx regions in a semiconductor integrated circuit include arrays of parallel extending fins having distal ends abutting the edges of each Rx region. The fin arrays are terminated by dummy gates, which extend laterally across the distal ends of the fins at the edges of the Rx regions. The dummy gates are used to induce symmetrical epitaxial growth of source/drain regions (S/D regions) on the end portions of the fins located between the dummy gates and adjacent active gates.
To fabricate the single diffusion break, a deep trench undercut adjacent to the source and drain epitaxial regions is provided by removing the dummy gate structure (poly material). The deep trench etch undercut damages or removes portions of the epitaxial source and drain regions. This results in smaller source/drain epitaxial volume and electrical contact area compared to that of the source and drain regions located between active gates. The smaller source and drain region volume and contact area can lead to greater contact resistance and degrade device performance.
SUMMARYIn an aspect of the disclosure, a structure comprises: a plurality of fin structures composed of semiconductor material; a plurality of replacement gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of replacement gate structures; and a single diffusion break between the diffusion regions of the adjacent replacement gate structures, the single diffusion break being filled with an insulator material. In a first cross-sectional view, the single diffusion break extends into the semiconductor material and in a second cross-sectional view, the single diffusion break is devoid of semiconductor material of the plurality of fin structures.
In an aspect of the disclosure, a structure comprises: a substrate material; a plurality of metal gate structures on the substrate material and comprising sidewall spacers, metal material and diffusion regions; and a single diffusion break structure between adjacent metal gate structures of the plurality of metal gate structures, the single diffusion break structure extending into the substrate in a first cross-section and being devoid of the substrate material in a second cross-section. The first cross-section is perpendicular to the plurality of metal gate structures and the second cross-section is parallel to a longitudinal axis of the plurality of metal gate structures.
In an aspect of the disclosure, the method comprises: forming a plurality of fin structures from semiconductor material; forming dummy gate structures over the plurality of fin structures; forming diffusion regions adjacent to the dummy gate structures; removing a portion of at least one of the plurality of dummy gate structures; forming single diffusion break structure comprising: forming a trench in the semiconductor material aligned with the removed portion of the at least one of the plurality of dummy gate structures and adjacent to the diffusion regions, while also removing selected fin structures; and filling the trench with insulator material; and replacing the dummy gate structures with replacement gate structures.
The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.
The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. More specifically, the present disclosure provides a single diffusion cut process for advanced FinFET technologies. Advantageously, the single diffusion cut process eliminates damage and/or defects to epitaxial source/drain regions during replacement metal gate processes, e.g., during deep trench etch processes to remove the dummy gate material. Accordingly, by implementing the processes described herein, device performance can be maintained even at smaller technology nodes, e.g., 10 nm technology node and smaller.
The structures of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the structures of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the structures use three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.
The fin structures 12 can be fabricated using conventional patterning processes including, e.g., sidewall imaging transfer (SIT) techniques. In an example of a SIT technique, a mandrel material, e.g., SiO2, is deposited on the substrate material 14 using conventional chemical vapor deposition (CVD) processes. A resist is formed on the mandrel material, and exposed to light to form a pattern (openings). A reactive ion etching (RIE) is performed through the openings to form the mandrels. In embodiments, the mandrels can have different widths and/or spacing depending on the desired dimensions between the fin structures 12. Spacers are formed on the sidewalls of the mandrels which are preferably material that is different than the mandrels, and which are formed using conventional deposition processes known to those of skill in the art. The mandrels are removed or stripped using a conventional etching process, selective to the mandrel material. An etching is then performed within the spacing of the spacers to form the sub-lithographic features. Due to the etching process, the fin structures 12 can have a tapered profile as shown in
Dummy gate structures 16 extend orthogonally over the fin structures 12. In embodiments, the dummy gate structures 16 are composed of polysilicon material 16a and capping material 24, e.g., SiN, both of which are deposited over the fin structures 12 and patterned using conventional lithography and etching processes such that no further explanation is required herein for an understanding of the formation of the dummy gate structures 16. A sidewall spacer material 18 is deposited and patterned over the dummy gate structures 16. In embodiments, the sidewall spacer material 18 is a low-k dielectric material deposited by a conventional CVD process, followed by an anisotropic etching process to expose the upper surface of the polysilicon material of the dummy gate structures 16.
As shown in
In
Referring still to
As shown in
The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims
1. A structure comprising:
- a plurality of fin structures composed of semiconductor material;
- a plurality of replacement gate structures extending over the plurality of fin structures;
- a plurality of diffusion regions adjacent to the each of the plurality of replacement gate structures; and
- a single diffusion break between the diffusion regions of the adjacent replacement gate structures, the single diffusion break being filled with an insulator material, wherein
- in a first cross-sectional view, the single diffusion break extends into the semiconductor material,
- in a second cross-sectional view, the single diffusion break is devoid of semiconductor material of the plurality of fin structures, and
- a replacement gate cut along a longitudinal axis of the adjacent replacement gate structures which includes the insulator material of the single diffusion break and which isolates the adjacent replacement gate structures along their longitudinal axis from one another.
2. The structure of claim 1, wherein the insulator material is nitride material.
3. The structure of claim 2, wherein the single diffusion break is a cut in the semiconductor material and cross-section of fin structures that separates the diffusion regions of the adjacent plurality of replacement gate structures.
4. (canceled)
5. The structure of claim 1, wherein the replacement gate cut is filled with a same material as the single diffusion break.
6. The structure of claim 5, wherein the same material is nitride material.
7. The structure of claim 1, wherein the replacement gate cut is lined with a sidewall spacer.
8. The structure of claim 1, wherein the first cross-sectional view is perpendicular to the plurality of replacement gate structures and the second cross-sectional view is parallel to a longitudinal axis of the plurality of replacement gate structures.
9. A structure comprising:
- a substrate material;
- a plurality of metal gate structures on the substrate material and comprising sidewall spacers, metal material and diffusion regions;
- a single diffusion break structure between adjacent metal gate structures of the plurality of metal gate structures, the single diffusion break structure being filled with insulator material and extending into the substrate in a first cross-section and being devoid of the substrate material in a second cross-section, and
- a gate cut along a longitudinal axis of the plurality of metal gate structures which includes the insulator material that isolates the adjacent metal gate structures along their longitudinal axis from one another,
- wherein the first cross-section is perpendicular to the plurality of metal gate structures and the second cross-section is parallel to a longitudinal axis of the plurality of metal gate structures.
10. (canceled)
11. (canceled)
12. The structure of claim 9, wherein the gate cut and the single diffusion break are composed of nitride material.
13. A method comprising:
- forming a plurality of fin structures from semiconductor material;
- forming dummy gate structures over the plurality of fin structures;
- forming diffusion regions adjacent to the dummy gate structures;
- removing a portion of at least one of the plurality of dummy gate structures and fin structures while an insulator layer over remains protected by a capping material and a spacer material;
- forming of a gate cut in the insulator layer along a longitudinal axis of the dummy gate structures;
- forming single diffusion break structure comprising: forming a trench in the semiconductor material aligned with the removed portion of the at least one of the plurality of dummy gate structures and adjacent to the diffusion regions, while also removing selected fin structures; and filling the trench with insulator material; and
- filling the gate cut with the insulator material while filling the trench of the single diffusion break structure with the insulator material; and
- replacing the dummy gate structures with replacement gate structures.
14. The method of claim 13, further comprising forming the spacer material about the dummy gate structures which remain after the replacement with the replacement gate structures.
15. The method of claim 14, wherein the insulator layer is an oxide material and the capping material is a blocking material over the oxide material on the diffusion regions, formed prior to the forming of the trench.
16. The method of claim 15, wherein the blocking material is Al2O3.
17. The method of claim 16, further comprising replacing the oxide material and the blocking material over the diffusion regions with contact material, after filling the trench with insulator material.
18. The method of claim 17, wherein the gate cut in the dummy gate structures remains after replacement with the replacement gate structures.
19. The method of claim 18, wherein the replacement gate structures are metal gate structures.
20. The method of claim 18, wherein the gate cut is filled with the insulator material.
21. The structure of claim 1, wherein:
- the insulator material of the single diffusion break abuts and directly contacts a liner material along its sidewalls extending from directly above the semiconductor material;
- the insulator material of the replacement gate cut abuts and directly contacts the liner material; and
- the replacement gate structures abut and directly contact the liner material; and
- further comprising: an insulator layer which is positioned and structured as an isolation region for the replacement gate structures, the insulator layer being in direct contact with the liner material and the liner material being located between the insulator material and the insulator layer; and contact material in direct contact with the diffusion regions and abutting and directly contacting the liner material.
22. The structure of claim 9, wherein:
- the insulator material of the single diffusion break structure abuts and directly contacts a liner material along its sidewalls extending from directly above the substrate material;
- the insulator material of the gate cut abuts and directly contacts the liner material; and
- the metal gate structures abut and directly contact the liner material; and
- further comprising: an insulator layer which is positioned and structured as an isolation region for the gate structures, the insulator layer being in direct contact with the liner material and the liner material being located between the insulator material and the insulator layer; and contact material in direct contact with the diffusion regions and abutting and directly contacting the liner material.
Type: Application
Filed: Nov 29, 2018
Publication Date: Jun 4, 2020
Inventors: Guowei XU (Ballston Lake, NY), Hui ZANG (Guilderland, NY), Ruilong XIE (Niskayuna, NY), Haiting WANG (Clifton Park, NY)
Application Number: 16/204,506