ELECTRO-OPTICAL MODULATOR USING WAVEGUIDES WITH OVERLAPPING RIDGES
An optical modulator may include a lower waveguide, an upper waveguide, and a dielectric layer disposed therebetween. When a voltage potential is created between the lower and upper waveguides, these layers form a silicon-insulator-silicon capacitor (also referred to as SISCAP) guide that provides efficient, high-speed optical modulation of an optical signal passing through the modulator. In one embodiment, at least one of the waveguides includes a respective ridge portion aligned at a charge modulation region which may aid in confining the optical mode laterally (e.g., in the width direction) in the optical modulator. In another embodiment, ridge portions may be formed on both the lower and the upper waveguides. These ridge portions may be aligned in a vertical direction (e.g., a thickness direction) so that ridges overlap which may further improve optical efficiency by centering an optical mode in the charge modulation region.
This application is a divisional of co-pending U.S. patent application Ser. No. 15/615,290, filed Jun. 6, 2017 which claims benefit of U.S. patent application Ser. No. 14/248,081, filed Apr. 8, 2014 which issued on Sep. 19, 2017 as U.S. Pat. No. 9,766,484 claiming benefit of U.S. provisional patent application Ser. No. 61/931,314, filed Jan. 24, 2014. The aforementioned related patent applications are herein incorporated by reference in their entirety.
TECHNICAL FIELDEmbodiments presented in this disclosure generally relate to optical modulation and, more specifically, to silicon-based electro-optical modulators.
BACKGROUNDMany electro-optic devices exploit the free carrier dispersion effect to change both the real and imaginary parts of the refractive index. This exploitation is used since the unstrained pure crystalline silicon does not exhibit a linear electro-optic (Pockels) effect, and the refractive index changes due to the Franz-Keldysh effect and Kerr effect are very weak. Phase modulation in a specific region of optical devices, such as Mach-Zehnder modulators, total-internal-reflection (TIR)-based structures, cross switches, Y-switches, ring resonators and Fabry-Perot resonators, may be used to modulate the output intensity.
Free carrier concentration in electro-optic devices can be varied by injection, accumulation, depletion or inversion of carriers. Most of such devices investigated to date present some common features: they require long interaction lengths (for example, 5-10 mm) and injection current densities higher than 1 kA/cm3 in order to obtain a significant modulation depth. Long interaction lengths are undesirable in order to achieve high levels of integration and miniaturization for fabricating low-cost compact device arrangements. High current densities may induce unwanted thermo-optic effects as a result of heating the structure and will, indeed, cause an opposite effect on the real refractive index change relative to that associated with free carrier movement, thus reducing its effectiveness.
So that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.
DESCRIPTION OF EXAMPLE EMBODIMENTS OverviewOne embodiment presented in this disclosure is an optical device that includes a first silicon waveguide disposed on a dielectric substrate, the first silicon waveguide comprising a first ridge extending in a direction of an optical path. The optical device includes a dielectric layer having a lower surface disposed on an upper surface of the first ridge and a second silicon waveguide defining a first surface disposed on an upper surface of the dielectric layer opposite the lower surface of the dielectric layer. The second silicon waveguide also defines a second surface opposite the first surface where the second surface includes a second ridge disposed thereon, the second ridge extending in a direction of the optical path. Moreover, the second ridge at least partially overlaps both the dielectric layer and the first ridge and the first silicon waveguide is doped a first conductivity type and the second silicon waveguide is doped a second, different conductivity type. The optical device includes a first electrical contact coupled to the first silicon waveguide and a second electrical contact coupled to the second silicon waveguide.
Another embodiment described herein is a method for forming an optical device. The method includes forming a first silicon waveguide on a dielectric substrate where the first silicon waveguide includes a first ridge extending in a direction of an optical path, forming a dielectric layer on the first ridge, and forming a second silicon waveguide disposed on an upper surface of the dielectric layer opposite a lower surface of the dielectric layer contacting the first ridge. The second silicon waveguide defines a first surface facing the upper surface and a second surface opposite the first surface where the second surface includes a second ridge extending in the direction of the optical path. Moreover, the second ridge at least partially overlaps both the dielectric layer and the first ridge and the first silicon waveguide is doped a first conductivity type and the second silicon waveguide is doped a second, different conductivity type. The method includes coupling a first electrical contact to the first silicon waveguide and coupling a second electrical contact to the second silicon waveguide.
Another embodiment described herein is an optical device that includes a first waveguide disposed on a substrate where the first waveguide includes a first ridge extending in a direction of an optical path and a second waveguide defining a first surface disposed above an upper surface of the first ridge opposite a lower surface of the first waveguide contacting the substrate. The second waveguide also defines a second surface opposite the first surface where the second surface includes a second ridge extending in a direction of the optical path. Moreover, the second ridge at least partially overlaps the first ridge in a direction perpendicular to the direction of the optical path and the first waveguide is doped a first conductivity type and the second waveguide is doped a second, different conductivity type. The optical device includes a first electrical contact coupled to the first waveguide and a second electrical contact coupled to the second waveguide.
Example EmbodimentsAn optical modulator may include a lower waveguide, an upper waveguide, and a dielectric layer disposed therebetween. When a voltage potential is created between the lower and upper waveguides, these layers form a silicon-insulator-silicon capacitor (also referred to as SISCAP) guide that provides efficient, high-speed optical modulation of an optical signal passing through the modulator. In one embodiment at least one of the waveguides includes a respective ridge portion (referred to as a ridge or ribbed waveguide) aligned at a charge modulation region. This ridge portion aids in confining the optical mode laterally (e.g., in the width direction) in the optical modulator which may result in more light of the optical mode passing within the charge modulation and improving the efficiency of the modulator.
In another embodiment, ridge portions may be formed on both the lower and the upper waveguides. These ridge portions may be aligned in a vertical direction (e.g., a thickness direction) so that ridges overlap. If the greatest intensity of the optical signal is approximately in the middle of the optical mode, using two aligned ridge portions centers the optical mode in the middle of the charge modulation region which may result in the greatest intensity of the optical signal falling within the charge modulation region.
The thickness of the surface layer 105 may range from less than 100 nanometers to greater than a micron. More specifically, the surface layer 105 may be between 100-300 nanometers thick. The thickness of the insulation layer 110 may vary depending on the desired application. The thickness of the insulation layer 110 may directly depend on the size of the mode being coupled to the SOI device 100 and the desired efficiency. As such, the thickness of insulation layer 110 may range from less than one micron to tens of microns. The thickness of the substrate 115 may vary widely depending on the specific application of the SOI device 100. For example, the substrate 115 may be the thickness of a typical semiconductor wafer (e.g., 100-700 microns) or may be thinned and mounted on another substrate.
For optical applications, the silicon surface layer 105 and insulation layer 110 (e.g., silicon dioxide, silicon nitride, and the like) may provide contrasting refractive indexes that vertically confine an optical signal in a waveguide in the surface layer 105. In a later processing step, the surface layer 105 of the SOI device 100 may be etched to form one or more silicon waveguides. Because silicon has a high refractive index compared to an insulator such as silicon dioxide, the optical signal remains primarily in the waveguide as it propagates across the surface layer 105.
Ridge Waveguides for Improved Optical Mode Confinement and Modulation EfficiencyThe gate dielectric layer 210 establishes a charge modulation region or charge accumulation region shown by the dashed box where free carriers (e.g., electrons and holes) flow into and out of the p-doped and n-doped waveguides 205 and 215. Doing so creates an active region (defined by WACTIVE) where the switching function associated with the modulator 200 (e.g., switching speeds above 1 Gb/s) can be controlled by a voltage potential across the gate dielectric layer 210. In one embodiment, the voltage potential is used to alter the phase of the optical signal propagating through the modulator as in, for example, a Mach-Zehnder interferometers (MZI). However, the modulators described herein may also be used in other types of devices such as ring resonators, Fabry-Perot cavities, etc.
The gate dielectric layer 210 may be referred to as either “gate dielectric” or “gate oxide” where it is to be understood that an oxide is only an exemplary form of a dielectric that may be used in the modulator device. The gate dielectric layer 210 may comprise any material that allows for fast charging/discharging of the free carries (e.g., enables switching speeds greater than or equal to 1 Gb/s). A non-limiting list of suitable materials include hafnium oxide, oxynitride, bismuth oxide, silicon nitride, silicon oxide, and combinations of these materials. Furthermore, using high-K dielectric materials as the gate dielectric provide higher capacitance and greater charge densities over using dielectrics with lower dielectric constants (assuming same thickness and voltage potential). For example, hafnium oxide and silicon nitride (high-K dielectrics) have higher dielectric constants than silicon dioxide, and thus, enable greater charge densities across the gate dielectric layer relative to using silicon dioxide. Using the higher voltages may increase the modulation efficiency—i.e., the amount the optical signal is phase shifted relative to the applied voltage.
Although the Figures described herein illustrate placing a gate dielectric layer 210 between the opposite doped waveguides, this is not a requirement. For all the embodiments described herein, the modulators may still perform optical modulation if the gate dielectric layer 210 is omitted and the two waveguides directly contact to form a PN junction. In this example, the PN junction establishes the charge modulation region where the free carriers flow into and out of the waveguides. However, including the gate dielectric layer 210 may improve the efficiency of the optical modulation.
As shown, the lower waveguide 205 is doped N-type while the upper waveguide 215 is doped P-type. However, for all the embodiments where the dopant type is specified, the dopant types may be reversed—e.g., the lower waveguide 205 may be doped P-type while the upper waveguide 215 is N-type. Furthermore, the waveguides 205 and 215, which serve as electrodes for the capacitive structure of the modulator 200, may be silicon based. For example, the material of the waveguides 205, 215 may include strained silicon, SixGe1-x, substantially single crystal silicon (i.e., crystalline silicon), polycrystalline silicon, and combinations thereof. In one embodiment, because of process constraints that will be discussed later, the lower waveguide 205 may include crystalline silicon while the upper waveguide 215 may be polycrystalline silicon. However, in other embodiments, both waveguides 205 and 215 may be made from crystalline silicon or polycrystalline silicon.
A width of the waveguides 205 and 215 may be selected to keep electrical contacts 225, which may be metallic or formed from silicide, and vias 220 out of the optical mode. Because electrically conductive materials have a deleterious effect on the optical modulation, the waveguides 205 may be designed such that any conductive contacts are sufficiently outside the boundaries of the optical mode. Moreover, as shown in
In one embodiment, the width of the active region (i.e., the width of the gate dielectric layer 210) is less than a micron, and more specifically, less than half a micron. The thickness of the waveguides 205 and 215 (excluding the ridge portions 240A and 240B) may range between 50-200 nanometers. In one embodiment, to center the greatest intensity of the light in the optical mode in the charge modulation region, the respective thicknesses of the waveguides 205 and 215 are the same. The thickness of the gate dielectric layer 210 may range from 20 nanometers to 1 or 2 nanometers.
Each waveguide 205, 215 includes a respective ridge portion 240 (referred to as ridge or ribbed waveguides) aligned at the charge modulation region. In addition to the ridge portions being aligned, the ridge portions may be centered on the respective waveguides 205, 215 although this is not a requirement. The ridge portions 240A-B aid in confining the optical mode laterally (e.g., in the width direction) in the modulator 200. As shown, the lower ridge portion 240A is surrounded on two sides by the dielectric material 230 which confines the optical mode near the charge modulation region because of the different refractive indexes associated with the material of the dielectric 230 and the waveguide 205. If the ridge portion 240A was omitted and the bottom portion of the lower waveguide 205 directly contacted the gate dielectric layer 210, the optical mode may spread out laterally within the lower waveguide 205 more so than what is illustrated in
Furthermore, adding the ridge portion 240B to the upper waveguide 240B also may improve the efficiency of the modulator 200 relative to using only the ridge portion 240A. In the SISCAP design shown, the greatest intensity of the optical signal is approximately in the middle of the optical mode. Without the upper ridge 240B, the center of the optical mode may be below the gate dielectric layer 210. Assuming that the thicknesses of the ridge portions 240A-B are the same, in modulator 200, the center of the optical mode is near or proximate to the gate dielectric layer 210. This results in the greatest intensity of the optical signal falling within the charge modulation region. Stated differently, although adding the ridge portion 240B may decrease the vertical confinement of the optical mode, the ridge portion 240B aligns the optical mode such that the greatest intensity of the optical signal is within the charge modulation region thereby improving efficiency.
In
Assuming the waveguides in modulator 250 have the same width as the waveguides in the modulator where the ends of the waveguides overlap, the electrical resistance between the electrical connections to the capacitance CGATE is only half as long in modulator 250 relative to the modulator where the ends of the waveguides overlap. Furthermore, because the resistances RP1/RP2 and RN1/RN2 are in parallel (assuming the voltage on both electrical contacts of a waveguide is the same), this also halves the resistance between the electrical connection and the dielectric layer 210 which forms the capacitance CGATE. As such, the resistance of the modulator 250 between the electrical connections and the gate dielectric layer 210 may be one fourth the corresponding resistance for the modulator where the ends of the waveguides overlap. This may result in a reduction of the total RC constant of modulator 250 which may increase the modulation bandwidth of modulator 250 relative to the modulator where the waveguide ends overlap.
Moreover, for clarity, some of the modulators illustrated in the figures do not show the P and N doping schemes and the conductive contacts and/or vias used to connect the waveguides to a modulation voltage. For example, the doping scheme for the waveguides and the electrical connections shown in
In the modulator 350 shown in
Modulator 300 of
Although modulators 300 and 350 are discussed specifically in relationship to
In
In
Although
In
The upper waveguide 215 may also be doped to the desired conductivity type. This may occur either as the silicon-based material is deposited onto the modulator (e.g., the silicon-based material already includes the desired concentration of the dopant—in-situ doping) or done separately in a later processing step. Moreover, the dopant concentration may be uniform throughout the upper waveguide 215 or may vary as shown in
In
Modulator 500 may be formed using the process shown in
As shown in
Because of the added nitride layer 815, the thickness of ridge 820 may be smaller than the thickness of a ridge 825 in the lower waveguide 505. In one embodiment, the total thickness of the nitride layer 815 (including the ridge 820) and the upper waveguide 615 (shown as TN) is approximately equal to the thickness of the lower waveguide 505 that includes the ridge 825 (shown as TR). Doing so may center the optical mode within the charge modulation region as explained above.
In
Alternatively, to fabricate modulator 800 in
Alternatively, to fabricate modulator 850 in
In
In
In
The u-shape interface between the mask 1400 and layer 1420 forms as a result of oxidizing the silicon layer 105 to the two layers: waveguide 1405 and silicon dioxide layer 1420 where the combined thickness of these layers is thicker than the original silicon layer 105 shown in
In
In another embodiment, the upper waveguide 1415 is further processed to have a ridge structure on its top surface. For example, the upper waveguide 1415 may have a top surface similar to the top surface of the upper waveguide 205 in
Although not shown, the structure in
The flowchart and block diagrams in the Figures illustrate the architecture, functionality and operation of possible implementations of systems, methods and computer program products according to various embodiments. In this regard, each block in the flowchart or block diagrams may represent a module, segment or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In view of the foregoing, the scope of the present disclosure is determined by the claims that follow.
Claims
1. A method for forming an optical device, the method comprising:
- forming a first waveguide on a dielectric substrate, the first waveguide comprising a first ridge projecting in a first direction from the dielectric substrate and extending in a second direction of an optical path;
- forming a dielectric layer on the first ridge; and
- forming a second waveguide on an upper surface of the dielectric layer opposite a lower surface of the dielectric layer contacting the first ridge, the second waveguide defining a first surface facing the upper surface and a second surface opposite the first surface, wherein the second surface comprises a second ridge projecting in the first direction from the second surface and extending in the second direction of the optical path, wherein the second ridge at least partially overlaps both the dielectric layer and the first ridge, and wherein the first waveguide is doped a first conductivity type and the second waveguide is doped a second, different conductivity type.
2. The method of claim 1, wherein respective widths of the first and second ridges in a direction perpendicular to the direction of the optical path are equal.
3. The method of claim 1, further comprising, after forming the dielectric layer and before forming the second waveguide:
- depositing dielectric material; and
- planarizing the dielectric material to expose the upper surface of the dielectric layer, whereby an upper surface of the dielectric material is co-planar with the upper surface of the dielectric layer.
4. The method of claim 1, wherein the first waveguide comprises raised wings, wherein the first ridge is arranged between the raised wings, and wherein a dielectric material is disposed between the raised wings and the first ridge.
5. The method of claim 1, wherein forming the dielectric layer comprises thermally growing the dielectric layer from a material of the first waveguide, wherein the dielectric layer is silicon dioxide.
6. The method of claim 1, further comprising:
- coupling a first electrical contact to the first waveguide; and
- coupling a second electrical contact to the second waveguide.
7. The method of claim 1, wherein the second waveguide comprises a u-shaped waveguide, defining a cavity between a first wing, a second wing, and the second ridge, wherein the second ridge is arranged between the first and second wings on a different plane from the first and second wings, and wherein a dielectric material is disposed between the first and second wings and the second ridge in the cavity.
8. The method of claim 1, wherein the second ridge comprises a different material than a remaining portion of the second waveguide.
9. A method for forming an optical device, the method comprising:
- forming a first waveguide on a dielectric substrate, the first waveguide extending in a first direction of an optical path;
- forming a dielectric layer on the first waveguide, wherein the dielectric layer extends in a second direction from the first waveguide perpendicular to the optical path according to a first height and a second height that is different from the first height; and
- depositing a second waveguide on an upper surface of the dielectric layer opposite a lower surface of the dielectric layer contacting the first waveguide, the second waveguide defining a u-shape according to the first height and the second height to define a ridge that at least partially overlaps both the dielectric layer and the first waveguide, wherein the second waveguide extends in the first direction of the optical path, and wherein the first waveguide is doped a first conductivity type and the second waveguide is doped a second, different conductivity type.
10. The method of claim 9, wherein forming the first waveguide further comprises:
- forming a lower ridge that extends in the second direction from the dielectric substrate, wherein the lower ridge at least partially overlaps with the ridge of the second waveguide.
11. The method of claim 10, wherein respective widths of the ridge of the second waveguide and the lower ridge in a direction perpendicular to the direction of the optical path are equal.
12. The method of claim 9, wherein forming the dielectric layer comprises thermally growing the dielectric layer from a material of the first waveguide, wherein the dielectric layer is silicon dioxide.
13. The method of claim 9, further comprising:
- coupling a first electrical contact to the first waveguide; and
- coupling a second electrical contact to the second waveguide.
14. The method of claim 9, wherein the u-shape defined by the second waveguide defines a cavity between a first wing of the second waveguide and a second wing of the second waveguide, wherein the ridge is positioned between the first wing and the second wing.
15. A method for forming an optical device, the method comprising:
- forming a first waveguide on a dielectric substrate, the first waveguide comprising a first ridge projecting in a first direction from the dielectric substrate and extending in a second direction of an optical path;
- forming a dielectric layer on the first ridge; and
- forming a second waveguide on an upper surface of the dielectric layer opposite a lower surface of the dielectric layer contacting the first ridge, the second waveguide defining a first surface facing the upper surface and a second surface opposite the first surface, wherein the second ridge at least partially overlaps both the dielectric layer and the first ridge, and wherein the first waveguide is doped a first conductivity type and the second waveguide is doped a second, different conductivity type.
16. The method of claim 15, wherein the second surface comprises a second ridge projecting in the first direction from the second surface and extending in the second direction of the optical path.
17. The method of claim 15, wherein respective widths of the first and second ridges in a direction perpendicular to the direction of the optical path are equal.
18. The method of claim 15, further comprising, after forming the dielectric layer and before forming the second waveguide:
- depositing dielectric material; and
- planarizing the dielectric material to expose the upper surface of the dielectric layer, whereby an upper surface of the dielectric material is co-planar with the upper surface of the dielectric layer.
19. The method of claim 15, wherein the first waveguide comprises raised wings, wherein the first ridge is arranged between the raised wings, and wherein a dielectric material is disposed between the raised wings and the first ridge.
20. The method of claim 15, further comprising:
- coupling a first electrical contact to the first waveguide; and
- coupling a second electrical contact to the second waveguide.
Type: Application
Filed: Feb 12, 2020
Publication Date: Jun 11, 2020
Patent Grant number: 11226505
Inventors: Donald ADAMS (Rochester, NY), Prakash B. GOTHOSKAR (Allentown, PA), Vipulkumar PATEL (Breinigsville, PA), Mark WEBSTER (Bethlehem, PA)
Application Number: 16/789,317