Patents by Inventor Mark Webster

Mark Webster has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10378599
    Abstract: A brake rotor comprising a brake pad wear surface; a hat surface; and a decorative insert comprising an insert material, the decorative insert disposed on the brake pad wear surface, the hat surface, or both; wherein at least one of a friction coefficient between the decorative insert and a brake pad is substantially the same as a friction coefficient between the brake pad wear surface and the brake pad, a wear rate of the decorative insert is substantially the same as or greater than a wear rate of the brake pad wear surface, or a wear rate of the decorative insert is substantially the same as or greater than a wear rate of the hat surface; and at least a portion of the decorative insert is visible on the brake pad wear surface, the hat surface, or both.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: August 13, 2019
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Christopher J. Mettrick, Mark T. Riefe, Michael L. Holly, James A. Webster, Michael J. Walker, Anil K. Sachdev
  • Patent number: 10330960
    Abstract: An optical demultiplexer that includes at least one a hybrid phase shifter configured to receive a light signal over a fiber element, the light signal including polarized optical signals. Each phase shifter includes a thermo-optic phase shifter configured to phase shift the light signal, an electro-optic phase shifter configured to phase shift the light signal, and a coupler configured to maintain polarization of the polarized signal components. The optical demultiplexer also includes control circuitry configured to regulate the thermo-optic and electro-optic phase shifters.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: June 25, 2019
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Sean Anderson, Mark Webster, Kalpendu Shastri
  • Patent number: 10320151
    Abstract: The embodiments herein describe a single-frequency laser source (e.g., a distributed feedback (DFB) laser or distributed Bragg reflector (DBR) laser) that includes a feedback grating or mirror that extends along a waveguide. The grating may be disposed over a portion of the waveguide in an optical gain region in the laser source. Instead of the waveguide or cavity being linear, the laser includes a U-turn region so that two ends of the waveguide terminate at the same facet. That facet is coated with an anti-reflective (AR) coating.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: June 11, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Matthew J. Traverso, Dominic F. Siriani, Mark Webster
  • Publication number: 20190073430
    Abstract: C Sharp (C#) system including one or more C Sharp (C#) computing devices for dynamically serializing C Sharp (C#) during runtime is provided. The C# system is configured to receive a serialized JSON class including at least one data object associated with at least one attribute name and deserialize the serialized JSON class. The C# system is also configured to serialize a C# class using the deserialized JSON class, and dynamically identify, from the C# class, the at least one data object during the runtime of the data objects. The C# system is further configured to generate a dynamic C# class, wherein the dynamic C# class includes a target class and a method for returning the at least one data object, and return the at least one data object.
    Type: Application
    Filed: September 7, 2017
    Publication date: March 7, 2019
    Inventor: Mark Webster
  • Patent number: 10175448
    Abstract: An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: January 8, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Mary Nadeau, Vipulkumar Patel, Prakash Gothoskar, John Fangman, John Matthew Fangman, Mark Webster
  • Patent number: 10145758
    Abstract: Embodiments herein describe techniques for testing optical components in a photonic chip using a testing structure disposed in a sacrificial region of a wafer. In one embodiment, the wafer is processed to form multiple photonic chips integrated into the wafer. While forming optical components in the photonic chips (e.g., modulators, detectors, waveguides, etc.), a testing structure can be formed in one or more sacrificial regions in the wafer. In one embodiment, the testing structure is arranged near an edge coupler in the photonic chip such that an optical signal can be transferred between the photonic chip and the testing structure. Moreover, the testing structure has a grating coupler disposed at or near a top surface of the wafer which permits optical signals to be transmitted into, or received from, the grating coupler when an optical probe is arranged above the grating coupler.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: December 4, 2018
    Assignee: Cisco Technology, Inc.
    Inventors: Matthew J. Traverso, Ravi S. Tummidi, Mark A. Webster, Sandeep Razdan
  • Publication number: 20180341064
    Abstract: A SOI device may include a waveguide adapter that couples light between an external light source—e.g., a fiber optic cable or laser—and a silicon waveguide on the silicon surface layer of the SOI device. In one embodiment, the waveguide adapter is embedded into the insulator layer. Doing so may enable the waveguide adapter to be formed before the surface layer components are added onto the SOI device. Accordingly, fabrication techniques that use high-temperatures may be used without harming other components in the SOI device—e.g., the waveguide adapter is formed before heat-sensitive components are added to the silicon surface layer.
    Type: Application
    Filed: August 1, 2018
    Publication date: November 29, 2018
    Inventors: Mark WEBSTER, Ravi Sekhar TUMMIDI
  • Publication number: 20180313718
    Abstract: Embodiments herein describe techniques for testing optical components in a photonic chip using a testing structure disposed in a sacrificial region of a wafer. In one embodiment, the wafer is processed to form multiple photonic chips integrated into the wafer. While forming optical components in the photonic chips (e.g., modulators, detectors, waveguides, etc.), a testing structure can be formed in one or more sacrificial regions in the wafer. In one embodiment, the testing structure is arranged near an edge coupler in the photonic chip such that an optical signal can be transferred between the photonic chip and the testing structure. Moreover, the testing structure has a grating coupler disposed at or near a top surface of the wafer which permits optical signals to be transmitted into, or received from, the grating coupler when an optical probe is arranged above the grating coupler.
    Type: Application
    Filed: April 28, 2017
    Publication date: November 1, 2018
    Applicants: Cisco Technology, Inc., Cisco Technology, Inc.
    Inventors: Matthew J. TRAVERSO, Ravi S. TUMMIDI, Mark A. WEBSTER, Sandeep RAZDAN
  • Patent number: 10103845
    Abstract: Embodiments of dual mode communication systems and methods are disclosed. On system embodiment, among others, comprises logic configured to perform spatial multiplexing and expanded bandwidth signaling to data.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: October 16, 2018
    Assignee: Intellectual Ventures I LLC
    Inventors: Mark A Webster, Michael J Seals
  • Patent number: 10054745
    Abstract: A SOI device may include a waveguide adapter that couples light between an external light source—e.g., a fiber optic cable or laser—and a silicon waveguide on the silicon surface layer of the SOI device. In one embodiment, the waveguide adapter is embedded into the insulator layer. Doing so may enable the waveguide adapter to be formed before the surface layer components are added onto the SOI device. Accordingly, fabrication techniques that use high-temperatures may be used without harming other components in the SOI device—e.g., the waveguide adapter is formed before heat-sensitive components are added to the silicon surface layer.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: August 21, 2018
    Assignee: Cisco Technology, Inc.
    Inventors: Mark Webster, Ravi Sekhar Tummidi
  • Publication number: 20180188450
    Abstract: Embodiments herein describe a photonic chip which includes a coupling interface for evanescently coupling the chip to a waveguide on an external substrate. In one embodiment, the photonic chip includes a tapered waveguide that aligns with a tapered waveguide on the external substrate. The respective tapers of the two waveguides are inverted such that as the width of the waveguide in the photonic chip decreases, the width of the waveguide on the external substrate increases. In one embodiment, these two waveguides form an adiabatic structure where the optical signal transfers between the waveguides with minimal or no coupling of the optical signal to other non-intended modes. Using the two waveguides, optical signals can be transmitted between the photonic chip and the external substrate.
    Type: Application
    Filed: February 19, 2018
    Publication date: July 5, 2018
    Inventors: Vipulkumar PATEL, Mark WEBSTER, Ravi TUMMIDI, Mary NADEAU
  • Patent number: 9933566
    Abstract: Embodiments herein describe a photonic chip which includes a coupling interface for evanescently coupling the chip to a waveguide on an external substrate. In one embodiment, the photonic chip includes a tapered waveguide that aligns with a tapered waveguide on the external substrate. The respective tapers of the two waveguides are inverted such that as the width of the waveguide in the photonic chip decreases, the width of the waveguide on the external substrate increases. In one embodiment, these two waveguides form an adiabatic structure where the optical signal transfers between the waveguides with minimal or no coupling of the optical signal to other non-intended modes. Using the two waveguides, optical signals can be transmitted between the photonic chip and the external substrate.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: April 3, 2018
    Assignee: Cisco Technology, Inc.
    Inventors: Vipulkumar Patel, Mark Webster, Ravi Tummidi, Mary Nadeau
  • Patent number: 9864133
    Abstract: The embodiments herein describe a photonic chip (formed from a SOI structure) which includes an optical interface for coupling the optical components in the photonic chip to an external optical device. In one embodiment, the optical interface is formed on a separate substrate which is later joined to the photonic chip. Through oxide vias (TOVs) and through silicon vias (TSVs) can be used to electrically couple the optical components in the photonic chip to external integrated circuits or amplifiers. In one embodiment, after the separate wafer is bonded to the photonic chip, a TOV is formed in the photonic chip to electrically connect metal routing layers coupled to the optical components in the photonic chip to a TSV in the separate wafer. For example, the TOV may extend across a wafer bonding interface where the two substrates where bonded to form an electrical connection with the TSV.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: January 9, 2018
    Assignee: Cisco Technology, Inc.
    Inventors: Vipulkumar Patel, Mark Webster, Ravi Tummidi, Mary Nadeau
  • Publication number: 20170336656
    Abstract: An optical demultiplexer that includes at least one a hybrid phase shifter configured to receive a light signal over a fiber element, the light signal including polarized optical signals. Each phase shifter includes a thermo-optic phase shifter configured to phase shift the light signal, an electro-optic phase shifter configured to phase shift the light signal, and a coupler configured to maintain polarization of the polarized signal components. The optical demultiplexer also includes control circuitry configured to regulate the thermo-optic and electro-optic phase shifters.
    Type: Application
    Filed: July 28, 2017
    Publication date: November 23, 2017
    Inventors: Sean Anderson, Mark Webster, Kalpendu Shastri
  • Publication number: 20170269393
    Abstract: An optical modulator may include a lower waveguide, an upper waveguide, and a dielectric layer disposed therebetween. When a voltage potential is created between the lower and upper waveguides, these layers form a silicon-insulator-silicon capacitor (also referred to as SISCAP) guide that provides efficient, high-speed optical modulation of an optical signal passing through the modulator. In one embodiment, at least one of the waveguides includes a respective ridge portion aligned at a charge modulation region which may aid in confining the optical mode laterally (e.g., in the width direction) in the optical modulator. In another embodiment, ridge portions may be formed on both the lower and the upper waveguides. These ridge portions may be aligned in a vertical direction (e.g., a thickness direction) so that ridges overlap which may further improve optical efficiency by centering an optical mode in the charge modulation region.
    Type: Application
    Filed: June 6, 2017
    Publication date: September 21, 2017
    Inventors: Donald ADAMS, Prakash B. GOTHOSKAR, Vipulkumar PATEL, Mark WEBSTER
  • Patent number: 9766484
    Abstract: An optical modulator may include a lower waveguide, an upper waveguide, and a dielectric layer disposed therebetween. When a voltage potential is created between the lower and upper waveguides, these layers form a silicon-insulator-silicon capacitor (also referred to as SISCAP) guide that provides efficient, high-speed optical modulation of an optical signal passing through the modulator. In one embodiment, at least one of the waveguides includes a respective ridge portion aligned at a charge modulation region which may aid in confining the optical mode laterally (e.g., in the width direction) in the optical modulator. In another embodiment, ridge portions may be formed on both the lower and the upper waveguides. These ridge portions may be aligned in a vertical direction (e.g., a thickness direction) so that ridges overlap which may further improve optical efficiency by centering an optical mode in the charge modulation region.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: September 19, 2017
    Assignee: Cisco Technology, Inc.
    Inventors: Donald Adams, Prakash Gothoskar, Vipulkumar Patel, Mark Webster
  • Patent number: 9746700
    Abstract: An optical demultiplexer that includes at least one a hybrid phase shifter configured to receive a light signal over a fiber element, the light signal including polarized optical signals. Each phase shifter includes a thermo-optic phase shifter configured to phase shift the light signal, an electro-optic phase shifter configured to phase shift the light signal, and a coupler configured to maintain polarization of the polarized signal components. The optical demultiplexer also includes control circuitry configured to regulate the thermo-optic and electro-optic phase shifters.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: August 29, 2017
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Sean Anderson, Mark Webster, Kalpendu Shastri
  • Publication number: 20170192174
    Abstract: A SOI device may include a waveguide adapter that couples light between an external light source—e.g., a fiber optic cable or laser—and a silicon waveguide on the silicon surface layer of the SOI device. In one embodiment, the waveguide adapter is embedded into the insulator layer. Doing so may enable the waveguide adapter to be formed before the surface layer components are added onto the SOI device. Accordingly, fabrication techniques that use high-temperatures may be used without harming other components in the SOI device—e.g., the waveguide adapter is formed before heat-sensitive components are added to the silicon surface layer.
    Type: Application
    Filed: March 17, 2017
    Publication date: July 6, 2017
    Inventors: Mark WEBSTER, Ravi Sekhar TUMMIDI
  • Publication number: 20170139132
    Abstract: The embodiments herein describe a photonic chip (formed from a SOI structure) which includes an optical interface for coupling the optical components in the photonic chip to an external optical device. In one embodiment, the optical interface is formed on a separate substrate which is later joined to the photonic chip. Through oxide vias (TOVs) and through silicon vias (TSVs) can be used to electrically couple the optical components in the photonic chip to external integrated circuits or amplifiers. In one embodiment, after the separate wafer is bonded to the photonic chip, a TOV is formed in the photonic chip to electrically connect metal routing layers coupled to the optical components in the photonic chip to a TSV in the separate wafer. For example, the TOV may extend across a wafer bonding interface where the two substrates where bonded to form an electrical connection with the TSV.
    Type: Application
    Filed: July 13, 2016
    Publication date: May 18, 2017
    Inventors: Vipulkumar PATEL, Mark WEBSTER, Ravi TUMMIDI, Mary NADEAU
  • Publication number: 20170139142
    Abstract: Embodiments herein describe a photonic chip which includes a coupling interface for evanescently coupling the chip to a waveguide on an external substrate. In one embodiment, the photonic chip includes a tapered waveguide that aligns with a tapered waveguide on the external substrate. The respective tapers of the two waveguides are inverted such that as the width of the waveguide in the photonic chip decreases, the width of the waveguide on the external substrate increases. In one embodiment, these two waveguides form an adiabatic structure where the optical signal transfers between the waveguides with minimal or no coupling of the optical signal to other non-intended modes. Using the two waveguides, optical signals can be transmitted between the photonic chip and the external substrate.
    Type: Application
    Filed: May 2, 2016
    Publication date: May 18, 2017
    Inventors: Vipulkumar PATEL, Mark WEBSTER, Ravi TUMMIDI, Mary NADEAU