ORTHOGONAL MULTI-PHASE SCHEDULING CIRCUITRY
An integrated circuit may include orthogonal multi-phase scheduling circuitry. The scheduling circuitry may include a number of orthogonal scheduling circuits each of which is configured to receive different command types and to output a single winning command. The scheduling circuitry may further include a phase assignment circuit for receiving the winning commands from the orthogonal scheduling circuits and for assigning the received winning commands to different corresponding phase groups. Each orthogonal scheduling circuit may include command buffers, command arbiters, a global arbiter, and associated safe checking circuits.
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Integrated circuits are often provided with memory controllers for communicating with off-chip memory devices. Memory controllers typically include command schedulers that run at some fractional rate (i.e., half rate or quarter rate) of the actual interface speed. For example, consider a scenario in which the interface between an integrated circuit and an associated memory device runs at a higher clock rate of 1200 MHz (sometimes referred to as the interface clock speed). Each period of the interface clock is sometimes referred to as an interface clock cycle. In this example, the command scheduler within the integrated circuit may only run at 300 MHz (sometimes referred to as the command scheduler clock rate or internal clock rate).
In such scenarios, the command scheduler should be configured to send multiple commands to the interface during each internal clock cycle to take full advantage of the available interface bandwidth. Issuing multiple commands per internal clock cycle, however, substantially increases the complexity of the command scheduler such that it is very difficult, if not impossible, to satisfy timing constraints at the desired operating speed, while also dramatically increasing the area and power consumption of the scheduler.
In order to meet the targeted speed and area/power budgets, conventional command schedulers only send one command per internal clock cycle. Sending only one command during each internal clock cycle in this way will suffer substantial performance penalties in terms of both bandwidth and latency. Moreover, only very simple scheduling algorithms with reduced scheduling features can be supported in such arrangements. It is within this context that the embodiments described herein arise.
The present embodiments relate to methods and apparatus for implementing and partitioning a complex command scheduler that is capable of scheduling n winning commands from m input commands at each interface clock cycle into n individual orthogonal scheduling circuits. Each of the n orthogonal scheduling circuits will only schedule one winning command per interface clock cycle. Configured and operated in this way, the latency of the communications interface supported by the command scheduler may be substantially reduced by increasing the command bus bandwidth by n times while improving timing margins and reducing power consumption.
It will be recognized by one skilled in the art, that the present exemplary embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order not to unnecessarily obscure the present embodiments.
Device 102 may include transceivers and/or other input-output (I/O) components for interfacing with external devices. For example, device 102 may include physical-layer (“PHY”) interface circuitry such as PHY circuits 106 configured to communicate with the auxiliary memory device 104 via interface 108. In one suitable arrangement, devices 102 and 104 may be mounted as separate discrete components on a circuit board, may be formed as part of a single package (e.g., a multichip package where auxiliary device 104 is mounted laterally with respect to main device 102 or where auxiliary device 104 is stacked vertically with respect to main device 102, etc.), may be formed as parts of different systems, etc.
PHY circuits 106 may serve as a physical-layer bridging interface between an associated memory controller on main device 102 and one or more high-bandwidth channels coupled to memory device 104 (e.g., PHY circuits 106 may be used to physically drive signals off of device 102 to memory device 104 and to receive signals from memory device 104). In general, PHY circuits 106 may be configured to support serial or parallel input-output channel interfaces running at single data rate (SDR), dual data rate (DDR), or quad data rate (QDR) communications schemes.
Memory device 104 may be a memory chip (e.g., one or more memory devices stacked on top of one another) that is implemented using random-access memory such as static random-access memory (SRAM), dynamic random-access memory (DRAM), low latency DRAM (LLDRAM), reduced latency DRAM (RLDRAM), or other types of volatile memory. If desired, memory device 104 may also be implemented using nonvolatile memory (e.g., fuse-based memory, antifuse-based memory, electrically-programmable read-only memory, etc.). In some embodiments, memory device 104 may be an off-chip memory device sometimes referred to as a single in-line memory module (SIMM) or a dual in-line memory module (DIMM). If desired, device 10 may be configured to communicate with at least two memory modules, at least four memory modules, etc.
To initiate a memory operation, processing circuitry 200 may output one or more corresponding commands along with the associated clock, address, and/or other control signals to memory controller 202. Memory controller 202 may include command scheduling circuitry 210 for selecting which commands are being sent to the PHY interface at any given point in time. Still referring to
In order to reduce the complexity of the memory controller, conventional command scheduling circuitry only sends out one command at each internal clock cycle. Other traditional schedulers are capable of outputting multiple commands during each internal clock cycle, but the interface clock rate will be severely limited while such schedulers have complex implementations that require elimination of features such as the elimination of Quality-of-Service (QoS) feature to help keep the overall complexity at a manageable level. Either of these approaches suffers from substantial performance penalties in terms of bandwidth and latency. Moreover, the elimination of features such as QoS may be undesirable for many applications, whereas large complex implementations will have a difficult time meeting area and power consumption budgets.
In accordance with an embodiment,
In this example, scheduling circuitry 210 may receive up to m_total commands of m_total different types of commands per internal clock cycle, where m_total is equal to (m0+m1+m2+m3). The first scheduling circuit 300-0 may receive up to m0 commands of m0 different types of commands and may output a single winning command cmd_won0. The second scheduling circuit 300-1 may receive up to m1 commands of m1 different types of commands and may output a single winning command cmd_won1. The third scheduling circuit 300-2 may receive up to m2 commands of m2 different types of commands and may output a single winning command cmd_won2. The fourth scheduling circuit 300-3 may receive up to m3 commands of m3 different types of commands and may output a single winning command cmd_won3. In other words, each of the four orthogonal scheduling circuits is configured to output a single winning command at any given point in time during normal operation. The cmd_woni can be null when there is no qualified input command for the scheduler i, for i=0, 1, 2, 3.
Scheduling circuitry 210 may further include a phase assignment circuit such as phase assignment circuit 302 configured to allocate the various winning commands to different phases of the internal clock signal. Assuming circuitry 210 has four scheduling circuits 300,
In this example, the maximum possible number of phases “p” in each internal clock cycle is p=4, where p is defined as being equal to L/K. As described above in connection with
In the example of
Configured in this way, scheduling circuitry 210 is able to schedule n commands from m_total input commands of m_total different types of commands received at every internal clock cycle, where the m_total input commands are sorted into p orthogonal phase groups. The n scheduling circuits 300, each of which is associated with a different phase group, may operate in parallel to output the n winning commands. The n winning commands are then scheduled at different phases using the phase assignment circuit 302, which optionally interleave in one or more NOPs whenever n is less than p. The number of interleaved NOPs may be equal to (p−n). By partitioning a m_total:n scheduling circuitry 210 into n smaller scheduling circuits 300, the complexity of the overall scheduling circuitry is dramatically reduced from O(m_total*n) to O(m_total/n) on average, which substantially reduces circuit area, cost, and power consumption.
As described above, the p phase groups are orthogonal to each other. The term “orthogonal” means that one particular type of command can only occur in a particular phase. Referring back to the example of
Generally, the orthogonal multi-phase scheduling circuitry 210 may be characterized by the following conditions: (1) a multiple phase condition; and (2) an orthogonal phase condition. The first multi-phase condition requires more than one command to be issued in L consecutive interface clock cycles. In other words, L consecutive interface clock cycles may correspond to p orthogonal phase groups during which different types of commands can occur. The second orthogonal phase condition requires that the number of interface clock cycles between any pair of the same command type be a multiple of L. Thus, in an example where p=L=4, a write command should only occur in a selected phase, and consecutive write commands should be separated by 4 interface clock cycles, 8 interface clock cycles, 12 interface clock cycles, or other multiples of four. In other words, each command type should only occur in a respective fixed phase group (i.e., a write command occurring in the phase0 group should not later on occur in another phase group). Moreover, any two commands in different phase groups should also be orthogonal.
Exemplary device configurations where orthogonal multi-phase scheduling circuitry 210 includes n=4 orthogonal scheduling circuits (each of which receives four different command types) feeding n winning commands into p=4 orthogonal phase groups is merely illustrative and is not intended to limit the scope of the present embodiments. In general, circuitry 210 may be configured to receive any number of inputs (e.g., m_total may be any integer greater than two, greater than eight, greater than 16, greater than 32, etc.) and may include any number of orthogonal scheduling circuits 300 (e.g., n may be any integer greater than one and less than or equal to the maximum possible number of phase groups p). If desired, each scheduling circuit 300 may receive the same number of commands (e.g., m0=m1=m2=m3) or may receive a different number of commands (e.g., m≠m1).
The first command buffer 502-1 may be configured to receive and queue commands of a first type; the second command buffer 502-2 may receive and queue commands of a second type; . . . ; and the mth command buffer 502-m may receive and queue commands of an mth type. Each command buffer may feed a respective command arbiter (e.g., command buffer 502-1 may feed command arbiter 504-1; command buffer 502-2 may feed command arbiter 504-2; . . ; and command buffer 502-m may feed command arbiter 504-m). Configured in this way, each command arbiter 504 may select one winning command from the corresponding queue of commands in the preceding buffer. Each command arbiter 504 may optionally qualify the commands based on safe flags generated from the corresponding safe checker circuits 508 and arbitrating between the qualified commands using a round robin scheme, a first-come first-out scheme, or other priority schemes.
Global arbiter circuit 506 may receive m commands from the m command arbiters 504 and may select one winning command cmd_won for output by scheduling circuit 300. The command safe checking circuits 508 may monitor the output command cmd_won. Safe checker 508 may check if a particular output command can be scheduled safely based on a minimum command phase interval between all previous commands and the particular output command and/or credit. One command safe checker is required for each command (e.g., safe checker 508-1 is used for checking the commands from arbiter 504-1; safe checker 508-2 is used for checking the commands from arbiter 504-2; . . . ; and safe checker 508-m is used for checking the commands from arbiter 504-m). For example, if the minimum interval from cmd0 to cmd1 is equal to 5, the safe checker for cmd1 may deassert the safe flag to zero to block cmd1 in the next four phases (i.e., 5-1) whenever cmd0 is sent. In this case, the safe checker for cmd1 will need to monitor cmd0 all the time.
Given a set of possible commands, there may be minimum command interval requirements between each pair of command types (e.g., minimum command phase interval requires set by the communications protocol of interest). For example, consider a scenario with a given set of different types of command (e.g., cmd0, cmd1, cmd2, cmd3, and cmd4).
Once the minimum command intervals are known, the commands may be grouped into the p possible phases in various ways to achieve different goals and tradeoffs. Consider a scenario where p=4. The five command types may assigned as follows:
-
- Phase0 command group: assigned with cmd0
- Phase1 command group: assigned with cmd2 and cmd4
- Phase2 command group: assigned with cmd3
- Phase3 command group: assigned with cmd1
Given the above command-phase grouping, it is possible to verify that each and every adjacent command pair (i.e., cmdi to the 1st next cmdj) will be equal to or larger than the corresponding minimum required command interface as listed in table 700. For example, if cmd0 is in phase0 and cmd4 is in phase1, then the phase interval between the two will be equal to one, which is at least equal to the corresponding value in table 700 (see arrow 610 in
Because any given command type can only occur in its assigned phase, the actual implemented minimum command interval from cmdi to cmdj can be larger than the theoretical required minimum interval from cmdi to cmdj. For example, the listed minimum required interval from cmd4 to cmd1 is 1 (see table entry 705), but the actual minimum command interval from cmd4 to cmd1 in the implemented circuit might be equal to 2. As another example, the listed minimum required interval from cmd2 to cmd2 is 6 (see table entry 706), but the actual minimum command interval from cmd2 to cmd2 in the implemented circuit might be equal to 8. Such possibility should be taken into consideration when design the multi-phase scheduling circuitry and when assigning commands to the different available phase groups.
Consider another example still with five different types of command (e.g., cmd0, cmd1, cmd2, cmd3, and cmd4). The minimum command interval requirements are the same as those in
-
- Phase0 command group: assigned with cmd0
- Phase1 command group: assigned with cmd2 and cmd4
- Phase2 command group: assigned with cmd3
- Phase3 Command Group: Assigned with cmd1
Given the above command-phase grouping (which is the same group as the previous example), the actual phase intervals for at least some command pairs will violate the corresponding minimum required command interface as listed in
In such scenario where at least some of the minimum command interval requirements are violated, safe checking is required from cmd4 to cmd0, from cmd4 to cmd1, from cmd4 to cmd2, and from cmd4 to cmd3 (which are all in different command groups), and also from cmd4 to cmd4 (which are in the same command group). In this example, the four command phase groups and the four individual scheduling circuits 300 (see
Because any given command type can only occur in its assigned phase, the actual implemented minimum command interval from cmdi to cmdj might be larger than the theoretical required minimum interval from cmdi to cmdj. For example, the listed minimum required interval from cmd4 to cmd0 is 6 (see table entry 707), but the actual minimum command interval from cmd4 to cmd0 in the implemented circuit might be equal to 7. Because cmd4 is assigned to phase1 while cmd0 is in phase0, the phase interval from phase1 to phase0 must be 3, 7, 11, 15, and so on. Thus, in order to meet the implemented minimum phase interval requirement, only 7, 11, 15, or higher intervals are viable assignments.
At step 802, the possible input commands may be distributed or assigned to p orthogonal phase groups with n non-empty phase groups. For example, the commands may be allocated to corresponding phases based on the minimum time interval requirements obtained from step 800, the number of commands in each command phase group, a Quality of Service (QoS) metric, the maximum operating frequency Fmax, the target throughput, the target latency, etc. In general, it may be desirable to distribute the m_total commands over the multiple orthogonal phase groups to maximize n (such that n is as close to p as possible) while balancing the number of command types received at the various schedulers (e.g., to minimize the largest of all mi for i=1, 2, . . . , p. In other words, the number of command types received at each individual scheduling circuit 300 may be equal or may be slightly different.
If desired, the command types may be grouped to minimize the difference of the actual minimal command interval and the required command interval. If desired, the command types may be grouped such that the p phase groups should be independent so that there is no safe concern among any two commands from any two phase groups (i.e., any command in phase group i to any command in phase group j has a phase/time interval between phase i and phase j larger than the minimum required command interval between the two commands). Some of the phase groups may be empty. If the number of non-empty phase groups is n, where n is less than p, then there will be (p−n) empty phase groups.
At step 804, the n individual scheduling circuits may be configured to receive a different group of command types and may each output one winning command. Because the n non-empty phase groups are orthogonal to one another, the n scheduling circuits are designed independently except for some safe checkers across the schedulers in some cases and only one winning command has to be scheduled from each, which dramatically reduces the complexity of the overall scheduling circuitry.
At step 806, the phase assignment circuit may be configured to arrange the n winning commands output in parallel from the n orthogonal scheduling circuits. If n<p, then (p−n) no-operations may be sent during the empty phases over the interface.
Although the methods of operations are described in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or described operations may be distributed in a system which allows occurrence of the processing operations at various intervals associated with the processing, as long as the processing of the overlay operations are performed in a desired way.
The embodiments described above that involve use of n orthogonal scheduling circuits are merely illustrative and are not intended to limit the scope of the present embodiments. If desired, orthogonal multi-phase scheduling circuitry may be implemented as a single scheduling circuit that satisfies the multiple phase condition (e.g., multiple commands are issued during different phases of the internal clock signal) and the orthogonal phase condition (e.g., particular command types will only occur in assigned orthogonal phase groups). An exemplary implementation of such single-scheduler orthogonal multi-phase scheduling circuitry 210′ is shown in
The first command buffer 902-1 may be configured to receive and queue commands of a first type; the second command buffer 902-2 may receive and queue commands of a second type; . . . ; and the 16th command buffer 902-16 may receive and queue commands of a 16th type. Each command queue 902 may feed a respective command arbiter (e.g., command buffer 902-1 may feed command arbiter 904-1; command buffer 902-2 may feed command arbiter 904-2; . . . ; and command buffer 902-16 may feed command arbiter 904-16). Configured in this way, each command arbiter 904 may select one winning command from the corresponding queue of commands in the preceding buffer. Each command arbiter 904 may optionally qualify the commands based on safe flags generated from the corresponding safe checker circuits 908 and arbitrating between the qualified commands using a round robin scheme, a first-come first-out scheme, or other priority schemes.
Global arbiter circuit 906 may receive the 16 commands from the 16 command arbiters 904 and may select a group of four orthogonal winning commands (e.g., cmd_wonA, cmd_wonB, cmd_wonC, cmd_wonD) for output. The command safe checking circuits 908 may monitor the four output winning commands. Safe checker 908 may check if a particular output command can be scheduled safely based on a minimum command phase interval between all previous commands and the particular output command and/or credit. One command safe checker is required for each command type (e.g., safe checker 908-1 is used for checking the commands from arbiter 904-1; safe checker 908-2 is used for checking the commands from arbiter 904-2; . . . ; and safe checker 908-16 is used for checking the commands from arbiter 904-16).
Phase assignment circuit 912 may be configured to allocate the four winning commands to the different phases of the internal clock signal. Assuming p=4, phase assignment circuit 912 will assign the four winning commands to the four available phase groups according to the command types of winning commands or the phase schedulers of the winning commands. In the example of
The example of
The following examples pertain to further embodiments.
Example 1 is an integrated circuit, comprising: an interface circuit configured to communicate with an external device; and multi-phase scheduling circuitry controlled by an internal clock signal, wherein the multi-phase scheduling circuitry is configured to output a first command during a first phase of the internal clock signal and to output a second command during a second phase of the internal clock signal that is different than the first phase.
Example 2 is the integrated circuit of example 1, wherein the multi-phase scheduling circuitry is optionally further configured to receive commands of a first type and to output the commands of the first type only during the first phase of the internal clock signal.
Example 3 is the integrated circuit of example 2, wherein the multi-phase scheduling circuitry is optionally further configured to receive commands of a second type and to output the commands of the second type only during the second phase of the internal clock signal.
Example 4 is the integrated circuit of any one of examples 1-3, wherein the multi-phase scheduling circuitry optionally comprises a plurality of orthogonal scheduling circuits.
Example 5 is the integrated circuit of any one of examples 1-3, wherein the multi-phase scheduling circuitry optionally comprises a plurality of scheduling circuits.
Example 6 is the integrated circuit of example 5, wherein each scheduling circuit in the plurality of scheduling circuits is optionally configured to receive commands of different types.
Example 7 is the integrated circuit of any one of examples 5-6, wherein each scheduling circuit in the plurality of scheduling circuits is optionally configured to output a single winning command at any given point in time.
Example 8 is the integrated circuit of any one of examples 5-7, wherein the multi-phase scheduling circuitry optionally further comprises: a phase assignment circuit configured to assign the first command to the first phase of the internal clock signal and to assign the second command to the second phase of the internal clock signal.
Example 9 is the integrated circuit of example 8, wherein the phase assignment circuit is optionally further configured to assign at least one no-operation (NOP) to at least one empty phase of the internal clock signal.
Example 10 is the integrated circuit of any one of examples 5-9, wherein at least one scheduling circuit in the plurality of scheduling circuits optionally comprises: a plurality of command queues configured to receive and buffer input commands of different types.
Example 11 is the integrated circuit of example 10, wherein the at least one scheduling circuit in the plurality of scheduling circuits optionally further comprises: a plurality of command arbiters configured to receive commands from the plurality of command queues.
Example 12 is the integrated circuit of example 11, wherein the at least one scheduling circuit in the plurality of scheduling circuits optionally further comprises: a global arbiter configured to receive commands from the plurality of command arbiters and to output a single winning command from among the commands received from the plurality of command arbiters.
Example 13 is the integrated circuit of example 12, wherein the at least one scheduling circuit in the plurality of scheduling circuits optionally further comprises: a plurality of safe checking circuits configured to monitor the single winning command output from the global arbiter and to check whether the single winning command can be safely scheduled based on minimum command interval requirements between previous commands and the single winning command.
Example 14 is an integrated circuit, comprising: an interface circuit operable to communicate with an off-chip device; and command scheduling circuitry controlled by an internal clock signal, wherein the command scheduling circuitry is configured to output at least a first type of command and a second type of command, and wherein the command scheduling circuitry is further configured to output the first type of command only during a first phase of the internal clock signal and to output the second type of command only during a second phase of the internal clock signal that is different than the first phase.
Example 15 is the integrated circuit of example 14, wherein the command scheduling circuitry is optionally further configured to output at least four different types of commands during at least four different phases of the internal clock signal.
Example 16 is the integrated circuit of any one of examples 14-15, wherein the command scheduling circuitry optionally comprises a plurality of scheduling circuits each of which is configured to receive commands of different types and to output a single winning command.
Example 17 is the integrated circuit of example 16, wherein the plurality of scheduling circuits optionally comprises a plurality of independent scheduling circuits such that no safe checking is required between commands in different phases of the internal clock signal.
Example 18 is the integrated circuit of example 16, wherein the plurality of scheduling circuits optionally comprises a plurality of dependent scheduling circuits such that safe checking is required between commands in different phases of the internal clock signal.
Example 19 is command scheduling circuitry, comprising: a plurality of command queues configured to receive different types of commands; a plurality of command arbiters configured to receive commands from the plurality of command queues; a global arbiter configured to receive commands from the plurality of command arbiters and to output orthogonal commands; and a phase assignment circuit configured to receive the orthogonal commands from the global arbiter and to assign the orthogonal commands to respective phase groups of a clock signal.
Example 20 is the command scheduling circuitry of example 19, optionally further comprising: a plurality of safe checking circuits interposed in feedback paths coupled between the global arbiter and the plurality of command arbiters.
For instance, all optional features of the apparatus described above may also be implemented with respect to the method or process described herein. The foregoing is merely illustrative of the principles of this disclosure and various modifications can be made by those skilled in the art. The foregoing embodiments may be implemented individually or in any combination.
Claims
1. An integrated circuit, comprising:
- an interface circuit configured to communicate with an external device; and
- multi-phase scheduling circuitry controlled by an internal clock signal, wherein the multi-phase scheduling circuitry is configured to output a first command during a first phase of the internal clock signal and to output a second command during a second phase of the internal clock signal that is different than the first phase.
2. The integrated circuit of claim 1, wherein the multi-phase scheduling circuitry is further configured to receive commands of a first type and to output the commands of the first type only during the first phase of the internal clock signal.
3. The integrated circuit of claim 2, wherein the multi-phase scheduling circuitry is further configured to receive commands of a second type and to output the commands of the second type only during the second phase of the internal clock signal.
4. The integrated circuit of claim 1, wherein the multi-phase scheduling circuitry comprises a plurality of orthogonal scheduling circuits.
5. The integrated circuit of claim 1, wherein the multi-phase scheduling circuitry comprises a plurality of scheduling circuits.
6. The integrated circuit of claim 5, wherein each scheduling circuit in the plurality of scheduling circuits is configured to receive commands of different types.
7. The integrated circuit of claim 5, wherein each scheduling circuit in the plurality of scheduling circuits is configured to output a single winning command at any given point in time.
8. The integrated circuit of claim 5, wherein the multi-phase scheduling circuitry further comprises:
- a phase assignment circuit configured to assign the first command to the first phase of the internal clock signal and to assign the second command to the second phase of the internal clock signal.
9. The integrated circuit of claim 8, wherein the phase assignment circuit is further configured to assign at least one no-operation (NOP) to at least one empty phase of the internal clock signal.
10. The integrated circuit of claim 5, wherein at least one scheduling circuit in the plurality of scheduling circuits comprises:
- a plurality of command queues configured to receive and buffer input commands of different types.
11. The integrated circuit of claim 10, wherein the at least one scheduling circuit in the plurality of scheduling circuits further comprises:
- a plurality of command arbiters configured to receive commands from the plurality of command queues.
12. The integrated circuit of claim 11, wherein the at least one scheduling circuit in the plurality of scheduling circuits further comprises:
- a global arbiter configured to receive commands from the plurality of command arbiters and to output a single winning command from among the commands received from the plurality of command arbiters.
13. The integrated circuit of claim 12, wherein the at least one scheduling circuit in the plurality of scheduling circuits further comprises:
- a plurality of safe checking circuits configured to monitor the single winning command output from the global arbiter and to check whether the single winning command can be safely scheduled based on minimum command interval requirements between previous commands and the single winning command.
14. An integrated circuit, comprising:
- an interface circuit operable to communicate with an off-chip device; and
- command scheduling circuitry controlled by an internal clock signal, wherein the command scheduling circuitry is configured to output at least a first type of command and a second type of command, and wherein the command scheduling circuitry is further configured to output the first type of command only during a first phase of the internal clock signal and to output the second type of command only during a second phase of the internal clock signal that is different than the first phase.
15. The integrated circuit of claim 14, wherein the command scheduling circuitry is further configured to output at least four different types of commands during at least four different phases of the internal clock signal.
16. The integrated circuit of claim 14, wherein the command scheduling circuitry comprises a plurality of scheduling circuits each of which is configured to receive commands of different types and to output a single winning command.
17. The integrated circuit of claim 16, wherein the plurality of scheduling circuits comprises a plurality of independent scheduling circuits such that no safe checking is required between commands in different phases of the internal clock signal.
18. The integrated circuit of claim 16, wherein the plurality of scheduling circuits comprises a plurality of dependent scheduling circuits such that safe checking is required between commands in different phases of the internal clock signal.
19. Command scheduling circuitry, comprising:
- a plurality of command queues configured to receive different types of commands;
- a plurality of command arbiters configured to receive commands from the plurality of command queues;
- a global arbiter configured to receive commands from the plurality of command arbiters and to output orthogonal commands; and
- a phase assignment circuit configured to receive the orthogonal commands from the global arbiter and to assign the orthogonal commands to respective phase groups of a clock signal.
20. The command scheduling circuitry of claim 19, further comprising:
- a plurality of safe checking circuits interposed in feedback paths coupled between the global arbiter and the plurality of command arbiters.
Type: Application
Filed: Mar 13, 2020
Publication Date: Jul 2, 2020
Patent Grant number: 12056065
Applicant: Intel Corporation (Santa Clara, CA)
Inventor: Qiang Wang (Palo Alto, CA)
Application Number: 16/818,163