Optical Transceiver and Manufacturing Method Thereof
A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.
This application is a continuation of U.S. patent application Ser. No. 17/952,681 filed on Sep. 26, 2022, entitled “Optical Transceiver and Manufacturing Method Thereof,” which is a continuation of U.S. patent application Ser. No. 17/121,060 filed on Dec. 14, 2020, entitled “Optical Transceiver and Manufacturing Method Thereof,” now U.S. Pat. No. 11,454,773, issued on Sep. 27, 2022, which is a continuation of U.S. patent application Ser. No. 16/451,472 filed on Jun. 25, 2019, entitled “Optical Transceiver and Manufacturing Method Thereof,” now U.S. Pat. No. 10,866,373 issued on Dec. 15, 2020, which claims the benefit of and priority to U.S. Provisional Patent Application No. 62/690,658, filed on Jun. 27, 2018, entitled “Optical Fibers Attached to Interposers,” and U.S. Provisional Patent Application No. 62/864,608, filed on Jun. 21, 2019, entitled “Optical Transceiver and Manufacturing Method Thereof,” which applications are incorporated herein by reference in their entirety.
BACKGROUNDOptical transceiver modules are used in high-speed optical communication systems that require high performance, compact package, and low power consumption. Optical transmission/reception functions are implemented in pluggable optical transceiver modules. The optical transceiver modules comply with various international standard specifications at communication speeds ranging up to more than 100 Gbps. Currently, fabrication processes of the compact optical transceiver modules are quite complex and increase of the yield rate thereof is needed.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
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The cross-sectional view of the singulated dummy die 100a illustrated in
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After attaching the singulated dummy dies 100a onto the interposer wafer INT, the periphery regions of the singulated dummy dies 100a adhere with the interposer wafer INT through the glue layers G, and the central region of the singulated dummy dies 100a cover the grooves 200c. The protrusions P may extend toward the wall structures WS and protrude into the trenches TR of the singulated dummy dies 100a. In some embodiments, the protrusions P are directly in contact with the wall structures WS of the singulated dummy dies 100a, and the trenches TR of the singulated dummy dies 100a are fully or partially filled by the protrusions P and the wall structures WS. In some alternative embodiments, the protrusions P are not in contact with the wall structures WS of the singulated dummy dies 100a. The protrusions P and the trenches TR may facilitate the alignment of the singulated dummy dies 100a and the interposer wafer INT.
After attaching the singulated dummy dies 100a onto the interposer wafer INT, the protection coatings PC of the singulated dummy dies 100a may cover and protect the grooves 200c of the interposer wafer INT from being damaged. As illustrated in
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In some embodiments, the attachment of the singulated dummy dies 100a is performed prior to the bonding of the electric integrated circuit dies 300. In some alternative embodiments, the bonding of the electric integrated circuit dies 300 is performed prior to the attachment of the singulated dummy dies 100a.
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In some other embodiments, the formation of the underfill UF1 may be omitted.
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After performing the thinning process of the interposer wafer INT, redistribution wirings RDL and conductive bumps B3 may be formed on the first rear surface RS1 of the interposer wafer INT. In some embodiments, the conductive bumps B3 formed on the first rear surface RS1 of the interposer wafer INT may be controlled collapse chip connection bumps (C4 bumps). For example, a plurality of groups of conductive bumps B3 may be formed on the first rear surface RS1 of the interposer wafer INT, and each group of conductive bumps B3 may be formed on one of the photonic integrated circuit dies 200 respectively.
After performing the thinning process of the interposer wafer INT, the insulating molding material is further ground or polished by a second grinding process. During the second grinding process of the insulating encapsulant 400a, not only the insulating molding material is partially removed but also portions of the electric integrated circuit dies 300 and the singulated dummy dies 100a are removed. After performing the second grinding process, dummy dies 100b with reduced thickness, electric integrated circuit dies 300a with reduced thickness, and a polished insulating encapsulant 400b are formed over the interposer wafer INT. As shown in
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Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3D-IC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3D-IC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.
In some embodiments, an underfill UF2 may be formed between the singulated optical transceiver OTC and the circuit substrate SUB to laterally encapsulate the photonic integrated circuit dies 200 and the conductive bumps B3. In some alternative embodiments, the formation of the underfill UF2 may be omitted.
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By utilizing the embodiments described herein, photonic fibers can be integrated within an interposer such as a silicon interposer. Further, by implementing the embodiments in a system on integrated chip (SOIC), the electrical losses can be minimized, leading to a more efficient final device.
In accordance with some embodiments of the present invention, a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.
In accordance with some other embodiments of the present invention, a structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and an optical fiber insertion groove located in proximity of the optical input/output portion. The electric integrated circuit die and a semiconductor dam are disposed over the photonic integrated circuit die in a side-by-side manner, wherein the electric integrated circuit die is electrically connected to the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam, wherein a side surface of the semiconductor dam is accessibly exposed from the insulating encapsulation, and the semiconductor dam separates the optical fiber insertion groove from the insulating encapsulant.
In accordance with some alternative embodiments of the present invention, a method including the following steps is provided. a photonic integrated circuit die including at least one optical input/output portion and at least one groove located in proximity of the optical input/output portion is provided. An electric integrated circuit die and a dummy die are bonded onto the photonic integrated circuit die. A portion of the dummy die is removed to form a semiconductor dam having a notch such that the at least one groove is exposed by the notch of the semiconductor dam.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A three-dimensional packaging method of a photonic-electronic chip, comprising:
- providing a photonic chip with a first surface and a second surface which are opposite to each other;
- fixing a dummy chip on a second area of the first surface of the photonic chip, wherein the photonic chip is provided with an optical coupling interface at the second area, and the dummy chip has a cavity with a single-sided opening, and the opening of the cavity faces and covers the optical coupling interface;
- forming an injection molding material layer on the photonic chip on which the dummy chip 100a is fixed, so that the injection molding material layer covers the dummy chip and the exposed areas of the first surface of the photonic chip; and
- thinning the injection molding material layer and the dummy chip so that the cavity of the dummy chip is connected up and down.
2. The three-dimensional packaging method of claim 1, wherein
- before the step of forming the injection molding material layer, the method further comprising a step of fixing an electronic chip on a first area of the first surface of the photonic chip; and
- the step of thinning the injection molding material layer and the dummy chip comprising thinning the injection molding material layer, the electronic chip and the dummy chip.
3. The three-dimensional packaging method of claim 2, wherein
- fixing the second surface of the photonic chip on a package substrate after the step of thinning the injection molding material layer and the dummy chip so that the cavity of the dummy chip is connected up and down.
4. The three-dimensional packaging method of claim 3, wherein
- the photonic chip has an electric channel for electrically connecting the electronic chip to the package substrate, and the electric channel is connected to a first metal bump provided on the first surface of the photonic chip;
- the fixing an electronic chip on a first area of the first surface of the photonic chip comprises: flip-chipping the electronic chip to the first area of the first surface of the photonic chip, and bonding a pin of the electronic chip with the first metal bump;
- the dummy chip has a dummy chip metal bump on a side with the opening; and
- the fixing of the dummy chip on the second area of the first surface of the photonic chip comprises: bonding the dummy chip metal bump with a second metal bump on the photonic chip.
5. The three-dimensional packaging method of claim 4, wherein
- the electric channel in the photonic chip is a conductive via, and the conductive via is connected to an electric connection point on the package substrate by a third metal bump on the second surface of the photonic chip after the second surface of the photonic chip is fixed on the package substrate.
6. The three-dimensional packaging method of claim 5, wherein
- before fixing the electronic chip and/or the dummy chip on the first area of the first surface of the photonic chip, the method further comprises: forming a metal blind via in the photonic chip, wherein the metal blind via cuts through the first surface of the photonic chip, and forming the first metal bump at the metal blind via on the first surface of the photonic chip;
- after forming the injection molding material layer on the photonic chip, and before thinning the injection molding material layer and the dummy chip, the method further comprises: thinning the photonic chip from the second surface of the photonic chip so that the metal blind via cuts through the second surface of the photonic chip to form the conductive via, and forming the third metal bump at the conductive via on the second surface of the photonic chip; and
- the fixing of the second surface of the photonic chip on the package substrate comprises bonding the third metal bump on the second surface of the photonic chip with the electric connection point on the package substrate.
7. The three-dimensional packaging method of claim 2, wherein,
- thinning the injection molding material layer, the electronic chip and the dummy chip so that the injection molding material layer, the electronic chip and the dummy chip have the same height.
8. A three-dimensional package structure of a photonic-electronic chip, comprising:
- a photonic chip having a first surface and a second surface opposite to each other;
- a dummy chip fixed on a second area of the first surface of the photonic chip, the dummy chip is a wafer on which no photonic components or electronic components are integrated or included, wherein the photonic chip is provided with an optical coupling interface at the second area, and the dummy chip has a cavity with upper and lower openings connected up and down, and the lower opening of the cavity faces and covers the optical coupling interface; and
- an injection molding material layer located on the first surface of the photonic chip and surrounds the dummy chip, and the cavity is not filled and covered by the injection molding material layer.
9. The three-dimensional package structure of claim 8, further comprising:
- an electronic chip fixed on a first area of the first surface of the photonic chip and surrounded by the injection molding material layer.
10. The three-dimensional package structure of claim 9, further comprising:
- a package substrate on which the second surface of the photonic chip is fixed; and
- the photonic chip has an electric channel for electrically connecting the electronic chip to the package substrate, and the electric channel is connected to a first metal bump provided on the first surface of the photonic chip.
11. The three-dimensional package structure of claim 10, wherein
- the electric channel in the photonic chip is a conductive via, and the conductive via cuts through the photonic chip; and
- the conductive via is connected to an electric connection point on the package substrate by a third metal bump on the second surface of the photonic chip.
12. The three-dimensional package structure of claim 9, wherein
- the injection molding material layer, the dummy chip and the electronic chip have the same height on a side away from the photonic chip.
13. The three-dimensional package structure of claim 8, wherein
- the optical coupling interface is an optical coupling interface of a grating coupler.
14. The three-dimensional package structure of claim 8, further comprising:
- a fiber array which is coupled to the optical coupling interface through the cavity of the dummy chip.
15. A three-dimensional packaging method of a photonic-electronic chip, comprising:
- providing a photonic chip with a first surface and a second surface which are opposite to each other;
- forming an optical coupling adhesive layer on a second area of the first surface of the photonic chip, wherein the photonic chip is provided with an optical coupling interface at the second area, and the optical coupling adhesive layer covers the optical coupling interface; and
- forming an injection molding material layer on the first surface of the photonic chip, the injection molding material layer surrounds the optical coupling adhesive layer, wherein the part of the injection molding material layer above the optical coupling interface has a through hole with upper and lower openings connected up and down, and the coverage area of the lower opening of the through hole covers the optical coupling interface.
16. The three-dimensional packaging method of claim 15, further comprising:
- fixing a dummy chip on the optical coupling adhesive layer;
- wherein forming the injection molding material layer on the first surface of the photonic comprises: forming the injection molding material layer on the photonic chip on which the dummy chip is fixed, so that the injection molding material layer covers the dummy chip and the exposed areas of the first surface of the photonic chip; and thinning the injection molding material layer so that the part of the injection molding material layer on the dummy chip is removed, and
- the method further comprises: after thinning the injection molding material layer, etching the part of the dummy chip above the optical coupling interface, so that the dummy chip is completely etched out, or the dummy chip is partially etched to form a cavity with upper and lower openings connected up and down, and the coverage area of the lower opening of the cavity covers the optical coupling interface.
17. The three-dimensional packaging method of claim 16, further comprising:
- thinning the injection molding material layer and the dummy chip, so that the injection molding material layer and the dummy chip have the same height on the side away from the photonic chip.
18. The three-dimensional packaging method of claim 15, wherein
- before the step of forming the injection molding material layer on the first surface of the photonic chip, the method further comprises a step of fixing the electronic chip on a first area of the first surface of the photonic chip.
19. The three-dimensional packaging method of claim 15, further comprising:
- fixing a dummy chip on the optical coupling adhesive layer; and
- removing a portion of the dummy chip while leaving behind a dam portion of the dummy chip.
20. The three-dimensional packaging method of claim 19, further comprising:
- placing an optical fiber into a groove located on the photonic chip.
Type: Application
Filed: Jul 5, 2023
Publication Date: Nov 2, 2023
Inventors: Chen-Hua Yu (Hsinchu), Hsing-Kuo Hsia (Jhubei City), Sung-Hui Huang (Dongshan Township), Kuan-Yu Huang (Taipei), Kuo-Chiang Ting (Hsinchu), Shang-Yun Hou (Jubei City), Chi-Hsi Wu (Hsinchu)
Application Number: 18/347,188