Phase Locked Loop Patents (Class 375/376)
  • Patent number: 10256823
    Abstract: A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: April 9, 2019
    Assignee: SK hynix Inc.
    Inventors: Hae-Rang Choi, Yong-Ju Kim, Dae-Han Kwon, Shin-Deok Kang
  • Patent number: 10243543
    Abstract: A pulse counting circuit receives pulses supplied by a source circuit having at least two inverted pulse signal supply terminals. The circuit includes a first counter to count pulses of a first pulse signal and supply a first count and a second counter to count pulses of a second pulse signal and supply a second count. A selection circuit selects one of the first and second counts.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: March 26, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Jean Nicolai, Albert Martinez
  • Patent number: 10243765
    Abstract: Described herein are systems and methods of receiving first and second input signals at a first two-input comparator, responsively generating a first subchannel output, receiving third and fourth input signals at a second two-input comparator, responsively generating a second subchannel output, receiving the first, second, third, and fourth input signals at a third multi-input comparator, responsively generating a third subchannel output representing a comparison of an average of the first and second input signals to an average of the third and fourth input signals, configuring a first data detector connected to the second subchannel output and a second data detector connected to the third subchannel output according to a legacy mode of operation and a P4 mode of operation.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: March 26, 2019
    Assignee: KANDOU LABS, S.A.
    Inventors: Amin Shokrollahi, Roger Ulrich
  • Patent number: 10187861
    Abstract: Implementing a distributed boundary clock in situations where book-end devices such as microwave TX/RX pairs must collaborate in achieving PTP on-path support is described. A dedicated channel, generally low-speed compared to the main channel is used to transfer timing from the master side to the slave side using framing and super-framing applied to the digital channel. Time-stamps of events such as super-frame boundaries are communicated between the two sides to enable timing transfer.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: January 22, 2019
    Assignee: Qulsar, Inc.
    Inventor: Kishan Shenoi
  • Patent number: 10164765
    Abstract: Aspects are generally directed to optical receivers and methods for detecting a non-persistent communication superimposed on an overt communication channel. In one example, an optical receiver includes an optical resonator to receive an optical signal having one or more symbols encoded thereon at a modulated symbol repetition rate, the modulated symbol repetition rate being modulated relative to a nominal symbol repetition rate. The optical resonator is configured to emit an intensity-modulated output optical signal that has a variation in an intensity thereof corresponding to a symbol transition in the optical signal. The optical receiver further includes signal processing circuitry including a clock configured to generate a reference signal, a photodetector configured to generate a trigger signal, and a non-persistent communication decoder configured to determine a temporal misalignment between the symbol transition and the nominal symbol repetition rate based on the reference signal and the trigger signal.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: December 25, 2018
    Assignee: RAYTHEON COMPANY
    Inventors: Benjamin P. Dolgin, Andrew Kowalevicz, Gary M. Graceffo
  • Patent number: 10130516
    Abstract: An electronic device for a deaf person is provided. The device includes sound sensors arranged at different positions of the electronic device, and configured for sensing an external sound and converting the sensed external sound into sound signals; a processor connected to the sound sensors, and configured for generating a prompt signal when any sound parameters of the sound signals transmitted by the sound sensors meets a prompt condition; a vibrator connected to the processor, and configured for vibrating upon receiving the prompt signals; a first comparator connected to the processor, and configured for, in response of receiving the prompt signal, determining a sound sensor corresponding to a sound signal with a highest intensity, and generating orientation information corresponding to the sound sensor that corresponds to the sound signal with the highest intensity; and an indicator connected to the first comparator, and configured for indicating the orientation information.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: November 20, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Mubing Li, Chungchun Chen, Xiaochuan Chen, Haisheng Wang, Jiantao Liu, Xue Dong, Jinghua Miao, Lin Lin
  • Patent number: 10135604
    Abstract: The present disclosure relates to a receiver and to a method implemented in the receiver for recovering a signal clock from a received data signal. Successive edge transitions between successive data samples of the received data signal are detected according to a clock recovered in the receiver. The recovered clock is adjusted based on a combination of weights assigned to at least some edge transitions among the plurality of successive edge transitions. In particular, (i) each very early transition is assigned a first weight having a first sign, (ii) each early transition is assigned a second weight having the first sign, (iii) each late transition is assigned a third weight having a second sign opposite from the first sign, and (iv) each very late transition is assigned a fourth weight having the second sign.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: November 20, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Behzad Dehlaghi, Shayan Shahramian
  • Patent number: 10122350
    Abstract: One embodiment describes a Josephson transmission line (JTL) system. The system includes a plurality of JTL stages that are arranged in series. The system also includes a clock transformer comprising a primary inductor configured to propagate an AC clock signal and a secondary inductor arranged in a series loop with at least two of the plurality of JTL stages. The clock transformer can be configured to propagate a single flux quantum (SFQ) pulse to set a respective one of the plurality of JTL stages in response to a first phase of the AC clock signal and to reset the respective one of the plurality of JTL stages in response to a second phase of the AC clock signal that is opposite the first phase.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: November 6, 2018
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Donald L. Miller, Ofer Naaman
  • Patent number: 10114072
    Abstract: A processing method and electronic apparatus for a digital signal are provided. The method includes: detecting the quality of a first eye in an eye diagram of the digital signal; equalizing the digital signal; detecting the quality of a second eye in the eye diagram of the equalized digital signal; determining whether the quality of the second eye superior to the quality of the first eye by a predetermined threshold; and if so, outputting the digital signal, or else again equalizing and performing subsequent steps on the auto-compensated digital signal. The above solution is capable of effectively improving the quality of eyes in the eye diagram of the digital signal.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: October 30, 2018
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Yuan Yuan, Wen cai Lu
  • Patent number: 10110210
    Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a data path to receive data information based on timing of a data capture clock signal, a clock path including a delay circuit to apply a time delay to an input clock signal and generate a delayed clock signal, a clock tree circuit to provide the data capture clock signal and a first feedback clock signal based on the delayed clock signal, a circuitry including latches to sample the input clock signal based on timing of the feedback clock signal and provide sampled information, and a controller to control the delay circuit based on the sampled information in order to cause the data capture clock signal to be out of phase with the input clock signal by one-fourth of a period of the input clock signal.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Chenchu Punnarao Bandi, Amit Kumar Srivastava
  • Patent number: 10103817
    Abstract: An optical receiver adapted to convert a received optical signal into a phase change of a timing signal to generate a first modified timing signal and to generate a data signal by comparing the first modified timing signal with a reference signal.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: October 16, 2018
    Assignee: Commissariat à L'Énergie Atomique et aux Énergies Alternatives
    Inventors: Robert Polster, Ivan Miro Panades, Yvain Thonnart
  • Patent number: 9984762
    Abstract: Apparatus for managing power in a data storage device, such as a solid state drive (SSD). In some embodiments, an energy management circuit supplies electrical power to a non-volatile memory (NVM). The energy management circuit has cascaded first and second E-Fuse switch circuits each with an input terminal and an output terminal. The second E-Fuse switch circuit receives input power from the first E-Fuse switch circuit used as a rail voltage for the device. The second E-Fuse switch circuit is configured to monitor the rail voltage, deactivate the first E-Fuse switch circuit responsive to the rail voltage falling below a predetermined threshold, and supply backup power to the device from a backup power source.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: May 29, 2018
    Assignee: Seagate Technology LLC
    Inventors: Nikhil Seshasayee, Keith Neil MacLean
  • Patent number: 9979408
    Abstract: Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: May 22, 2018
    Assignee: Analog Devices, Inc.
    Inventors: Christopher Mayer, David J. McLaurin, Christopher W. Angell, Sudhir Desai, Steven R. Bal
  • Patent number: 9979406
    Abstract: System and methods for a clock system disciplined to an external reference. In one embodiment, the clock includes a flywheel oscillator controlled by the external reference and a free running holdover oscillator. The holdover oscillator provides increased accuracy during periods of holdover when the external reference is not available. In a further embodiment, the flywheel oscillator is additionally controlled by a phase-locked loop with the holdover oscillator frequency as input, and a control switch for switching the flywheel oscillator to analog control if the phase-locked loop exhibits a fault.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: May 22, 2018
    Assignee: Arbiter Systems, Incorporated
    Inventors: William J. Dickerson, Robert T. Dickerson
  • Patent number: 9973196
    Abstract: Apparatus for clock synchronization comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: May 15, 2018
    Assignee: NXP B.V.
    Inventors: Jos Verlinden, Remco van de Beek, Stefan Mendel
  • Patent number: 9960774
    Abstract: A system and method for correcting for phase errors, in a phase locked loop, resulting from spread spectrum clocking involving a reference clock signal having a frequency modulation. A correction generation circuit generates an offset signal, that when injected after the charge pump of the phase locked loop, causes the voltage controlled oscillator to produce a signal with substantially the same frequency modulation, thereby reducing the phase error. The correction generation circuit may include a timing estimation circuit for estimating the times at which transitions (between positive-sloping and negative-sloping portions of the triangle wave) occur, and an amplitude estimation circuit for estimating the amplitude of the offset signal that results in a reduction in the phase error.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: May 1, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Amir Amirkhany, Ashkan Roshan Zamir
  • Patent number: 9941889
    Abstract: A circuit for compensating quantized noise in fractional-N frequency synthesizer, comprising a PLL circuit that locks a phase compensated signal to a phase of a reference phase, wherein the phase lock loop circuit comprises a frequency divider and a phase frequency detector; a sigma-delta modulation and phase difference calculator coupled to the frequency divider generating an accumulated phase error by accumulating all previous differences between an input of the frequency divider and an output of the frequency divider within a period; a digital controlled delay line coupled to both the frequency divider and the SDM and Phase Difference calculator and generates the phase compensated signal by multiplying the accumulated phase error with a delay control word; and the phase frequency detector further generates a phase error by comparing the phase compensated signal with the reference clock.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: April 10, 2018
    Assignee: BEKEN CORPORATION
    Inventors: Dawei Guo, Caogang Yu
  • Patent number: 9875778
    Abstract: Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: January 23, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Tsuneo Abe
  • Patent number: 9866221
    Abstract: Embodiments are directed to a system for synchronizing switching events. The system includes a controller, a clock generator communicatively coupled to the controller and a delay chain communicatively coupled to the controller. The delay chain is configured to perform a plurality of delay chain switching events in response to an input to the delay chain. The controller is configured to initiate a synchronization phase that includes enabling the clock generator to provide as an input to the delay chain a clock generator output at a synchronization frequency, wherein the clock generator output passing through the delay chain synchronizes the plurality of delay chain switching events to occur at the synchronization frequency resulting in a frequency of an output of the delay chain being synchronized to the synchronization frequency of the clock generator output.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: January 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith A. Jenkins, Barry P. Linder
  • Patent number: 9832288
    Abstract: An extremely high frequency (EHF) protocol converter may include a transducer, an EHF communication circuit, a protocol conversion circuit, and a circuit port. The transducer may be configured to convert between an electromagnetic EHF data signal and an electrical EHF signal. The EHF communication circuit may be configured to convert between a baseband data signal and the electrical EHF signal. The protocol conversion circuit may be adapted to convert between the baseband data signal having data formatted according to a first data protocol associated with a first external device and a second baseband data signal having data formatted according to a second data protocol associated with a second external device. The second data protocol may be different from the first data protocol. The circuit port may conduct the second baseband data signal to the second external device.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: November 28, 2017
    Assignee: KEYSSA, INC.
    Inventors: Gary D. McCormack, Roger Isaac, Eric Almgren
  • Patent number: 9813174
    Abstract: Provided are a time correction method and a time correction apparatus for a slave clock device. The method is applied to a slave clock device, wherein the method includes: acquiring background traffic information, in a running process, of the slave clock device; acquiring a deviation correction value according to the background traffic information and a fitted function reflecting delay on an asymmetric link; and correcting a synchronization time, which is output from the slave clock device, in real time according to the deviation correction value. With the above technical solution, the technical problem in related art that there is no technical solution for effectively eliminating a dynamic delay change of an asymmetric link due to a background traffic change is solved, thereby greatly reducing the impact of the traffic change on the asymmetric link delay.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: November 7, 2017
    Assignee: XI'AN ZHONGXING NEW SOFTWARE CO., LTD
    Inventor: Bin Wang
  • Patent number: 9806880
    Abstract: An example phase-locked loop (PLL) includes a digital filter, an oscillator, and a time-to-digital converter (TDC). The digital filter is configured to sample at a discrete time that is responsive to a reference clock signal received at the digital filter. The oscillator is coupled to the digital filter and configured to generate an output signal of the PLL. The TDC is coupled to the oscillator to determine a phase difference between the output signal and the reference clock signal. The TDC also provides a time signal to the digital filter that is based on the phase difference and is representative of an instantaneous rate of operation of the PLL. The digital filter is further configured to adjust a response characteristic of the digital filter according to the time signal.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: October 31, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Magnus Olov Wiklund, Emanuele Lopelli, Charles Wang, Mahbod Mofidi
  • Patent number: 9774319
    Abstract: A phase detection circuit includes a sampling signal generation circuit configured to generate a plurality of sampling signals in response to a plurality of phase change clocks having different phases and data; a charging voltage generation circuit configured to compare the plurality of sampling signals, and change a voltage level of one charging voltage between a first charging voltage and a second charging voltage; and a comparison circuit configured to compare voltage levels of the first and second charging voltages, and generate a result signal.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: September 26, 2017
    Assignee: SK hynix Inc.
    Inventors: Myeong Jae Park, Kyung Hoon Kim, Kyu Young Kim, Woo Yeol Shin
  • Patent number: 9755817
    Abstract: A phase interpolator is provided with a plurality of slices. Each slice includes a first switch for mixing a first clock signal into an interpolated output signal and a second switch for mixing a second clock signal into the interpolated output signal. In response to a high-resolution signal, at least one of the slices may switch on both the first switch and the second switch.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: September 5, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Eskinder Hailu, Hanan Cohen, Li Sun, Zhiqin Chen
  • Patent number: 9755653
    Abstract: A phase detector including a first latch and a control circuit is provided. The first latch generates a first output signal and a second output signal in response to a phase difference between a first input signal and a second input signal. Each of the first and second output signals includes first phase information and second phase information of the phase difference. The control circuit generates a phase indicating signal in response to the first phase information of the phase difference. The phase indicating signal indicates a relative position between the first input signal and the second input signal.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: September 5, 2017
    Assignee: MEDIATEK INC.
    Inventors: Pang-Ning Chen, Yu-Li Hsueh, Pi-An Wu
  • Patent number: 9729159
    Abstract: Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage controlled oscillator (VCO) circuitry having a bias signal that sets a frequency range, circuitry that shifts the VCO circuitry to operate in one of the frequency ranges, and other circuitry to compare/calibrate signals and/or set the bias current. According to further implementations, as a function of operation of the circuitry, an operating frequency range of the VCO circuitry may be shifted to a different operating frequency range, and closed-loop, continuous frequency range, auto-calibration or other features may be provided.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: August 8, 2017
    Assignee: GSI Technology, Inc.
    Inventor: Yu-Chi Cheng
  • Patent number: 9716507
    Abstract: A delay circuit includes a delay line configured to output an output signal by imposing a delay value on an input signal. The delay circuit further includes an arithmetic unit configured to calculate a control code for the delay value based on delay codes. The delay circuit further includes a delay locked loop (DLL) configured to generate the delay codes based on a clock signal. The delay circuit further includes a controller configured to suspend operation of the DLL when the clock signal operates at a first frequency, to set the DLL to operate based on a second frequency when the DLL is suspended, and to resume operation of the DLL when the clock signal operates at the second frequency without the need to relock the DLL.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: July 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Muhammad Nummer, Rob Abbott
  • Patent number: 9705514
    Abstract: A hybrid analog/digital control approach for a digitally controlled oscillator augments a digital control path with an analog control path that acts to center the digital control path control signal within its range. The digital control path controls a first group of varactors within an oscillator tank circuit using a digital filter and a delta sigma modulator, which generates a dithered control signal for at least one of the first group of varactors. The analog control path controls a second group of varactors in the tank circuit but actively tunes only one varactor at a time. The analog control path performs relatively low bandwidth centering of the digital control signal resulting in negligible impact on PLL bandwidth, stability, and noise performance. Instead, the digital control path dominates in setting the PLL dynamic and noise behavior, and has reduced range requirements due to the centering action.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: July 11, 2017
    Assignee: Silicon Laboratories Inc.
    Inventor: Michael H. Perrott
  • Patent number: 9685962
    Abstract: A clock data recovery apparatus includes an oscillator, a phase detector and an oscillator control circuit. The oscillator generates an original clock signal. The phase detector includes a first sampling circuit, a frequency dividing circuit, a second sampling circuit and a selecting circuit. The first sampling circuit samples a data signal using the original clock signal to generate a first set of sample results. The frequency dividing circuit divides the original clock signal to generate a frequency divided clock signal. The second sampling circuit performs sampling using the frequency divided clock signal to generate a second set of sample results. The selecting circuit selectively outputs one of the first and second sets of sample results as a final set of sample results. The oscillator control circuit controls the oscillator according to the final set of sample results.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: June 20, 2017
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Meng-Tse Weng, Chun-Wen Yeh, Jiunn-Yih Lee
  • Patent number: 9667407
    Abstract: A multichannel receiver includes multiple receiver modules, each having: a voltage-controlled oscillator that generates a clock signal with a controllable frequency; a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal; a sampling element that produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal; a timing error estimator that operates on the digital receive signal to provide timing error estimates; a phase control filter that derives, from the timing error estimates, a phase control signal supplied to the phase interpolator, wherein the phase control signal minimizes a phase error between the sampling signal and the analog receive signal; and a frequency control filter that derives, from the timing error estimates, a frequency control signal for controlling the clock signal frequency, wherein the frequency control signal minimizes a frequency offset between the clock signal and the analog receive
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: May 30, 2017
    Assignee: CREDO TECHNOLOGY GROUP LIMITED
    Inventors: Xike Liu, Kei Peng, Chan Ho Yeung, YiFei Dai, Lawrence (Chi Fung) Cheng, Runsheng He
  • Patent number: 9634678
    Abstract: A technique for reducing noise in an output clock signal of a feedback control system (e.g., a PLL or FLL) samples rising edge errors and falling edge errors between a reference clock signal and a feedback clock signal. The technique applies edge alignment correction to reduce or eliminate edge alignment errors between the reference clock signal and the feedback clock signal. A PLL generates an output clock signal based on a control signal generated using an error signal generated based on a rising edge difference between a rising edge of an input clock signal and a corresponding edge of an edge alignment corrected feedback clock signal and based on a falling edge difference between a falling edge of the input clock signal and a corresponding edge of the edge alignment corrected feedback clock signal. The edge alignment corrected feedback clock signal is partially based on the output clock signal.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: April 25, 2017
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Brian G. Drost, Vaibhav Karkare
  • Patent number: 9614659
    Abstract: A Continuous Time Linear Equalizer (CTLE) and a method of operating a CTLE in a receiver for a Pulse Amplitude Modulation (PAM) signal are disclosed. The method includes initiating equalization using an initial equalization setting that is optimized to meet a first objective and responsive to a determination, shifting to a final equalization setting that is optimized to meet a second objective.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: April 4, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Reza Hoshyar, Kevin Zheng, Nirmal Warke, Wenting Zhou, Ali Kiaei, Ahmad Bahai
  • Patent number: 9608645
    Abstract: In one implementation an output signal of an oscillator is varied to be within a desired frequency band with respect to a reference signal, the output signal having a plurality of phases. The implementation may include comparing the output signal with the reference signal, counting falling edges about each phase of the number of phases in a predetermined time period and summing to define a count output; comparing the count output with a product of the number of phases of the output signal and the factor to define a comparison, generating a control signal based upon the comparison, and inputting the control signal to the oscillator to alter the output signal thereof.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: March 28, 2017
    Assignee: Infineon Technologies AG
    Inventors: Chin Yeong Koh, Kar Ming Yong
  • Patent number: 9602114
    Abstract: A design method for a phase-locked loop comprises: a controlled-frequency oscillator; a phase comparator, to determine a phase difference between an output signal of the controlled-frequency oscillator and a reference signal; a corrector to receive as input a signal representative of the phase difference and to generate at its output a first correction signal; at least one second corrector, to receive as input a signal representative of or affected by a phase noise of the reference signal or of the output signal of the controlled-frequency oscillator and to generate at its output a second correction signal; and a circuit for generating a slaving signal for the controlled-frequency oscillator on the basis of the first and second correction signals; the method using the H-infinity method. Method for fabricating such a loop comprising a design step implementing this method. Phase-locked loop thus obtained.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: March 21, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Michael Pelissier, Anton Korniienko, Mykhailo Zarudniev, Gèrard Scorletti, Olesia Mokrenko, Eric Blanco, Patrick Villard, Gèrard Billiot
  • Patent number: 9571111
    Abstract: A method and apparatus and computer program product for calibrating a Phase Lock Loop (PLL) that reduces a PLL lock time for subsequent calibrations to thereby improve an overall system time and latency. The system and method for calibrating obviates effect of Process, Voltage and Temperature to achieve a faster PLL lock.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: February 14, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Hayden C. Cranford, Jr., Venkatasreekanth Prudvi, Rajesh Agraramachandrarao, Sandeep Tippannanavar, Neelamekakannan Alagarsamy
  • Patent number: 9571083
    Abstract: In some example embodiments, there may be provided an apparatus. The apparatus may include a delay line including a plurality of cells; and tuning circuitry coupled to the delay line and configured to generate a first output and a second output to tune the delay of the delay line, wherein the first output tunes in aggregate the plurality of cells of the delay line, and wherein the second output tunes each of the plurality of cells separately. Related methods, systems, and articles of manufacture are also disclosed.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: February 14, 2017
    Assignee: Nokia Technologies Oy
    Inventor: Tapio Ilmari Rapinoja
  • Patent number: 9571077
    Abstract: A method and device for dynamically updating a phase interpolator circuit module using a phase update circuit module. The method can include interpolating a set of input clock phases based on a phase interpolator code input and sequentially updating the rising edge generator and falling edge generator starting from a synchronizer update signal. The dynamic sequential update involves disabling a rising edge ramp signal while updating a rising edge interpolator and generating old clock out falling edge according to an old phase interpolator code input, disabling a falling edge ramp signal while updating a falling edge interpolator, enabling the rising edge ramp signal and generating a new clock out rising edge according to a new phase interpolator code input, and enabling the falling edge ramp signal and generating a new clock out falling edge according to the new phase interpolator code input.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: February 14, 2017
    Assignee: RAMBUS INC.
    Inventors: Cosmin Iorga, James L. Gorecki
  • Patent number: 9542985
    Abstract: The present disclosure includes methods and systems for channel skewing. One or more methods for channel skewing includes providing a number of groups of data signals to a memory component, each of the number of groups corresponding to a respective channel, and adjusting a phase of a group of data signals corresponding to at least one of the number of channels such that the group of data signals are skewed with respect to a group of data signals corresponding to at least one of the other respective channels.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: January 10, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Travis E. Swanson, Paul J. Voit, Ryan M. Przybilla
  • Patent number: 9537585
    Abstract: A circuit according to an example includes a digital-to-time converter and a signal processing circuit coupled to the digital-to-time converter and configured to generate a processed signal derived from a signal provided to the signal processing circuit, the processed signal including a predetermined phase relation with respect to the signal provided to the signal processing circuit, wherein the circuit is configured to receive a reference signal and to generate an output signal based on the received reference signal. The a measurement circuit is configured to measure a delay between the output signal and the reference signal, wherein the output of the digital-to-time converter is coupled to a memory configured to store calibration data of the digital-to-time converter based on the measured delay.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: January 3, 2017
    Assignee: Intel IP Corporation
    Inventors: Thomas Mayer, Stefan Tertinek, Peter Preyler
  • Patent number: 9537496
    Abstract: Provided is a method for driving a SERDES circuit, which may reduce waste of a space of the SERDES circuit. The circuit driving method includes generating a common clock signal from a common phase locked loop (PLL) supplying a clock signal to a serializer/deserializer (SERDES) circuit, distributing the common clock signal to an eye opening monitor and a data transmission lane in the SERDES circuit, and driving the eye opening monitor and the data transmission lane using the common clock signal.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: January 3, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hwang-Ho Choi, Jong-Shin Shin, Seung-Hee Yang, Chang-Kyung Seong
  • Patent number: 9526079
    Abstract: A sensor, a time alignment apparatus, a time processing method, and a time alignment method are provided. The sensor begins to sense at least one sensed data at a first local time instant. The sensor transmits a response message at a second local time instant. The response message carries the at least one sensed data, the first local time instant, and the second local time instant. The time alignment apparatus receives the response message at a first global time instant. The time alignment apparatus calculates a second global time instant that the at least one sensed data being sensed according to a required transmission time between the time alignment apparatus and the sensing apparatus, a clock skew rate between the time alignment apparatus and the sensing apparatus, the first global time instant, the first local time instant, and the second local time instant.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: December 20, 2016
    Assignee: Institute For Information Industry
    Inventors: Chi-Sheng Shih, Yen-Chieh Cheng, Chang Min Yang
  • Patent number: 9520889
    Abstract: A frequency synthesizer includes circuitry configured to generate two or more feedback clocks based on the oscillation signals output from a voltage-controlled oscillator. The circuitry also modulates the feedback clocks based on fractional offsets from a reference clock frequency for input into two or more phase and frequency detectors. Multiple charge pump circuits receive inputs from these phase and frequency detectors. The current from these charge pumps is summed and input to a low pass filter. The output of the filter represents an average of the time difference between the reference clock and the multiple feedback clocks.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: December 13, 2016
    Assignee: BROADCOM CORPORATION
    Inventor: Gregory Alyn Unruh
  • Patent number: 9520823
    Abstract: In accordance with an embodiment, an actuator control circuit includes a driver circuit connected to a ringing characteristic determination circuit. A signal generator that is configured to generate an output signal having first period that has first and second portions where the first portion longer than the second portion is connected to the ringing characteristic determination circuit. Another embodiment includes a method for controlling an actuator by determining a resonant frequency and a ringing amplitude of an actuator signal; generating a control signal in response to the resonant frequency and the ringing amplitude of the actuator signal; and causing the actuator to move in response to the second drive signal.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: December 13, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yoshihisa Tabuchi, Tomonori Kamiya
  • Patent number: 9514831
    Abstract: A circuit for providing a plurality of clock signals of differing frequencies includes: a phase locked loop section including a first voltage controller oscillator, connected to receive a reference clock value and generate therefrom a first voltage level, wherein the first voltage controller oscillator receives the first voltage level and generates therefrom a first clock signal; and one or more second voltage controller oscillators, each connected to receive the first voltage level, a corresponding trim value and a corresponding control voltage and derive therefrom a corresponding second clock signal.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: December 6, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Jonathan Huynh, Sung-En Wang, Steve Choi, Jongmin Park
  • Patent number: 9508417
    Abstract: Apparatuses and methods for controlling timing circuit locking and/or latency during a change in clock frequency (e.g. gear down mode) are described herein. An example apparatus may include a timing circuit. The timing circuit may be configured to provide a clock signal to the forward path, adjust a rate of the clock signal responsive to receipt of a command to adjust the rate of the clock signal, select a feedback clock signal responsive to a loop delay of the timing circuit, and provide a control signal to an adjustable delay circuit of the forward path circuit. Another example apparatus may include a forward path configured to delay a signal based at least in part on a loop delay and a latency value, and a latency control circuit configured to provide an adjusted latency value as the latency value responsive to receipt of a command, wherein the forward path is configured to operate at least in part at an adjusted clock rate responsive to receipt of the command.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: November 29, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Jongtae Kwak
  • Patent number: 9490821
    Abstract: An apparatus is disclosed in which a clock signal may propagate through a delay circuit. The delay circuit may include a first and a second delay stage, in which each delay stage may be programmable for one of two delay times, depending on a value of a respective control signal to each delay stage. The delay circuit may also include circuitry which may change the value of the respective control signal from a first value to a second value. The circuitry may change the value of the respective control signal responsive to a determination that an output of the first stage and an output of the second stage are equal.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: November 8, 2016
    Assignee: Apple Inc.
    Inventors: Gilbert H. Herbeck, Gregoire J. Le Grand de Mercey, Yair R. Koren, Jung Wan Kim
  • Patent number: 9484936
    Abstract: An integrated circuit comprises a dual port modulator and a voltage controlled oscillator (VCO). The dual port modulator has a first input for receiving a transmitter modulation signal, a first output for providing a fractional portion of a high port modulation signal, a second output for providing a integer portion of the high port modulation signal, and a third output for providing a low port modulation signal. The VCO is coupled to the dual port modulator and has a first input for receiving the fractional portion of the high port modulation signal, a second input for receiving the integer portion of the high port modulation signal, a third input for receiving a tuning signal based on the low port modulation signal, and a first output for outputting an RF signal. The dual port modulator provides a signed single bit signal for generating the fractional portion of the high port modulation signal.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: November 1, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Khurram Waheed, Kevin B. Traylor
  • Patent number: 9484935
    Abstract: Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO having a tuning voltage input and a frequency tuning circuit configured to set a frequency band setting of the VCO. The frequency tuning circuit can include a voltage monitor configured to compare the voltage level of the tuning voltage input to one or more tuning voltage threshold levels, a control circuit configured to control at least a frequency band setting and a bias current setting of the VCO, and an amplitude detection circuit configured to compare an amplitude of an oscillation signal of the VCO to one or more amplitude threshold levels.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: November 1, 2016
    Assignee: Analog Devices Global
    Inventors: Hyman Shanan, Michael F. Keaveney
  • Patent number: 9473115
    Abstract: Technologies are generally described for quadrature-based injection-locking of ring oscillators. In some examples, an external signal may be injected into a ring oscillator. Phase signals may be measured from within the ring oscillator and used to determine a mean quadrature error (MQE) that characterizes the difference in frequency between the external signal and the ring oscillator's natural frequency. A control signal may then be generated from the MQE and used to adjust the ring oscillator natural frequency to reduce the difference between the ring oscillator natural frequency and the external signal.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: October 18, 2016
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Mayank Raj, Azita Emami
  • Patent number: RE46336
    Abstract: Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: March 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chang Lin, Chan-Hong Chern, Steven Swei, Ming-Chieh Huang, Tien-Chun Yang