Abstract: A fast clock domain crossing architecture for high frequency trading includes a receiver that recovers data and a clock of a first clock domain from a communication from an exchange, functional circuitry that generates and a buy/sell command based on the recovered data and the recovered clock, format circuitry that formats the command in a second clock domain, and a transmitter that transmits the formatted command to the exchange. The architecture further includes error detection circuitry that detects bit errors that arise from an asynchronous boundary of the clock domains without increasing a round-trip latency, and/or synchronization circuitry that synchronizes the clock domains, where the synchronization circuitry includes a cleanup PLL that filters input jitter and a phase detector and variable delay line that compensate for latency within the architecture.

Abstract: Methods/systems employ randomly jittered under-sampling to reduce a sampling rate required to estimate the amplitude of high-frequency signals in circuit breakers, power meters, and other digital signal processing applications. The methods/systems can greatly reduce the nominal sampling rate for applications where RMS, peak and mean estimates of the signal are desired for both the entire band-limited signal and separate estimates for each frequency component. This can in turn result in large cost savings, as less complex and thus less expensive controllers and related components may be used to perform the sampling. As well, the methods/systems herein can provide reasonably accurate waveform estimates that allow additional cost savings in bill of materials (BOM) and printed circuit board assembly (PCBA) footprint and real-estate by eliminating the need for certain analog components, such as signal conditioning components.

Abstract: This technology is to enable high quality audio reproduction on the reception side without supplying a transmission clock using a clock signal line from the reception side to the transmission side. The transmission apparatus receives encoded data capable of clock recovery from a reception apparatus (external device), generates an audio clock on the basis of a carrier clock recovered from the encoded data, and transmits audio data to the reception apparatus in synchronization with the audio clock. The reception apparatus transmits the encoded data capable of clock recovery to the external device in synchronization with the carrier clock generated on the basis of an self-generating audio clock, receives the audio data from the transmission apparatus (external device), and processes the audio data on the basis of the self-generating audio clock.

Abstract: Embodiments of the present disclosure provide a signal transmitting method. According to the method, in a signal transmitting process, before entering a digital to analog converter (DAC), a first frequency modulated signal of a high-pass channel is first subjected to nonlinear compensation and gain mismatch compensation. In the process, a nonlinear compensation coefficient and a gain mismatch compensation coefficient are determined according to an output voltage of the high-pass channel and an output frequency of a voltage-controlled oscillator (VCO) during a calibration stage.

Abstract: A neural processing unit (NPU) is proposed. The NPU may comprise a first circuit configured to perform operations for an artificial neural network (ANN) model, and arranged for a plurality of processing elements (PE) groups including a plurality of PEs, and a second circuit configured to operate as a clock divider configured to generate a plurality of clock signals having different phases, respectively, by dividing a source clock signal and provide the plurality of clock signals to the plurality of PE groups. A first clock signal of the plurality of clock signals may be provided to a first PE group of the plurality of PE groups, and a second clock signal of the plurality of clock signals may be provided to a second PE group of the plurality of PE groups.

Abstract: Technologies for converting serial data stream to a parallel data and strobe scheme with data strobe preamble information in the serial data stream are described. A device includes an interface circuit that receives a serial data stream and converts the serial data stream to parallel data and a data strobe (DQS) signal associated with the parallel data using N-bit header fields inserted into the serial data stream. The N-bit header fields specify DQS preamble information for the parallel data.

Abstract: One example includes a circuit. The circuit includes a first transistor having a first control terminal, a first current terminal, and a second current terminal. The first control terminal can be a first input to the circuit. The circuit also includes a second transistor having a second control terminal, a first current terminal, and a second current terminal. The second control terminal can be a second input to the circuit. The circuit also includes an adaptive bias current source coupled to the second current terminal of the respective first and second transistors. The circuit further includes a voltage offset generator coupled in parallel with the second transistor.

Abstract: A tuning array selection circuit, together with a decoder and a voltage controlled oscillator (VCO), can be employed to overcome some disadvantages of previous methods of phase locked loops. For example, a VCO can include a coarse tuning array and a fine tuning array. A coarse tuning array can be used to tune a VCO to generate a signal within a wide frequency range. A fine tuning array can be used to tune a VCO to generate a signal within a narrow frequency range. In one embodiment, the narrow frequency range is within the wide frequency range. The tuning array selection circuit can coordinate selection of appropriate fine tuning devices and narrow tuning devices to reduce transition jitter and the risk of fail locking of phase locked loops.

Abstract: A circuit and a method for removing spread spectrum are provided. The circuit includes a data clock recovery module and a clock extraction module that are connected. The data clock recovery module performs clock recovery on an input signal carrying spread spectrum information to obtain a parallel clock signal and a first signal, where the parallel clock signal includes frequency information and phase information, and the first signal includes the frequency information. The clock extraction module divides a frequency of the parallel clock signal to obtain a reference clock signal; acquires a feedback clock signal based on the first signal; acquires a de-spread clock signal based on the reference clock signal and the feedback clock signal, where the de-spread clock signal includes the phase information and does not include the frequency information; and divides a frequency of the de-spread clock signal to obtain an output clock signal.

Abstract: A timing recovery method includes the following operations: performing a time domain timing recovery process according to a predefined cyclic prefix portion of a first symbol during a downstream time-division duplexing frame period to tune a phase locked loop circuit; and performing a frequency domain timing recovery process according to at least one second symbol that follows the first symbol during the downstream time-division duplexing frame period to tune the phase locked loop circuit.

Abstract: An electronic apparatus includes a controller. The controller includes an instruction executer configured to generate or acquire data, an issuer configured to accept a request and issues a time stamp, a first updater configured to update a first counter value according to a first operation, a second updater configured to update a second counter value in accordance with issuance of the time stamp, a first non-volatile memory to hold the first counter value and a secret key, and a volatile register to hold the second counter value. The time stamp is a message authentication code or a digital signature issued from the first and second counter values and the data. The second counter value is not stored in the first non-volatile memory.

Abstract: An electronic device includes a receiver circuit, a clock generator circuit, and a clock control circuit. The receiver circuit receives first clock information associated with a first clock of another electronic device. The clock generator circuit generates a second clock for the electronic device. The clock control circuit obtains second clock information associated with the second clock, generates a clock control signal according to the first clock information and the second clock information, and outputs the clock control signal to the clock generator circuit, where the clock generator circuit adjusts the second clock in response to the clock control signal.

Abstract: An method of determining a symbol according to a phase difference between input signals input in order of time may include calculating a first phase difference between a phase of a first previous signal received prior to a target signal and a phase of a second previous signal received prior to the first previous signal; calculating a second phase difference between a phase of the target signal and the phase of the second previous signal; calculating target likelihoods based on the first phase difference and the second phase difference; and determining an expected phase difference between the target signal and the first previous signal or an expected symbol for the target signal, based on the target likelihoods.

Abstract: A semiconductor package includes source clock circuitry to generate a source clock signal. Reference clock circuitry generates a reference clock signal. A first timing circuit includes a first source clock input to receive the source clock signal. First fan-out circuitry distributes the received source clock signal as a first distributed clock signal to a first set of clocked devices. A first delay circuit delays the received source clock signal by a first delay value based on a first phase difference between the first distributed clock signal and the reference clock signal.

Abstract: The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR circuit includes a phase detector, a loop filter, a SSC demodulator, a control code generator and a phase interpolator. The PLL is configured to generate a clock signal with SSC modulation and a SSC direction signal. The phase detector is configured to compare phases of an input signal and an output clock signal to generate a detection result, wherein the input signal is with SSC modulation. The loop filter is configured to filter the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is configured to generate a control code according to the filtered signal and the control signal to control the phase interpolator to use the clock signal to generate the output clock signal.

Abstract: In accordance with an embodiment, a timing sequence generation circuit includes: a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time with respect to one another; a first shift register comprising a flip-flop having a clock input coupled to a clock signal input of the first shift register and an output coupled to an output of the first shift register; and a first circuit configured to: select a clock signal from among the clock signals; and deliver the selected clock signal to the clock signal input of the first shift register

Abstract: A clock circuit is provided for clocking a high-speed data communication interface. The interface has (N) lanes. The clock circuit includes a triangle wave generator, N clock generators, and N lane FIFOs. The triangle wave generator provides P phase outputs, wherein P is greater than or equal to N. Each clock generator receives an associated one of the phase outputs and generates a clock signal having a frequency based upon the phase output. Each FIFO receives data and an associated one of the clock signals, and provides the data at a clock frequency associated with the associated clock signal.

Abstract: A system for receiving signals transmitted via serial links includes an equalizer for accessing a digitized communications signal and producing an equalized output signal, and a fast equalization module for determining output data corresponding to the communications signal. The fast equalization module includes a filter to access an output of the equalizer, a slicer module to access an output of the filter and produce a data output corresponding to the communications signal, a lookup table to provide filtering coefficients to the filter, and a coefficient improvement module to improve the coefficients based on an error signal from the filter. The coefficient improvement module is configured to update the coefficients in the lookup table.

Abstract: A mobile terminal and its methods of use are disclosed herein. In an embodiment, a mobile terminal for enabling radio communications includes a common reference device, frequency conversion circuitry, and pilot tracking circuitry and/or signal tracking circuitry. The common reference device provides a common reference signal for frequency conversions. The frequency conversion circuitry uses the common reference signal from the common reference device to perform a frequency conversion of incoming or outgoing communications. The pilot tracking circuitry determines a frequency error based on a frequency of a received pilot signal and causes an adjustment to the frequency conversion performed by the frequency conversion circuitry based on the frequency error. The signal tracking circuitry determines a frequency error signal based on the frequency of an incoming communication signal and causes an adjustment to the frequency conversion performed by the frequency conversion circuitry based on the frequency error.

Abstract: Design and methods for implementing a Rational Ratio Multiplier (RRM) with close to 50% duty cycle. This invention gives an optimal way to implement an RRM that saves both area and power for a given design and is able to achieve a good accuracy of the output clock with a difference between the high period and the low period of the output clock by only half a cycle of the input clock which is the closest to get to a 50% duty cycle clock.

Abstract: A transmitter and a receiver are provided. The transmitter includes a processing unit configured to receive a clock signal and a data signal, set a value of a consecutive identical digit (CID) value related to the data signal and generate a modulation signal during a unit interval (UI) based on the data signal and the CID value, and a transmitter driver configured to output output signals having different voltage levels during the unit interval by receiving the modulation signal.

Abstract: A neural network operation apparatus and method are disclosed. The neural network operation apparatus may include an adder configured to perform addition of data for performing a neural network operation and main data, a first multiplexer configured to output one of an output result of the adder and the main data based on a reset signal, a second multiplexer configured to output one of the main data and a quantization result of the data based on a phase signal, and a controller configured to control the first and second multiplexers by generating the reset signal and the phase signal.

Abstract: A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in an output of the clock gating circuit. The clock gating circuit is disabled when an output of the counter indicates a preconfigured maximum count value. An edge synchronization circuit that synchronizes edges in the base clock signal with edges in a data signal received over the one-wire bus ignores edges in the data signal while the counter output has a value that is less than the maximum count value, and resets the counter in response to an edge detected in the data signal received over the one-wire bus.

Abstract: This disclosure relates to a digital comparator coupled to a pair of pull-up resistors and a pair of pull-down resistors whereby both pairs of resistors are coupled to an output terminal of a low dropout (LDO) regulator. In particular, the digital comparator comprises an edge detector module, a consecutive two-edge detector module and a consecutive three-edge detector module whereby the edge detector module is configured to receive two clock signals as inputs and after being processed by these three modules, to pull-up or pull-down the resistors at the output terminal of the LDO regulator based on the rising and falling edges of the received clock signals.

Abstract: An optical underwater communication system is disclosed which includes a first transceiver and a second transceiver, each including one or more optical sources configured to provide light activated and deactivated according to a first bit stream, one or more sensor packages each comprising a plurality of photodetectors configured to receive light from the other transceiver and, in response, provide an output voltage signal and an output current signal, a detector configured to i) convert the output voltage signal and the output current signal to pulses associated with arrival of photons, and ii) count the number of pulses based on a predetermined timing sequence, an encoder configured to encode a message to be sent into a first bit stream, and a decoder configured to decode a message received into a second bit stream.

Abstract: A frequency synthesizer employs a combination of a low divide ratio divider phase-locked loop (PLL) and a wide band, on-chip voltage-controlled oscillator (VCO). To reduce phase noise, low divide ratio phase detection is employed. By using the off-chip PLL with a bank of on-chip VCOs, the frequency synthesizer may have enhanced frequency stability and avoid having to include an acquisition circuit. A separation between the PLL and VCO may reduce integer boundary spurs (IBS) eliminating or reducing a need for a filter bank and switches reducing a complexity of the frequency synthesizer.

Abstract: In described examples, a phase locked loop (PLL) includes a compensation circuit, a transconductance circuit, and an oscillator. The compensation circuit includes a capacitor circuit and a resistive element having a resistance responsive to a center frequency of the PLL's bandwidth. The transconductance circuit includes a current source and an error amplifier. The current source generates a current responsive to the center frequency. The error amplifier has a transconductance responsive to the center frequency, and receives a signal responsive to the resistance and a difference between an input clock signal and a feedback signal. The oscillator input is coupled to the error amplifier output. The oscillator provides a signal at its output for generating the feedback signal.

Abstract: Disclosed is a card clock recovery system for use in an NFC card transceiver couplable to an NFC reader.

Abstract: Time stamp replication within wireless networks is described. In an embodiment, a wireless station receives an input time stamp and uses this input time stamp to generate an output time stamp. The wireless station transmits the output time stamp to wireless stations in one of a number of groups which make up the wireless network. The output time stamp is generated to compensate for delays between receiving the input time stamp and transmitting the output time stamp such that output time stamp which is transmitted at a time T corresponds to the value that the input time stamp would have had if it had been received at time T (and not at a time earlier than T). This may, therefore, reduce or eliminate independent time stamp errors and jitter caused by multiple disparate systems and processes.

Abstract: Provided is a clock signal generation circuit. The clock signal generation circuit includes a control word generation circuit, an initial clock generation circuit and a spread spectrum clock generation circuit, wherein the control word generation circuit is connected to the initial clock generation circuit and the spread spectrum clock generation circuit; the initial clock generation circuit is further connected to the spread spectrum clock generation circuit.

Abstract: The present disclosure provides a switching current source circuit and a method for quickly establishing a switching current source. The switching current source circuit includes a first and a second switching current source branches connected in parallel with one end of a load. When the switching enable signal is switched, due to the charge coupling of the first and second switching current source branches, the bias voltage respectively generates bounce in the same direction as and a direction opposite to the transition direction of the switching enable signal. The two bounces cancel each other to make the current source bias voltage recover quickly when a toggle event happens. The present disclosure accelerates the establishment of current through the coupling of charges, and reduces the decoupling capacitance at the same time, thereby reducing the circuit area and saving the costs.

Abstract: A storage device is provided. The storage device includes nonvolatile memory devices provided on a printed circuit board (PCB), a connector, a storage controller and at least one first passive filter. The connector is provided in the PCB and includes connection terminals. The storage controller is provided on the PCB, communicates with an external host through the connection terminals and controls the nonvolatile memory devices. The at least one first passive filter is provided in the PCB, is connected between the connector and the storage controller, and performs an equalization on either a signal provided to the storage controller or a signal provided from the storage controller.

Abstract: A clock generator can include a Fin Field Effect Transistor (FinFET) oscillator and a phased-locked loop (PLL). The FinFET oscillator can generate a FinFET signal. The PLL can generate an output clock signal based on a reference clock signal and the FinFET signal.

Abstract: Systems and methods are disclosed herein for syntonizing machines in a network. A coordinator accesses probe records for probes transmitted at different times between pairs of machines in the mesh network. For different pairs of machines, the coordinator estimates the drift between the pair of machines based on the transit times of probes transmitted between the pair of machines as indicated by the probe records. For different loops of at least three machines in the mesh network, the coordinator calculates a loop drift error based on a sum of the estimated drifts between pairs of machines around the loop and adjusts the estimated absolute drifts of the machines based on the loop drift errors. Here, the absolute drift is defined relative to a drift of a reference machine.

Abstract: A method and apparatus in which a data stream generated by a previous network node, a cumulative phase offset report (CPOR) and a client rate report (CRR) are received. A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between a PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD), where IPSD indicates CPSC increment between successive CPSC samples. The data stream is demultiplexed to obtain CBR carrier streams that include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and the PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.

Abstract: A memory controller conveys a clock signal with command and address signals to a registered clock driver (RCD) on a memory module. A controller-side chip interface on the RCD supports both source-synchronous and filtered clocking for receipt of the command and address signals, the selection between the two clocking schemes dependent upon the noise environment impacting the clock and command/address signals. If the noise is predominantly correlated, then the chip interface is placed in a source-synchronous clocking mode. If the noise is predominantly uncorrelated, then the chip interface is placed in a filtered clocking mode that filters out uncorrelated noise from the clock signal.

Abstract: A phase locked loop (PLL) method includes generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; generating an output clock based on the first signal; generating an intermediate feedback clock including frequency dividing the output clock; fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock. In one implementation, a PLL includes a frequency multiplier to generate the sampling clock based on the feedback clock. In another implementation, a PLL uses the intermediate feedback clock as the sampling clock.

Abstract: A method and an electronic device of correcting frame for an optical camera communication (OCC) are provided. The method includes the following steps. The optical signal is captured. The optical signal is input to a first machine learning (ML) model to obtain a missing timestamp. The optical signal and the missing timestamp are input to a second ML model to obtain a first complement frame corresponding to the missing timestamp. The first complement frame is outputted.

Abstract: A Controller Area Network, CAN, bit stream sampling apparatus for a CAN controller, the apparatus configured to receive a bit stream from a CAN transceiver, the apparatus configured to: detect rising edges in said bit stream; detect, separately, falling edges in said bit stream; and generate a restored non-return-to-zero coded bit stream based at least on said detected falling edges and said detected rising edges.

Abstract: A device includes feed-forward clock circuitry to provide a receiver (RX) clock to a sampler circuit that samples a data lane of a set of RX data lanes, the feed-forward clock circuitry having a temperature-induced delay. The device also includes an RX phase-locked loop (PLL) coupled between the feed-forward clock circuitry and the sampler circuit. The RX PLL includes a phase interpolator positioned in a feedback path of the RX PLL. The phase interpolator has a negative delay that matches the temperature-induced delay of the feed-forward clock circuitry to cause the sampler circuit to cancel out the common noise shared between the feed-forward clock circuitry and the data lane.

Abstract: A method and apparatus for determining jitter, a storage medium and an electronic device are disclosed. The method for determining jitter includes: determining a plurality of measurement time points for an output signal from an integrated circuit (IC); identifying one or more jitter points from the plurality of measurement time points by comparing the output signal with a predetermined signal at the plurality of measurement time points; and determining a jitter of the output signal of the IC based on the one or more jitter points. The jitter of the output signal of an IC chip can be determined without relying on any other additional equipment.

Abstract: A failure detection system for an energy network includes a radio frequency (RF) receiver adapted to be coupled with or in close proximity to the energy network, the RF receiver providing an amplitude modulated RF signal; an RF amplifier receiving the amplitude modulated RF signal and providing an amplified signal; an envelope detector receiving the amplitude modulated RF signal and providing a demodulated envelope signal; an optional algorithm implementation system receiving the demodulated envelope signal, where the optional algorithm implementation system processes the demodulated envelope signal by one or more of a Fast Fourier transform (FFT) trigger system and a phase-locked loop (PLL) trigger system; and a signature output that is the overall output signal of the failure detection system, wherein the signature output is adapted to indicate whether the energy network is experiencing partial discharge.

Abstract: A phase-locked loop (PLL) circuit generates an analog signal in phase-lock with a reference signal at a reference frequency. The PLL circuit includes a charge pump circuit, a loop filter circuit, a feedback divider, and a voltage controlled oscillator (VCO). The charge pump circuit charges a sample capacitor of the loop filter circuit to a sample voltage based on a phase difference between the generated analog signal and the reference signal. The loop filter circuit stores the sample voltage as a proportional control voltage in a hold capacitor to reduce or avoid ripple in the control voltage that causes jitter in the analog signal. The loop filter circuit also provides the sample voltage to an integral component circuit comprising a comparator and digital accumulator producing an integral control. The VCO generates the analog signal at a frequency based on the proportional control voltage and the integral control voltage.

Abstract: Systems, methods, and circuits provide delay-locked loop (DLL) timing error mitigation. A DLL false-lock detection system can include DLL circuitry configured to receive a reference clock signal having a time period. The system can include shift register circuitry and latched comparison circuitry which can determine a time period of a locked condition of the DLL delay line with respect to the reference clock signal time period. The system can determine whether the system is correctly locked to the base time period or incorrectly locked to a multiple of the base time period. A further system can operate to cause a phase detector circuitry in a DLL to ignore the first edge of a reference clock signal presented to the phase detector circuitry and thereby avoid stuck-lock conditions.

Abstract: A signal is transmitted at a high speed in a direction opposite to a transmitting direction of a main large-capacity channel. A first transmitting unit transmits a first signal including a clock component to an external device through a transmission path as a differential signal. A second transmitting unit superimposes a second signal including a clock component on the transmission path as an in-phase signal to transmit to the external device. A state notifying unit communicates with the external device through a pair of differential transmission paths included in the transmission path and notifies the external device of a connection state of its own device by a DC bias potential of at least one of the pair of differential transmission paths.

Abstract: A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.

Abstract: Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

Abstract: A clock recovery circuit a first phase-locked loop (PLL) circuit configured to perform a coarse phase fixing operation on a test data signal by using a first reference clock signal, the test data signal having a prescribed pattern, and a second PLL circuit configured to perform a fine phase fixing operation on the test data signal, subsequently to the coarse phase fixing operation. The second PLL circuit may be configured to perform the fine phase fixing operation on the test data signal by selectively using at least two selection reference clock signals among a plurality of second reference clock signals that are delayed from the first reference clock signal by a unit phase, in a training mode, having a phase difference of N times the unit phase, where N is an integer equal to or greater than 2.

Abstract: A clock and data recovery circuit includes a phase detector that outputs phase characteristic data based on a digital data signal and an adjustment circuit that adjusts phase characteristic data. The clock and data recovery circuit sets an adjustment value in an adjustment circuit by calculating an adjustment value of phase characteristic data using a monitor circuit while changing a phase of a reference clock signal to be adjusted in a phase interpolation circuit based on offset data output from an offset output circuit in a training period before communication starts.

Abstract: Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.