Image processing device

A device for processing image data for inputted image data composed of blocks, each of which has 64 pixels values arranged in a matrix. Each of the pixel values is inputted to one of first through fourth stages forming a pre-processing unit. Each of the stages has 16 addition and subtraction units. Four pixels positioned at predetermined locations in the matrix are inputted to a predetermined addition and subtraction unit, so that the four pixels are subjected to addition and subtraction, and a part of a two-dimensional DCT. Thus, 64 pre-processed DCT coefficients are obtained. The pre-processed DCT coefficients are inputted to the post-processing unit, in which the remaining part of the two-dimensional DCT and the quantization are performed, so that the quantization DCT coefficients are obtained.

Skip to:  ·  Claims  ·  References Cited  · Patent History  ·  Patent History

Claims

1. An image processing device, in which inputted original image data, composed of pixel values, are arranged in a matrix, said pixel values being subjected to a two dimensional discrete cosine transformation (DCT) to obtain a DCT coefficient for each of spatial frequencies, and said DCT coefficient being quantized by a quantization coefficient included in a quantization table to obtain a quantized DCT coefficient, said device comprising:

pre-process unit for obtaining pre-processed DCT coefficients corresponding to said pixel values, said pre-process unit being divided into a plurality of stages in accordance with cosine coefficients of said two dimensional DCT, said pre-processed DCT coefficients being obtained by applying a calculation, which corresponds to said cosine coefficients, to said pixel values in each of said stages;
classifying unit for classifying said pixel values into groups composed of a predetermined number of pixel values, said groups are disposed in said matrix arrangement symmetrically about an axis, and said groups are multiplied by cosine coefficients having the same absolute value;
pixel value input unit for inputting said pixel values of each of said groups into said plurality of stages, respectively; and
post-process unit for performing a post-process in which each of said pre-processed DCT coefficients a multiplied by a corresponding post-process coefficient to obtain said quantized DCT coefficient, said post-process coefficient being generated based on combination of said quantization coefficient and one of a plurality of multiplying terms corresponding to said cosine coefficients.

2. A device according to claim 1, wherein said DCT coefficient is ##EQU2## wherein said inputted original image data includes pixel values Pyx of an 8.times.8 pixel block, wherein the suffix "y" represents the vertical position within the 8.times.8 pixel block, and the suffix "x" represents the horizontal position within the 8.times.8 pixel block, a vertical position within an 8.times.8 matrix in which 64 DCT coefficients are arranged is indicated by a parameter "v" and a horizontal position within said 8.times.8 matrix is indicated by a parameter "u", and further wherein Cu and Cv=1/2 when u and v=0, and Cu and Cv=1 when u and v.noteq.0;

said pre-process unit comprising a first stage in which each of the parameters "u" and "v" is 0, 4, 2, or 6, a second stage in which said parameter "u" is 0, 4, 2, or 6 and said parameter "v" is 1, 3, 5, or 7, a third stage in which said parameter "u" is 1, 3, 5, or 7 and said parameter "v" is 0, 4, 2, or 6, and a fourth stage in which each of said parameters "u" and "v" is 1, 3, 5, or 7.

3. A device according to claim 2, wherein said first stage comprises a first area in which each of said parameters "u" and "v" is 0 or 4, a second area in which said parameter "u" is 2 or 6 and said parameter "v" is 0 or 4, or said parameter "u" is 0 or 4 and said parameter "v" is 2 or 6, and a third area in which each of said parameters "u" and "v" is 2 or 6.

4. A device according to claim 3, wherein said first area performs a first process corresponding to a multiplication in which each of said pixel values Pyx is multiplied by cos(4.PI./16).box-solid.cos(4.PI./16).

5. A device according to claim 3, wherein said second area performs a second process corresponding to a multiplication in which each of said pixel values Pyx is multiplied by cos(4.PI./16).box-solid.cos(2.PI./16) or cos(4.PI./16).box-solid.cos(6.PI./16).

6. A device according to claim 3, wherein said third area performs a third process corresponding to a multiplication in which each of said pixel values Pyx is multiplied by cos(2.PI./16).box-solid.cos(2.PI./16), cos(2.PI./16).box-solid.cos(6.PI./16), or cos(6.PI./16).box-solid.cos(6.PI./16).

7. A device according to claim 2, wherein said second stage comprises a fourth area in which said parameter "u" is 0 or 4 and said parameter "v" is 1, 3, 5, or 7, a fifth area in which said parameter "u" is 2 or 6 and said parameter "v" is 1, 3, 5, or 7.

8. A device according to claim 2, wherein said third stage comprises a fourth area in which said parameter "u" is 1, 3, 5, or 7 and said parameter "v" is 0 or 4, a fifth area in which said parameter "u" is 1, 3, 5, or 7 and said parameter "v" is 2 or 6.

9. A device according to claim 7, wherein said fourth area performs a fourth process corresponding to a multiplication in which each of said pixel values Pyx is multiplied by cos(4.PI./16).box-solid.cos(.PI./16), cos(4.PI./16).box-solid.cos(3.PI./16), cos(4.PI./16).box-solid.cos(5.PI./16), or cos(4.PI./16).box-solid.cos(7.PI./16).

10. A device according to claim 7, wherein said fifth area performs a fifth process corresponding to a multiplication in which each of said pixel values Pyx is multiplied by cos(2.PI./16).box-solid.cos(.PI./16), cos(2.PI./16).box-solid.cos(3.PI./16), cos(2.PI./16).box-solid.cos(5.PI./16), cos(2.PI./16).box-solid.cos(7.PI./16), cos(6.PI./16).box-solid.cos(.PI./16), cos(6.PI./16).box-solid.cos(3.PI./16), cos(6.PI./16).box-solid.cos(51r/16), or cos(6.PI./16).box-solid.cos(7.PI./16).

11. A device according to claim 2, wherein said fourth stage comprises a sixth area in which each of said parameters "u" and "v" is 1, 3, 5, or 7.

12. A device according to claim 11, wherein said sixth area performs a sixth process corresponding to a multiplication in which each of said pixel values Pyx is multiplied by cos(.PI./16).box-solid.cos(.PI./16), cos(.PI./16).box-solid.cos(3.PI./16), cos(.PI./16).box-solid.cos(5.PI./16), cos(.PI./16).box-solid.cos(7.PI./16), cos(3.PI./16).box-solid.cos(3.PI./16), cos(3.PI./16).box-solid.cos(5.PI./16), cos(3.PI./16).box-solid. cos(7.PI./16), cos(5.PI./16).box-solid. cos(5.PI./16), cos(5.PI./16).box-solid. cos(7.PI./16), or cos(7.PI./16).box-solid. cos(7.PI./16).

13. A device according to claim 1, wherein a number of said pixel values included in each of said groups is four.

14. A device according to claim 13, said inputted original image data is pixel values Pyx of an 8.times.8 pixel block, wherein the suffix "y" represents the vertical position of the 8.times.8 pixel block, and suffix "x" represents the horizontal position of the 8.times.8 pixel block, and said classifying unit classifies said pixel values into a first pixel group composed of P.sub.00, P.sub.07, P.sub.70, P.sub.77, a second pixel group composed of P.sub.01, P.sub.06, P.sub.71, P.sub.76, a third pixel group composed of P.sub.02, P.sub.05, P.sub.72, P.sub.75, a fourth pixel group composed of P.sub.03, P.sub.04, P.sub.73, P.sub.74, a fifth pixel group composed of P.sub.10, P.sub.17, P.sub.60, P.sub.67, a sixth pixel group composed of P.sub.11, P.sub.16, P.sub.61, P.sub.66, a seventh pixel group composed of P.sub.12, P.sub.15, P.sub.62, P.sub.65, an eighth pixel group composed of P.sub.13, P.sub.14, P.sub.63, P.sub.64, a ninth pixel group composed of P.sub.20, P.sub.27, P.sub.50, P.sub.57, a tenth pixel group composed of P.sub.21, P.sub.26, P.sub.51, P.sub.56, an eleventh pixel group composed of P.sub.22, P.sub.25, P.sub.52, P.sub.55, a twelfth pixel group composed of P.sub.23, P.sub.24, P.sub.53, P.sub.54, a thirteenth pixel group composed P.sub.30, P.sub.37, P.sub.40, P.sub.47, a fourteenth pixel group composed of P.sub.31, P.sub.36, P.sub.41, P.sub.46, a fifteenth pixel group composed of P.sub.32, P.sub.35,P.sub.42, P.sub.45, and a sixteenth pixel group composed of P.sub.33, P.sub.34, P.sub.43, P.sub.44.

15. A device according to claim 1, wherein said post-process coefficient is obtained by multiplying said one of said plurality of multiplying terms and an inverse value of said quantization coefficient.

16. An image processing device applying a two-dimensional discrete cosine transformation (DCT) to original image data to obtain DCT coefficients, and then applying a quantization coefficient to each of said DCT coefficients to obtain quantized DCT coefficients, said device comprising:

unit for generating pixel groups in accordance with pixel values which form said original image data and are arranged in a matrix, each of said pixel groups being composed of a predetermined number of said pixel values which are symmetrically disposed in said matrix arrangement;
unit for applying a pre-process to said pixel values to obtain pre-processed DCT coefficients corresponding to said pixel values, said pre-process unit being divided into a plurality of stages in accordance with cosine coefficients used in said two dimensional DCT, said pre-processed DCT coefficients being obtained by applying a calculation corresponding to said cosine coefficients to said pixel values in each of said stages;
unit for inputting said pixel values of each of said groups into said plurality of stages, respectively; and
unit for applying a post-process in which each of said pre-processed DCT coefficients is multiplied by a corresponding post-process coefficient to obtain said quantized DCT coefficient, said post-process coefficient being generated based on combination of said quantization coefficient and one of a plurality of multiplying terms corresponding to said cosine coefficients.

17. A device according to claim 8, wherein said fourth area performs a fourth process corresponding to a multiplication in which each of said pixel values Pyx is multiplied by cos(4.PI./16).box-solid. cos(.PI./16), cos(4.PI./16).box-solid. cos(3.PI./16), cos(4.PI./16).box-solid. cos(5.PI./16), or cos(4.PI./16).box-solid. cos(7.PI./16).

18. A device according to claim 8, wherein said fifth area performs a fifth process corresponding to a multiplication in which each of said pixel values Pyx is multiplied by cos(2.PI./16).box-solid. cos(.PI./16), cos(2.PI./16).box-solid. cos(3.PI./16), cos(2.PI./16).box-solid. cos(5.PI./16), cos(2.PI./16).box-solid. cos(7.PI./16), cos(6.PI./16).box-solid. cos(.PI./16), cos(6.PI./16).box-solid. cos(3.PI./16), cos(6.PI./16).box-solid. cos(5.PI./16), or cos(6.PI./16).box-solid. cos(7.PI./16).

Referenced Cited
U.S. Patent Documents
5166987 November 24, 1992 Kageyama
5299025 March 29, 1994 Shirasawa
5311307 May 10, 1994 Yoshimoto
5333212 July 26, 1994 Ligtenberg
5657399 August 12, 1997 Iwabuchi et al.
5719958 February 17, 1998 Wober et al.
Other references
  • "Digital Signal Processing Handbook" 1st ed., Ohm Press, Tokyo, Japan on Jan. 31, 1993, pp. 70-82, and an English Translation thereof.
Patent History
Patent number: 5886790
Type: Grant
Filed: Jul 11, 1996
Date of Patent: Mar 23, 1999
Assignee: Asahi Kogaku Kogyo Kabushiki Kaisha (Tokyo)
Inventor: Nobuaki Abe (Hokkaido)
Primary Examiner: Kim Yen Vu
Assistant Examiner: Mark Wallerson
Law Firm: Greenblum & Bernstein, P.L.C.
Application Number: 8/678,707
Classifications
Current U.S. Class: 358/2612; 358/2613; 358/426; 358/427; 358/432; 358/433; Transform Coding (382/248)
International Classification: H04N 1417; H04N 1415; H04N 141;