Image data-outputting unit and liquid crystal display device
An LCD drive of an image data-outputting unit causes an LCD to display thereon the same image twice and perform overdrive for a frame period in a first mode, causes the LCD to display thereon an image to be displayed in the first half of the frame period and display thereon a black image in the second half of the frame period in a second mode, and causes the LCD to display thereon the same image twice for the frame period without performing the overdrive in a third mode.
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The present application is based on Japanese patent application No. 2006-181038, the entire contents of which are incorporated herein by reference.
BACKGROUND1. Field
One embodiment of the invention relates to an image data-outputting unit and a liquid crystal display device.
2. Description of the Related Art
Since a liquid crystal panel is of “a hold type” in which an image continues to be displayed at the same level for a one frame period (16 msec), a moving image blur occurs due to a response delay of liquid crystal in the liquid crystal panel of the hold type. On the other hand, since a CRT display, a surface-conduction electron-emitter display (SED) or the like is of “an impulse type” in which the light emission is made only for a moment of one frame period, no moving image blur occurs.
In recent years, the various kinds of methods have been proposed for the purpose of improving the moving image blur occurring in the liquid crystal panel. The techniques relating to these methods, for example, are disclosed in the Japanese Patent Kokai Nos. 2002-116743 and 2002-215111.
A liquid crystal display device disclosed in the Japanese Patent Kokai No. 2002-116743 is such that an image signal is written to a frame memory once for one vertical synchronous time period, an image signal is repeatedly read out from the frame memory twice for one vertical synchronous time period, and a voltage value corresponding the image signal thus read out is applied to each of corresponding display pixels of a liquid crystal panel. As a result, step responsibility of the display pixels is further improved in this case than in the case where the voltage value corresponding to the image signal is repeatedly applied three times at a rate of one time for one vertical synchronous period.
A liquid crystal display device disclosed in the Japanese Patent Kokai No. 2002-215111 includes a frame memory for storing therein an input image signal for one frame, a frame frequency-converting portion for converting a period of an image signal into half a frame period, and outputting the resulting image signal, and a signal switching portion for switching the image signal obtained through conversion of the frame period and a black display signal over to each other. Thus, an image to be displayed is displayed in the first half of the frame period, and a black signal is displayed in the second half of the frame period. As a result, it becomes possible to realize the display of a pseudo impulse type, and thus it is possible to improve degradation of an image quality due to the moving image blur.
However, according to the liquid crystal display device disclosed in the Japanese Patent Kokai No. 2002-116743, although the responsibility of the liquid crystal is improved, the moving image blur cannot be sufficiently improved. In addition, according to the liquid crystal display device disclosed in the Japanese Patent Kokai No. 2002-215111, although the moving image blur can be improved, the overall screen becomes dark because of reduction of a luminance. The displayed image is degraded depending on the kinds of images all the more because there are various displayed images such as the image having a low luminance and the image having a small motion.
A general architecture that implements the various features of the invention will now be described with reference to the drawings. The drawings and the associated descriptions are provided to illustrate embodiments of the invention and not to limit the scope of the invention.
Various embodiments according to the invention will be described hereinafter with reference to the accompanying drawings. In general, according to one embodiment of the invention, there is provided an image data-outputting unit, including: a storage portion for storing therein image data supplied in a predetermined period; and an image data-outputting portion for outputting the image data (n−k) times (n and k: integral numbers (n>k≧0)) from the storage portion with an output period which is 1/n of the predetermined period.
In addition, according to a further embodiment of the invention, there is provided an image data-outputting circuit, including: a storage portion for storing therein image data supplied in a predetermined period; an image data-outputting portion for performing a first mode in which the image data is outputted n times from the storage portion in an output period which is 1/n of the predetermined period, or a second mode in which the image data is outputted (n−k) times (n and k: integral numbers (n>k≧0)) from the storage portion in an output period which is 1/n of the predetermined period; an overdrive circuit for, when the first mode is performed, increasing or decreasing a data value of the current image data in accordance with the last image data for a precedent predetermined period and the current image data outputted from the image data-outputting portion, and outputting image data of the increased or decreased data value; and a selecting portion for selecting one of the first and second modes to provide a first or second mode signal to the image data-outputting portion and the over drive circuit.
In addition, according to a still further embodiment of the invention, there is provided a liquid crystal display device, including: a storage portion for storing therein image data supplied in a predetermined period; an image data-outputting portion for performing a first mode in which the image data is outputted n times from the storage portion in an output period which is 1/n of the predetermined period, or a second mode in which the image data is outputted (n−k) times (n and k: integral numbers (n>k≧0)) from the storage portion in the period which is 1/n times as large as the predetermined period; an overdrive circuit for, when the first mode is performed, increasing or decreasing a data value of the current image data in accordance with the last image data for a precedent predetermined period and the current image data outputted from the image data-outputting portion, and outputting image data of the increased or decreased data value; a selecting portion for selecting one of the first and second modes to provide a first or second mode signal to the image data-outputting portion and the overdrive circuit; and a liquid crystal panel for displaying thereon an image corresponding to the image data outputted from the image data-outputting portion or the overdrive circuit in accordance with the first or second mode.
According to the invention, the image quality can be enhanced in correspondence to a kind of image such as a moving image or a still image with the simple configuration.
First EmbodimentThe liquid crystal display device 1 includes a write circuit 2A for writing image data to a frame memory 3 which will be described below for one frame period, a read circuit 2B for reading out the same image data twice from the frame memory 3 for one frame period, the frame memory 3 for storing therein image data, a MUTE circuit (mute means) 4 for outputting one of the two pieces of the same image data in one frame outputted from the read circuit 2B, and inhibits the other piece of the same image data from being outputted, a MUTE driving circuit 5 for driving the MUTE circuit 4, an overdrive circuit 6 for outputting data for which overdrive processing is executed, a delay data memory 7 for storing therein delay data for the overdrive circuit 6, a liquid crystal display (LCD) panel 8 for displaying an image by using an LCD, and a mode selecting portion 9 for selecting a mode among a predetermined number of modes.
Here, the write circuit 2A, the read circuit 2B, the frame memory 3, the MUTE circuit 4, the MUTE driving circuit 5, the overdrive circuit 6, the delay data memory 7 and the mode selecting portion 9 constitute an image data-outputting unit. In addition, the write circuit 2A, the read circuit 2B, the MUTE circuit 4, and the MUTE driving circuit 5 constitute an image data-outputting portion 10.
The write circuit 2A writes a digital image signal (image data) for individual pixels which is successively supplied from a video apparatus or the like with a frame period (e.g., corresponding to 50 Hz) to the frame memory 3, receives as its inputs a vertical synchronous signal V and a horizontal synchronous signal H, and generates a vertical synchronous signal 2V and a horizontal synchronous signal 2H which are two times in frequency as high as the vertical synchronous signal V and the horizontal synchronous signal H, respectively. The read circuit 2B is structured such that it reads out the image data once every output of the vertical synchronous signal 2V from the frame memory 3, that is, reads out the same image data twice in a period (e.g., corresponding to 100 Hz) which is half the frame period.
The MUTE driving circuit 5 drives the MUTE circuit 4 in accordance with the vertical synchronous signal 2V received as its input from the read circuit 2B.
The overdrive circuit 6 executes overdrive processing so that it compares the current image data and the last image data with each other, outputs a data value larger than that of the current image data with respect to the pixels in each of which the data value of the current image data is larger than that of the last image data, outputs a data value smaller than that of the current image data with respect to the pixels in each of which the data value of the current image data is smaller than that of the last image data, and outputs a data value of the current image data with respect to the pixels in each of which the data value of the current image data is equal to that of the last image data. Here, when the mode selecting portion 9 which will be described later selects a third mode in which the same image is displayed twice for one frame period, and no overdrive processing is executed, the current image data is outputted as it is.
The LCD panel 8 includes a liquid crystal display (LCD) 81, and an LCD driver 80 for driving the LCD 81. Note that, both the overdrive circuit 6 and the delay data memory 7 may be incorporated in the LCD panel 8.
LCD 81 is constructed such that a liquid crystal such as a nematic liquid signal is disposed between a full-face electrode and a plurality of pixel electrodes, the resulting construction is sandwiched between a pair of deflection plates, a plurality of active elements such as TFTs are connected to intersections between a plurality of data lines and a plurality of scanning lines which intersect perpendicularly each other, respectively, and the active elements drive the pixels in an active matrix manner, respectively. In addition, the LCD 81 includes a back light, constituted by a cold cathode tube or an LED for radiating a light thereto from its back face side.
The LCD driver 80 drives the LCD 81 such that it selects successively a plurality of scanning lines, and applies a voltage corresponding to the image data to each of a plurality of data lines in accordance with the image data outputted from the overdrive circuit 6 to change a light transmittance of the liquid crystal to suitable one.
The mode selecting portion 9 selects any one among a first mode in which the same image is displayed twice for one frame period and the overdrive processing is executed, a second mode in which the image is displayed in the first half of one frame period and no image is displayed in the second half of one frame period (the black image is inserted), and a third mode in which the same image is displayed twice for one frame period and no overdrive processing is executed in accordance with a manipulation made by a user.
The delay circuit 60, as shown in
[Operation of Liquid Crystal Display Device]
Next, an operation of the liquid crystal display device 1 will now be described with reference to
(1) First Mode: A description will now be described with respect to the case where the user selects the first mode by the manipulating the mode selecting portion 9. The write circuit 2A writes the image signal D which is successively supplied from the video apparatus or the like with the frame period (e.g., corresponding to 50 Hz) to the frame memory 3, and the read circuit 2B reads out the image signal D from the frame memory 3 with the frame period (e.g., corresponding to 100 Hz) which is half the frame period (e.g., corresponding to 50 Hz) and outputs the image signal D thus read out to the MUTE circuit 4. In addition, the read circuit 2B generates the vertical synchronous signal 2V and the horizontal synchronous signal 2H which are 2 times in frequency as high as the vertical synchronous signal V and the horizontal synchronous signal H, respectively, which are inputted from the video apparatus or the like to the liquid crystal display device 1, and outputs the resulting vertical synchronous signal 2V and horizontal synchronous signal 2H to the LCD driver 80.
The MUTE circuit 4 outputs the image data D outputted from the read circuit 2B to the overdrive circuit 6 as it is by driving the MUTE driving circuit 5 in accordance with the mode selection made by the mode selecting portion 9.
The overdrive circuit 6 compares the current image data and the last image data with each other, and outputs the data value higher than that of the current image data to the LCD driver 80 with respect to the pixels in each of which the data value of the current image data is higher than that of the last image data.
As shown in
The overdrive voltage Vod2 is determined in accordance with the signal a shown in
(2) Second Mode: A description will now be described with respect to the case where the user selects the second mode by the manipulating the mode selecting portion 9. The write circuit 2A writes the image signal D which is successively supplied from the video apparatus or the like with the frame period (e.g., corresponding to 50 Hz) to the frame memory 3, and the read circuit 2B reads out the image signal D from the frame memory 3 with the frame period (e.g., corresponding to 100 Hz) which is half the frame period (e.g., corresponding to 50 Hz) and outputs the image signal D thus read out to the MUTE circuit 4. In addition, the read circuit 2B generates the vertical synchronous signal 2V and the horizontal synchronous signal 2H which are 2 times in frequency as high as the vertical synchronous signal V and the horizontal synchronous signal H, respectively, which are inputted from the video apparatus or the like to the liquid crystal display device 1, and outputs the resulting vertical synchronous signal 2V and horizontal synchronous signal 2H to the LCD driver 80.
The MUTE circuit 4 outputs the image data D outputted from the read circuit 2B to the overdrive circuit 6 in the first half of the frame period by driving the MUTE driving circuit 5 in accordance with the mode selection made by the mode selecting portion 9, and inhibits the image data from being outputted to the overdrive circuit 6 in the second half of the frame period.
The overdrive circuit 6 outputs the image data outputted from the MUTE circuit 4 to the LCD panel 8 without executing the overdrive processing for the image data outputted from the MUTE circuit 4.
As shown in
Note that, the LCD driver 80 may turn ON the back light in the first half of the frame period T in which the image to be displayed is displayed, and may turn OFF the back light in the second half of the frame period T in which the black image is displayed. As a result, the moving image blur can be further improved.
(3) Third Mode: A description will now be described with respect to the case where the user selects the third mode by the manipulating the mode selecting portion 9. The write circuit 2A writes the image signal D which is successively supplied from the video apparatus or the like with the frame period (e.g., corresponding to 50 Hz) to the frame memory 3, and the read circuit 2B reads out the image signal D from the frame memory 3 with the frame period (e.g., corresponding to 100 Hz) which is half the frame period (e.g., corresponding to 50 Hz) and outputs the image signal D thus read out to the MUTE circuit 4. In addition, the read circuit 2B generates the vertical synchronous signal 2V and the horizontal synchronous signal 2H which are 2 times in frequency as high as the vertical synchronous signal V and the horizontal synchronous signal H, respectively, which are inputted from the video apparatus or the like to the liquid crystal display device 1, and outputs the resulting vertical synchronous signal 2V and horizontal synchronous signal 2H to the LCD driver 80.
The MUTE circuit 4 outputs the image data D outputted from the read circuit 2B to the overdrive circuit 6 as it is by driving the MUTE driving circuit 5 in accordance with the mode selection made by the mode selecting portion 9.
The overdrive circuit 6 outputs the image data outputted from the read circuit 2B to the liquid crystal panel 8 as it is without executing the overdrive processing for the image data outputted from the read circuit 2B.
As shown in
According to the above-mentioned first embodiment of the invention, the first mode is selected and the bright image is displayed in the case of the still image or the image having a small motion, and the second mode is selected in the case of the image, having a violent motion, obtained from a sports program or the like. As a result, it is possible to display the image having the improved moving image blur. In addition, the mode corresponding to the kind of image can be selected and carried out with the simple configuration in which one frame memory is merely used.
In addition, the data on the delay time td and the data on the overdrive voltage Vod2 which are stored in the delay data memory 7 in advance can be adjusted and rewritten in accordance with the dispersion in property of the LCD panel 8. In particular, the delay time td is easy to control. As a result, the yield of the liquid crystal display device 1 is enhanced.
Second EmbodimentIn the liquid crystal display device according to the above-mentioned first embodiment of the invention, the description has been given with respect to the case where the same image data is read out twice from the frame memory 3 for one frame period. On the other hand, a liquid crystal display device according to a second embodiment of the invention is such that the read circuit 2B reads out the same image data three times from the frame memory 3 for one frame period and the MUTE circuit 4 outputs the first image data of the three pieces of the same image data which are obtained by reading the same image data three times for one frame period.
According to the second embodiment of the invention, since the image is displayed for a time period which is one-third one frame period in the second mode, the display form can be made closer to that in “the impulse type” in the second embodiment than in the first embodiment, and thus the moving image blur can be further improved.
It should be noted that the invention is not intended to be limited to the first and second embodiments, and thus the various changes and modifications thereof can be implemented. Although in each of the first and second embodiments, one frame period has been described as the predetermined period, the predetermined period is not limited to one frame period. For example, when one field period has three fields corresponding to R, G and B, respectively, a time period corresponding to one field may be set as the predetermined period.
In addition, in the first embodiment described above, the MUTE circuit 4 is structured so as to inhibit the image data from being outputted in the second half of one frame period in the second mode. Alternatively, the MUTE circuit 4 may be structured so as to output the image data in the second half of one frame period and inhibit the image data from being outputted in the first half of one frame period.
Moreover, in the first and second embodiments, the descriptions have been given with respect to the cases where the same image data is read out twice and three times from the frame-memory for the predetermined period, respectively. However, the number of times of reading out the same image data is not limited thereto, and thus may also be four or more.
In addition, in the first and second embodiments, the descriptions have been given with respect to the cases where the MUTE circuit 4 outputs only the first image data of the two pieces and three pieces of the same image data which are obtained by reading out the same image data twice and three times from the read circuit 2B, respectively. Alternatively, the image data may also be outputted over the number of times of output (twice or more) smaller than the number, n, of times of read. For example, when the same image data is read out four times from the read circuit 2B for one frame period, the MUTE circuit 4 may output the first and third image data of the four pieces of the same image data.
It should be noted that the present invention is not limited to the embodiments described above, and the various combinations and changes may be made without departing from or changing the technical idea of the present invention.
Claims
1. An image data-outputting unit, comprising:
- a storage portion for storing therein image data supplied in a predetermined period; and
- an image data-outputting portion for outputting the image data (n−k) times (n and k; integral numbers (n>k≧0)) from the storage portion with an output period which is 1/n of the predetermined period;
- wherein the image data-outputting portion comprises:
- a reading portion for reading out the image data n times from the storage portion with an output period which is 1/n of the predetermined period; and
- a mute circuit for outputting the image data, which is read out n times, (n−k) times for the predetermined period.
2. An image data-outputting unit according to claim 1, wherein the mute circuit outputs the image data (n−k) times in a form of the same output pattern every predetermined period.
3. An image data-outputting circuit, comprising:
- a storage portion for storing therein image data supplied in a predetermined period;
- an image data-outputting portion for performing a first mode in which the image data is outputted n times from the storage portion in an output period which is 1/n of the predetermined period, or a second mode in which the image data is outputted (n−k) times (n and k: integral numbers (n>k≧0)) from the storage portion in an output period which is 1/n of the predetermined period;
- an overdrive circuit for, when the first mode is performed, increasing or decreasing a data value of the current image data in accordance with the last image data for a precedent predetermined period and the current image data outputted from the image data-outputting portion, and outputting image data of the increased or decreased data value; and
- a selecting portion for selecting one of the first and second mode to provide a first or second mode signal to the image data-outputting portion and the over drive circuit.
4. An image data-outputting unit according to claim 3, wherein the image data-outputting portion comprises:
- a reading portion for reading out the image data n times from the storage portion in a output period which is 1/n of the predetermined period; and
- a mute circuit for outputting the image data, which is read out n times, (n−k) times for the predetermined period.
5. An image data-outputting unit according to claim 4, wherein the mute circuit outputs the image data (n−k) times in a form of the same output pattern every predetermined period.
6. An image data-outputting unit according to claim 3, wherein the selecting portion is adapted to select a mode in which the overdrive circuit in the first mode is stopped as a third mode.
7. An image data-outputting unit according to claim 3, wherein the overdrive circuit executes overdrive processing in which a difference between the current image data and image data obtained by delaying the current image data by a predetermined time is obtained, and the difference thus obtained is increased or decreased and is outputted.
8. An image data-outputting unit according to claim 7, wherein the overdrive circuit previously stores a plurality of combinations between the predetermined time for delay, and an amount of increase or decrease of the difference.
9. An image data-outputting unit according to claim 7, wherein the overdrive circuit executes the overdrive processing so that a product of the predetermined time for delay and an amount of increase or decrease of the difference becomes the same value every predetermined period.
10. A liquid crystal display device, comprising:
- a storage portion for storing therein image data supplied in a predetermined period;
- an image data-outputting portion for performing a first mode in which the image data is outputted n times from the storage portion in an output period which is 1/n of the predetermined period, or a second mode in which the image data is outputted (n−k) times (n and k: integral number (n>k≧0)) from the storage portion in the period which is 1/n times as large as the predetermined period;
- an overdrive circuit for, when the first mode is performed, increasing or decreasing a data value of the current image data in accordance with the last image data for a precedent predetermined period and the current image data outputted from the image data-outputting portion, and outputting image data of the increased or decreased data value;
- a selecting portion for selecting one of the first and second modes to provide a first or second mode signal to the image data-outputting portion and the overdrive circuit; and
- a liquid crystal panel for displaying thereon an image corresponding to the image data outputted from the image data-outputting portion or the overdrive circuit in accordance with the first or second mode.
11. A liquid crystal display device according to claim 10, wherein the image data-outputting portion comprises:
- a reading portion for reading out the image data n times from the storage portion in a period which is 1/n times of the predetermined period; and
- a mute circuit for outputting the image data, which is read out n times, (n−k) times for the predetermined period.
12. A liquid crystal display device according to claim 11, wherein the mute circuit outputs the image data (n−k) times in a form of the same output pattern every predetermined period.
13. A liquid crystal display device according to claim 11, wherein the selecting portion is adapted to select a mode in which the overdrive circuit in the first mode is stopped as a third mode.
14. A liquid crystal display device according to claim 11, wherein the overdrive circuit executes overdrive processing in which a difference between the current image data and image data obtained by delaying the current image data by a predetermined time is obtained, and the difference thus obtained is increased or decreased and is outputted.
15. A liquid crystal display device according to claim 14, wherein the overdrive circuit previously stores a plurality of combinations between the predetermined time for delay, and an amount of increase or decrease of the difference.
16. A liquid crystal display device according to claim 14, wherein the overdrive circuit executes the overdrive processing so that a product of the predetermined time for delay and an amount of increase or decrease of the difference becomes the same value every predetermined period.
6301431 | October 9, 2001 | Yamagata et al. |
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6977636 | December 20, 2005 | Jinda et al. |
20070165015 | July 19, 2007 | Li et al. |
2002-116743 | April 2002 | JP |
2002-215111 | July 2002 | JP |
Type: Grant
Filed: Dec 27, 2006
Date of Patent: Jul 20, 2010
Patent Publication Number: 20080001871
Assignee: Kabushiki Kaisha Toshiba (Tokyo)
Inventor: Hirotoshi Abe (Saitama)
Primary Examiner: Ricardo L Osorio
Attorney: Pillsbury Winthrop Shaw Pittman, LLP
Application Number: 11/645,622
International Classification: G06F 3/038 (20060101); G09G 5/00 (20060101);