Abstract: A display device includes a display panel, a scan driver outputting a scan signal, and a data driver. The scan driver includes a first sub-scan driver that receives a first start signal and an odd clock signal, and a second sub-scan driver that receives a second start signal and an even clock signal. The scan signal has an activation period corresponding to a horizontal period. The odd clock signal includes a first clock enable period and a first clock disable period, which are ‘k’ times greater than the horizontal period. The even clock signal includes a second clock enable period and a second clock disable period, which are ‘k’ times greater than the horizontal period. The first clock enable period and the second clock enable period alternate with one another.

Abstract: The embodiment relates to a data driving device for driving pixels of a display panel. In the data driving device, two adjacent DACs can have different gate loads for the same gray level value so that the fluctuation of the gate load according to the gray level value is reduced.

Abstract: A method to drive bi-stable liquid crystal displays and related drivers and displays using same are disclosed. The method and driver use additional high impedance states of the outputs to save power while addressing bi-stable and multi-stable liquid crystal displays. The invention implements high impedance states at the driver outputs, allowing non-addressed sections of the display to electrically “float” and by doing so reduces the required power to drive the display. Other advantages include improved visual effect of an update, such as reduced flash during the update, simpler operation, and better yields due to a larger operating window.

Abstract: The present disclosure relates to electronic displays and display components, specifically to a method of addressing more pixels with a smaller number of driver outputs while also allowing very narrow frames on three sides of a display. It further discloses a display driver integrated circuit capable of providing the signals required for the disclosed addressing method and display systems capable of being addressed by the disclosed method and display driver integrated circuit.

Abstract: A display panel, a driving method for the display panel and a display device. The display panel includes a gate driving circuit, the gate driving circuit includes shift registers of a plurality of stages arranged in sequence, the shift registers of the plurality of stages arranged in sequence are combined into N groups of gate driving sub-circuits, and shift registers in the N groups of gate driving sub-circuits are cascaded, respectively; an m-th group of gate driving sub-circuits in the N groups of gate driving sub-circuits comprises a shift register of an m-th stage and a shift register of an (m+L*N)th stage that are cascaded, where m is an integer that is greater than or equal to 1 and less than or equal to N, L is an integer that is greater than or equal to 1, N is an even number that is greater than or equal to 2.

Abstract: A gate driver according to an embodiment and a display device including the same are disclosed. The gate driver according to the embodiment includes an output clock line through which an output clock signal is applied, a dummy clock line disposed side by side with the output clock line and through which a dummy clock signal is applied, a pull-up transistor including a first electrode connected to the output clock line, a gate electrode connected to a first control node, and a second electrode connected to an output node from which a gate signal is output, and a pull-down transistor including a first electrode connected to the output node, a gate electrode connected to a second control node, and a second electrode connected to a power line through which a low-potential power voltage is applied.

Abstract: A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.

Abstract: An electronic device has a display substrate including a display area, a driver area, and a fan-out area. The fan-out area is divided to a plurality of fan-out regions, and has interconnects configured to access display elements formed on the display area. The driver area is adjacent to the fan-out area and configured to receive a driver chip having a plurality of pads. The interconnects of the fan-out area include a subset of first interconnects. Each first interconnect passes a first fan-out region and a second fan-out region to access a respective display element. A first portion of the subset of first interconnects is formed on the first fan-out region with a first interconnect pitch, and a second portion of the subset of first interconnects is formed on the second fan-out region with a second interconnect pitch different from the first interconnect pitch.

Abstract: A display device includes a first display panel; and a second display panel, wherein the first display panel includes a first substrate including a first region and a second region that is thinner than the first region, a first scan driver positioned on one edge of the first region, a second scan driver positioned in the second region, and a plurality of pixels connected to the first scan driver and the second scan driver by a scan line, the second display panel includes a second substrate including a first region and a second region that is thinner than the first region, a first scan driver positioned on one edge of the first region, and a plurality of pixels connected to the first scan driver by a scan line.

Abstract: A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.

Abstract: According to one embodiment, a display device comprises a display panel, first and second driver chips. The display panel includes first and second edge portions, a display area between the first and second edge portions in a first direction, first signal lines extending to the display area, and second signal lines extending to the display area. The first driver chip is connected to the first edge portion to supply video signals to the first signal lines. The second driver chip is connected to the second edge portion to supply video signals to the second signal lines. Number N of the first signal lines and number M of the second signal lines are alternately arranged in a second direction.

Abstract: A display device includes: a first base layer; a circuit element layer on the first base layer; a pixel definition layer on the circuit element layer and comprising a plurality of light-emitting openings which are spaced apart from each other and define a plurality of light-emitting regions; a second base layer spaced apart from and facing the first base layer; a light-shielding layer on the second base layer and comprising a plurality of openings respectively overlapping the light-emitting regions, wherein on a plane of the first base layer, shapes of first to third openings along one direction among the openings are different from each other.

Abstract: It is an object to provide a semiconductor device which can supply a signal with sufficient amplitude to a scan line while power consumption is kept small. Further, it is an object to provide a semiconductor device which can suppress distortion of a signal supplied to the scan line and shorten a rising time and a falling time while power consumption is kept small. A semiconductor device which includes a plurality of pixels each including a display element and at least one first transistor and a scan line driver circuit supplying a signal for selecting the plurality of pixels to a scan line. A light-transmitting conductive layer is used for a pixel electrode layer of the display element, a gate electrode layer of the first transistor, source and drain electrode layers of the first transistor, and the scan line.

Abstract: A display device with favorable display quality is provided. A display portion where a plurality of pixels is arranged in a matrix is divided into Region A and Region B, i.e., regions on the upstream side and the downstream side of a scanning direction. A signal line for supplying an image signal is provided in each of Region A and Region B. Region A and Region B adjoin each other such that a boundary line showing the boundary between the regions is bent. Bending the boundary line suppresses formation of a stripe in a boundary portion. For example, in a given column, the total number of pixels electrically connected to a signal line in Region A is made different from the total number of pixels electrically connected to a signal line in Region B.

Abstract: A display device includes a substrate on which a display area including a plurality of pixels and a non-display area surrounding the display area are defined, a first voltage line disposed on the substrate in the non-display area, where the first voltage line provides a first voltage to the pixels, a second voltage line disposed on the substrate in the non-display area, where the second voltage line provides a second voltage to the pixels, and a first demux circuit area and a second demux circuit area disposed on the substrate in the non-display area, where the first demux circuit area and the second demux circuit area transmit data signals to the pixels. The first voltage line passes an area between the first demux circuit area and the second demux circuit area.

Abstract: A shift-register unit, a grid driving circuit and a displaying device, which relates to the technical field of displaying. In the present disclosure, the oxide-semiconductor layers of the oxide thin-film transistors may be delimited into regions according to the total channel widths and the channel lengths required by the oxide thin-film transistors in the shift-register unit, wherein the sum of the widths of the independent semiconductor branches obtained by the delimitation is equal to the required total channel width. Accordingly, one oxide thin-film transistor can realize the required total channel width by using the one or more semiconductor branches, to ensure the normal operation of the oxide thin-film transistor, whereby the oxide-semiconductor layers of the different oxide thin-film transistors can be configured differently, to realize the purpose of reducing the border frame of the displaying device.

Abstract: An electronic display includes an active area including multiple pixels. The electronic display also includes a first row driver set including a first column of row drivers and a second column of row drivers. A first active row driver in the first column of row drivers drives a first portion of the multiple pixels, and a first spare row driver in the second column of row drivers is in an inactive state. The electronic display also includes a second row driver set including a third column of row drivers and a fourth column of row drivers. A third active row driver in the third column of row drivers drives a second portion of the multiple pixels, and a second spare row driver in the fourth column of row drivers is inactive.

Abstract: A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.

Abstract: To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

Abstract: Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

Abstract: To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

Abstract: The present application provides a distributed system on panel (SOP) display panel and a display system. The distributed SOP display panel includes a plurality of display modules and a plurality of functional modules. Each display module includes a plurality of display units. The functional modules include first functional modules and a second functional module. The first functional modules are electrically connected to the display units in adjacent display modules, the second functional module is electrically connected to the plurality of display modules, in order to alleviate a technical problem of improper layout of system functions of a conventional SOP display device.

Abstract: A display device includes a substrate including a display area and a non-display area, a pixel unit provided in the display area, and including a first pixel column including a plurality of pixels and a second pixel column including a plurality of pixels displaying a different color from a color of the first pixel column, and data lines which are respectively connected to the first pixel column and the second pixel column, and respectively apply data signals to the first pixel column and the second pixel column, wherein the data line connected to the first pixel column includes sub lines and the data line connected to the second pixel column includes sub lines.

Abstract: A display substrate and manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, and a shift register unit and a first clock signal line that are on the base substrate, the first clock signal line extends along a first direction on the base substrate and is configured to provide a first clock signal to the shift register unit, the shift register unit includes an input circuit, an output circuit, a first control circuit and an output control circuit, and the first control circuit includes a first control switch and a second control switch, an active layer of the first control switch and an active layer of the second control switch are a continuous control semiconductor layer, the control semiconductor layer extends along the first direction.

Abstract: Disclosed are a driving circuit, a driving method and a display device. The driving circuit (100) comprises: a data writing circuit (101), configured to, under control of a first scanning signal received at the first scanning signal end, write a data signal received at the data signal end into the first node; a control circuit (102), configured to, under control of a third scanning signal received at the third scanning signal end (SCAN3), write a data signal received by the first node (N1) into the second node (N2); and a driving sub-circuit (103), configured to, under control of a data signal received at the second node (N2), use a driving voltage received at the driving voltage end (Vdd) to drive the light-emitting component 104.

Abstract: A display device includes: active stages each include a scan output circuit outputting a scan clock signal to a first output terminal and a carry output circuit outputting a carry clock signal to a second output terminal, when a voltage of a first node is at a logic high level. The scan output circuit and carry output circuit output a scan signal of a turn-off level to the first output terminal when a voltage of a second node or a carry signal is at a logic high level. An interval between pulses of the carry clock signal generated during one frame period is the same, and at least two of intervals between pulses of the scan clock signal generated during the one frame period are different from each other.

Abstract: This application provides a signal decoding method, a decoding circuit, and a stylus. In one example, a to-be-measured signal is sampled to obtain a plurality of sampled signals. The to-be-measured signal is a modulation signal that carries an interference signal. The modulation signal is sent by a touch panel of a terminal device. At least two edge signals in the to-be-measured signal are determined based on the plurality of sampled signals. The to-be-measured signal is decoded based on the at least two edge signals to obtain the modulation signal.

Abstract: The disclosure includes: first level shift part generating a voltage signal by converting an input voltage signal into amplitude between first negative and positive polarity power supply voltages; second level shift part generating a first polarity voltage signal by converting the voltage signal into amplitude between a reference and the first positive polarity power supply voltage; third level shift part outputting a first-polarity high voltage signal by converting the first polarity voltage signal into amplitude between a higher second positive polarity power supply voltage and the reference; fourth level shift part generating a second polarity voltage signal by converting the voltage signal into amplitude between the reference and the first negative polarity power supply voltage; and fifth level shift part outputting a second-polarity high voltage signal by converting the second polarity voltage signal into amplitude between a lower second negative polarity power supply voltage and the reference.

Abstract: The present disclosure relates to a gate driving circuit and a display device including the gate driving circuit, and more particularly, to a gate driving circuit having a reduced size and a display device including the gate driving circuit. The gate driving circuit comprises a plurality of dummy stage circuits and stage circuits, which supply gate signals to each gate line and comprise a Q node, a QH node, and a QB node. A gate signal output circuit included in each of the stage circuits can output first to j-th gate signals based on first to j-th scan clock signals or a first low voltage according to the voltage level of the Q node or the voltage level of the QB node.

Abstract: An array substrate and a testing method thereof are provided. The array substrate includes a gate driving circuit, a plurality of clock signal lines and a plurality of testing terminals, wherein a number of the clock signal lines is greater than a number of the testing terminals; the plurality of clock signal lines are connected to the gate driving circuit and the plurality of testing terminals, and at least two clock signal lines are connected to a same testing terminal; and the plurality of testing terminals are configured to connect to a testing device.

Abstract: Provided is a display panel. The display panel includes multiple scanning lines, a gate driver circuit, and a timing controller. The timing controller is configured to: receive multiple data enable signals, generate a gate control signal, and provide the gate control signal for the gate driver circuit. The gate control signal includes a start signal, a first clock signal and a second clock signal. The multiple data enable signals are only within the active cycle. The timing controller is configured to generate a rising edge and a falling edge of the start signal within a time interval formed by a rising edge and a falling edge of a first data enable signal in the Nth frame cycle.

Abstract: Disclosed are a memory device and a read/write method of the memory device and, more particularly, a memory device and a read/write method of the memory device capable of reducing power consumption of a display device by reducing a storage operation and an output operation of the memory device for a plurality of pieces of pixel data.

Abstract: A shift register, a gate driving circuit, and a display panel. The shift register includes a first input module, a second input module, a first output module, a second output module, a first output control module, and a second output control module, where the first input module is configured to control the potential of a first node according to a first start signal and a first clock signal, the second input module is configured to control the potential of a second node according to a second start signal and the first clock signal, and the second start signal and the first start signal have opposite potentials; the first output module includes a first coupling unit configured to couple the potential of a third node according to the potential of a first output terminal in the case where the potential of the first output terminal jumps.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a blanking input circuit, a blanking control circuit, a blanking coupling circuit, a display input circuit and an output circuit. The blanking input circuit is configured to charge a control node in response to a compensation selection control signal, and to maintain a level of the control node. The blanking control circuit is configured to charge a first node, by using a first clock signal, under control of the level of the control node and the first clock signal. The blanking coupling circuit is electrically connected to the control node, and is configured to control, by coupling, the level of the control node in response to the first clock signal.

Abstract: An embodiment is able to improve the pure-color brightness ratio by compensating for image data of a current pixel on the basis of a result of comparing image data of a current pixel with image data of a previous pixel.

Abstract: The circuit includes a first transistor; a second transistor whose first terminal is connected to a gate of the first transistor for setting the potential of the gate of the first transistor to a level at which the first transistor is turned on; a third transistor for setting the potential of a gate of the second transistor to a level at which the second transistor is turned on and bringing the gate of the second transistor into a floating state; and a fourth transistor for setting the potential of the gate of the second transistor to a level at which the second transistor is turned off. With such a configuration, a potential difference between the gate and a source of the second transistor can be kept at a level higher than the threshold voltage of the second transistor, so that operation speed can be improved.

Abstract: A shift-register unit includes a first circuit including a first input circuit coupled via a first node to a first output circuit, and a second circuit including a second input circuit coupled via a second node to a second output circuit. The first input circuit is configured to control a voltage level of the first node in response to a first input signal. The first output circuit is configured to output a shift-register signal and a first output signal in response to the voltage level of the first node. The second input circuit is configured to control a voltage level of the second node in response to the first input signal. The second output circuit is configured to output a second output signal in response to the voltage level of the second node. The first input circuit and the second input circuit have a same circuit structure.

Abstract: Methods of manufacturing a wound monitoring and/or therapy apparatus and/or wound dressing include positioning electronic components and connections in regions of a substrate that are not configured to be perforated. The methods can also include following a set of rules for positioning the components as well as positioning and shaping the connections based on the constraints stemming from, among other things, the positioning of the perforations on the substrate and with the goal of maintaining acceptable levels of signal integrity. The methods further include manufacturing a multi-layered substrate. Wound monitoring and/or therapy apparatus manufactured using such methods are also disclosed.

Abstract: A display device includes gate lines and pixels connected to the gate lines. The display device includes stages which provide gate signals to the gate lines, and first and second gate power lines which transfer a first voltage to the stages. A first stage among the stages includes a first node controller and a first output unit. The first node controller is connected to the second gate power line, and controls a voltage of a first control node. The first output unit is connected to the first gate power line, and outputs a first voltage of the first gate power line as a gate signal in response to a voltage of the first control node.

Abstract: A control method for an electronic apparatus includes obtaining a first positional relationship between eyes of a user and a first display area and a second positional relationship between eyes of the user and a second display area and setting a brightness value of the first display area and a brightness value of the second display area at least based on the first positional relationship and the second positional relationship. The electronic apparatus includes the first display area. The user includes a subject that uses the electronic apparatus. The first display area and the second display area move relative to each other.

Abstract: A shift register circuit includes a denoising control sub-circuit and a denoising sub-circuit. The denoting control sub-circuit is configured to generate an alternating voltage signal according to a voltage of a first voltage terminal and a signal of a second clock signal terminal in response to a signal of a first clock signal terminal, to rectify the alternating voltage signal and then to output a signal to a first denoising control node, so that the voltage of the first denoting control node is maintained to be a voltage that enables the denoising sub-circuit to be turned on. The denoting sub-circuit is configured to denoise a scan signal output terminal in response to a voltage of the first denoising control node being the voltage that enables the denoising sub-circuit to be turned on.

Abstract: A data processing method of a driving circuit and a driving circuit are provided. Wherein, the data processing method of the driving circuit can include obtaining a timing parameter, performing data processing based on the timing parameter and obtaining a first processing result, decoding the first processing result according to a preset reference voltage and obtaining a second processing result, and amplifying the second processing result, and outputting an amplified second processing result.

Abstract: In a semiconductor device and a shift register, low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire.

Abstract: A display device includes a display panel including a first area and a second area spaced apart from the first area in a plan view. The display panel includes a first base layer including a first pixel, a second base layer facing the first base layer and including a second pixel, a first signal line electrically connected to the first pixel of the first area, a second signal line electrically connected to the second pixel of the second area, and a connection line electrically connecting the first signal line and the second signal line.

Abstract: The present application discloses a display panel and a display device. The display panel includes a non-display region and a gate driver on array (GOA) unit region in the non-display region. The GOA unit region includes multi-level GOA units arranged in multiple columns, thereby improving a space limitation problem associated with arranging a plurality of GOA units in a display panel while the display panel achieves high resolution.

Abstract: To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

Abstract: An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 ?m is 1 aA or less.

Abstract: Provided are a display driving method and apparatus, and a display panel and an electronic device. The display driving method is applied to a display panel, and comprises: determining a first charging duration of each display point on the basis of a preset position, in a display panel, of each display point in the display panel; generating, according to the first charging duration of each display point, a display control signal corresponding to each display point; and adjusting a second charging duration of each display point according to the display control signal.

Abstract: A display device includes: a first pixel connected to a first data line and a first scan line; a second pixel connected to the first data line and a second scan line; a first scan driver connected to a first scan start line and the first scan line; and a second scan driver connected to a second scan start line and the second scan line. In a first frame period, the second scan start line is to be suppled with a second scan start signal having a turn-on level, after a first period elapses after a first scan start signal having a turn-on level is supplied to the first scan start line. In a second frame period, a difference between a time at which the first scan start signal having the turn-on level is supplied and a time at which the second scan start signal having the turn-on level is supplied corresponds to a second period. The second period is shorter than the first period.

Abstract: A flat panel display device formed in a pentile structure is provided, which includes a pixel portion and a lighting tester. The pixel portion includes a first pixel column, a second pixel column and a third pixel column. In the first pixel column, first pixels for displaying a first color and second pixels for displaying a second color are alternately arranged in a direction the data lines. In the second pixel column, first and second pixels arranged in reverse order of the first pixel column in a direction parallel to the data lines. In the third pixel column, third pixels for displaying a third color are arranged in a direction parallel to the data lines. The lighting tester applies a first voltage to the first pixel column and applies a second voltage to the second pixel column during a first time period. The lighting tester applies the second voltage to the first pixel column and applies the first voltage to the second pixel column during a second time period.