Abstract: A shift register includes n shift register units which are cascaded. Each shift register unit includes a shift module and multiple enable modules. The shift module of an i-th-level shift register unit is configured to receive and latch a shift signal output by the shift module in an (i?1)-th-level shift register unit. The multiple enable modules of the i-th-level shift register unit are electrically connected to the shift module of the i-th-level shift register unit, and each of the multiple enable modules is configured to generate a gate driving signal according to the shift signal. n and i are positive integers, 1?i?n.

Abstract: The present invention provides a fingerprint identification panel and the fingerprint identification circuit thereof, which comprise a gate driving circuit, a source driving circuit, and a detection circuit. The gate driving circuit is coupled to a plurality of gate lines, outputs a plurality of gate signals to the plurality of gate lines, and controls a state transition of the plurality of gate signals. The source driving circuit is coupled to a plurality of source lines. The detection circuit is coupled to the plurality of source lines or to a portion of the plurality of source lines. The detection circuit detects the levels of the plurality of signals on the coupled source lines when the state of the gate signal is changed and generates a plurality of detection signals.

Abstract: A source driver includes a plurality of shift register groups cascaded in sequence, an enable control circuit and at least one switching circuit electrically connected to the enable control circuit. Each shift register group includes a plurality of stages of shift registers, and is configured to sample digitized image data; a first start signal of an n-th shift register group is output by an (n?1)-th shift register group, n is a positive integer greater than 2. The enable control circuit is configured to output a first turn-on signal or a first turn-off signal. In two adjacent shift register groups, a last-stage shift register in a present shift register group is electrically connected to a first-stage shift register in a next shift register group through a switching circuit.

Abstract: An electronic device includes a display panel including pixels respectively connected to scan lines, scan stages corresponding to the scan lines, where each of the scan stages receives a carry signal, and outputs a scan signal, masking circuits electrically connected to some of the scan stages, respectively, where each of the masking circuits outputs a masking carry signal in response to a masking signal and the scan signal, and transmission circuits electrically connected to others of the scan stages, respectively, where each of the transmission circuits outputs the scan signal output from a corresponding scan stage among the scan stages. A j-th (j is an integer greater than 1) scan stage among the scan stages receives one of the scan signal output from a (j?1)-th scan stage and the masking carry signal as the carry signal.

Abstract: An array substrate includes pixel electrodes arranged in an array, a plurality of scan lines extending along the row direction of the array and arranged along the column direction of the array and a plurality of data lines extending along the column direction and arranged along the row direction. One group of data lines includes a first data line and a second data line. The loaded drive voltage of the first data line and the loaded drive voltage of the second data line are different in the same frame. The driving process of one frame includes a reset stage and a display stage. At the reset stage, the first data line is connected to the second data line. At the display stage, the first data line is disconnected from the second data line.

Abstract: To provide a novel shift register. Transistors 101 to 104 are provided. A first terminal of the transistor 101 is connected to a wiring 111 and a second terminal of the transistor 101 is connected to a wiring 112. A first terminal of the transistor 102 is connected to a wiring 113 and a second terminal of the transistor 102 is connected to the wiring 112. A first terminal of the transistor 103 is connected to the wiring 113 and a gate of the transistor 103 is connected to the wiring 111 or a wiring 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103, a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102.

Abstract: An electroluminescent display device includes a display panel including a display region, which includes a plurality of pixel arrangement regions and a plurality of scan circuit regions between the plurality of pixel arrangement regions, and a non-display region around the display region; a scan driving circuit formed in the plurality of scan circuit regions, and a clock signal line transferring a clock signal, and a first voltage line and a second voltage line located at both sides of the clock signal line, the clock signal line and the first and second voltage lines being located in the scan circuit region, wherein the first voltage line transfers a low potential driving voltage which is supplied to a cathode corresponding to the display region.

Abstract: A display substrate, a manufacturing method and a display device are provided. The display substrate includes a scan driving circuit; the scan driving circuit includes a plurality of shift register units, at least one shift register unit includes a signal output line and an output circuit, the output circuit includes an output transistor and an output reset transistor; the signal output line includes a first output line portion extending along the first direction; the first output line portion is coupled to the second electrode of the output transistor or the output reset transistor through a plurality of first or second signal line via holes arranged in a signal line overlap area, and the plurality of first or second signal line via holes are arranged along the first direction.

Abstract: The present application provides a gate driving unit circuit and a method of driving the same, a gate driving circuit and a display apparatus. The gate driving unit circuit includes a shift register and a plurality of driving signal output sub-circuits. Each driving signal output sub-circuit corresponds to one of gate lines on an array substrate, is coupled to a first power supply terminal and a signal output terminal of the shift register, and also coupled to a corresponding one of driving scan signal lines. Each driving signal output sub-circuit is configured to output, under the control of a signal output by the signal output terminal of the shift register, a driving scan signal provided by the corresponding driving scan signal line or an OFF voltage provided by the first power supply terminal to the corresponding gate line.

Abstract: To suppress a change in electrical characteristics and to improve reliability in a semiconductor device using a transistor including an oxide semiconductor. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film which is between the gate electrode and the oxide semiconductor film and is in contact with a surface of the oxide semiconductor film, a protective film in contact with an opposite surface of the surface of the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film. In the gate insulating film or the protective film, the amount of gas having a mass-to-charge ratio m/z of 17 released by heat treatment is greater than the amount of nitrogen oxide released by heat treatment.

Abstract: An electronic device and a scan driving circuit each including a shift register and a demultiplexer are provided. The demultiplexer is electrically connected to the shift register. The demultiplexer includes at least one scan unit. The at least one scan unit includes a switch circuit and a buffer. An input terminal of the buffer is electrically connected to the switch circuit. An output terminal of the buffer is electrically connected to a scan line.

Abstract: A display driving device for improving the definition of an image according to one aspect of the present invention includes a brightness calculator for calculating first brightness data corresponding to a first resolution and second brightness data corresponding to a second resolution less than the first resolution using input image data, an offset calculator for calculating an offset on the basis of the first brightness data and the second brightness data, an input image converter for converting the input image data into input image data to which the calculated offset has been applied, a first data output unit for generating output image data for a first panel using the converted input image data and outputting the generated output image data, and a second data output unit for generating output brightness data for a second panel using the second brightness data and outputting the generated output brightness data.

Abstract: A display device includes: active stages each include a scan output circuit outputting a scan clock signal to a first output terminal and a carry output circuit outputting a carry clock signal to a second output terminal, when a voltage of a first node is at a logic high level. The scan output circuit and carry output circuit output a scan signal of a turn-off level to the first output terminal when a voltage of a second node or a carry signal is at a logic high level. An interval between pulses of the carry clock signal generated during one frame period is the same, and at least two of intervals between pulses of the scan clock signal generated during the one frame period are different from each other.

Abstract: An array substrate and a display panel are disclosed in an embodiment of the present application. The array substrate includes a plurality of GOA units in cascade and a plurality of clock signal lines. The plurality of clock signal lines are arranged on one side of the GOA units and are arranged at intervals along a direction away from the GOA units. The plurality of GOA units are electrically connected to the plurality of clock signal lines, respectively. Wherein, a number of the GOA units electrically connected to each of the clock signal lines is equal. The array substrate reduces a resistance difference and a capacitance difference between the plurality of clock signal lines and alleviates a problem of dense horizontal lines by adjusting a number of stages of the GOA units.

Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.

Abstract: A pixel circuit, a method for driving the pixel circuit and a display device including the same are disclosed. The pixel circuit includes a driving element including a first electrode connected to a first power line to which a pixel driving voltage is applied, a gate electrode connected to a first node, and a second electrode connected to a second node; a first switch element including a first electrode connected to a second power line to which a data voltage is applied, a gate electrode to which a first scan pulse is applied, and a second electrode connected to the first node; a second switch element including a first electrode connected to the second power line, a gate electrode to which a second scan pulse is applied, and a second electrode connected to the first node.

Abstract: To provide a novel shift register. Transistors 101 to 104 are provided. A first terminal of the transistor 101 is connected to a wiring 111 and a second terminal of the transistor 101 is connected to a wiring 112. A first terminal of the transistor 102 is connected to a wiring 113 and a second terminal of the transistor 102 is connected to the wiring 112. A first terminal of the transistor 103 is connected to the wiring 113 and a gate of the transistor 103 is connected to the wiring 111 or a wiring 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103, a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102.

Abstract: A power management integrated circuit includes a flip-flop circuit configured to perform a logic operation on a start clock signal which sets a driving start time point of a gate driving circuit and an on-clock signal which sets an output start time point of the gate driving circuit; a first AND gate circuit configured to receive one among output signals of the flip-flop circuit and the start clock signal, to perform an AND logic operation thereon, and to generate a gate start signal; and a second AND gate circuit configured to receive the other of the output signals of the flip-flop circuit and the start clock signal, to perform an AND logic operation thereon, and to generate a gate reset signal.

Abstract: A display panel and a display device are provided. The display panel and display device include gate driver on array (GOA) units in a first column, GOA units in a second column, and signal input lines. By adjusting a positional relationship between the signal input line and the GOA units in the first column and the GOA unit in the second column, the GOA units in the first column and the GOA units in the second column may share the signal input line, so as to save a set of signal input lines and reduce a width of the frame area.

Abstract: Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

Abstract: A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.

Abstract: A display substrate and manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, and a shift register unit and a first clock signal line that are on the base substrate, the first clock signal line extends along a first direction on the base substrate and is configured to provide a first clock signal to the shift register unit, the shift register unit includes an input circuit, an output circuit, a first control circuit and an output control circuit, and the first control circuit includes a first control transistor and a second control transistor, an active layer of the first control transistor and an active layer of the second control transistor are a continuous control semiconductor layer, the control semiconductor layer extends along the first direction.

Abstract: Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.

Abstract: A method and light-emitting diode (LED) device configured to compensate for crosstalk between rows of the LED device.

Abstract: A shift register comprises a first shift register unit and a second shift register unit. The first shift register unit comprises a first input circuit connected to a first input terminal and a first pull-up node, a first output circuit connected to the first pull-up node, a first output terminal and a first clock terminal, a first pull-down circuit and a unidirectional isolation circuit, and the first output terminal is connected to the first pull-down circuit by the unidirectional isolation circuit. The second shift register unit comprises a second input circuit connected to a second input terminal and a second pull-up node, and a second output circuit connected to the second pull-up node, a second output terminal and a second clock signal, and the second output terminal is connected to a node between the first pull-down circuit and the unidirectional isolation circuit.

Abstract: An artificial neural network (ANN) generates a base expanded matrix that represents an output of a layer of the ANN, such as the output layer. Values in each row are grouped with respect to a set of network parameters in a previous layer, and a sum of the values in each row produces an output vector of activations. The ANN updates the values in at least one column of the expanded matrix according to parameter updates, which results in an updated expanded matrix or an update expanded matrix. An error or a total cost can be computed from the updated expanded matrix or the update expanded matrix. Nonlinear activation functions can be modeled as piecewise linear functions, and a change in an activation function's slope can be modeled as a linear update to an expanded matrix. Parameter updates can be constrained to a restricted value set in order to simplify update operations performed on the expanded matrices.

Abstract: A display device includes: a pixel unit including pixels connected to data lines and scan lines, and signal output lines, where at least one signal output line of the signal output lines is connected to each of the scan lines through a contact point; a data driver disposed at one side of the pixel unit to drive the data lines; a scan driver disposed at the one side of the pixel unit together with the data driver to drive the scan lines; and a timing controller controlling the data driver and the scan driver. The data driver includes: output buffers outputting data signals to the data lines, respectively; and a slew rate controller adjusting a slew rate of the data signals by controlling a bias value supplied to the output buffers in units of pixel rows based on positions of the pixels and a change in the data signals.

Abstract: A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

Abstract: According to one embodiment, a display device includes a first common electrode and a second common electrode arranged in a first direction, a first switch unit selectively supplying a first drive signal or a second drive signal different from the first drive signal to the first common electrode, and a second switch unit selectively supplying the first drive signal or the second drive signal to the second common electrode, wherein the second common electrode and the first switch unit are arranged in a second direction intersecting the first direction, the first switch unit comprises a first switch circuit and a second switch circuit arranged in the second direction.

Abstract: A liquid crystal display device according to the present disclosure includes: a liquid crystal unit including a pixel electrode, a counter electrode facing the pixel electrode, and a liquid crystal layer sealed between the pixel electrode and the counter electrode; a first writing circuit configured to write a positive polarity video signal among video signals whose polarity changes periodically; and a second writing circuit configured to write a negative polarity video signal among the video signals whose polarity changes periodically. The liquid crystal unit, the first writing circuit, and the second writing circuit are provided for each pixel. The first writing circuit and the second writing circuit include transistors having conductivity types different from each other.

Abstract: A gate driving unit includes an input module, a first output module, a second output module, a feedback module, and an output-controlling module. The input module outputs a previous level-transferring signal into a first node. The first output module outputs a present level-transferring signal. The second output module outputs a scan signal. The feedback module outputs a present-level feedback signal. The output-controlling module pulls up potential of the scan signal to a first direct-current high voltage and pulls up potential of the present level-transferring signal to a second direct-current high voltage.

Abstract: A display apparatus, including a display panel and a first driver, is provided. The display panel includes multiple pixel circuits and multiple first wires. The first wires are configured to transmit multiple first driving signals. Each of the first wires includes a first portion and a second portion. The first driving signal is transmitted in the first portion and the second portion in different directions. The first driver is coupled to the display panel. The first driver is configured to output the driving signals to drive the display panel.

Abstract: The present disclosure relates to a circuit of controlling a common voltage of a liquid crystal panel. According to an embodiment of the present disclosure, a voltage control circuit is configured to provide a common voltage to a common electrode of a liquid crystal panel. The liquid crystal panel includes M rows and N columns of pixel units. Each pixel unit is coupled to the common electrode. The voltage control circuit includes an operational amplifier arranged in a negative feedback configuration. The operational amplifier includes: an input stage, a gain stage and an output stage. The output stage includes a second NMOS transistor and a second PMOS transistor. A gate of the second NMOS transistor receives a first control signal, a drain of the second NMOS transistor is coupled to a gate of a first PMOS transistor, and a source of the second NMOS transistor is coupled to a second reference voltage.

Abstract: A DLDO has a configuration that mitigates performance degradation associated with limit cycle oscillation (LCO). The DLDO comprises a clocked comparator, an array of power transistors, a digital controller and a clock pulsewidth reduction circuit. The digital controller comprises control logic configured to generate control signals that cause the power transistors to be turned ON or OFF in accordance with a preselected activation/deactivation control scheme. The clock pulsewidth reduction circuit receives an input clock signal having a first pulsewidth and generates the DLDO clock signal having the preselected pulsewidth that is narrower that the first pulsewidth, which is then delivered to the clock terminals of the clocked comparator and the digital controller. The narrower pulsewidth of the DLDO clock reduces the LCO mode to mitigate performance degradation caused by LCO.

Abstract: A detection device is provided and includes insulating substrate; detection element including first photodiode, first thin film transistor, second thin film transistor, and third thin film transistor; dummy element including second photodiode and first thin film transistor; and first scan line, wherein first scan line is a gate of each of first thin film transistors, dummy element is located adjacent to detection element, and dummy element includes first photodiode and none of second thin film transistor and third thin film transistor.

Abstract: The present application provides a gate driving unit circuit and a method of driving the same, a gate driving circuit and a display apparatus. The gate driving unit circuit includes a shift register and a plurality of driving signal output sub-circuits. Each driving signal output sub-circuit corresponds to one of gate lines on an array substrate, is coupled to a first power supply terminal and a signal output terminal of the shift register, and also coupled to a corresponding one of driving scan signal lines. Each driving signal output sub-circuit is configured to output, under the control of a signal output by the signal output terminal of the shift register, a driving scan signal provided by the corresponding driving scan signal line or an OFF voltage provided by the first power supply terminal to the corresponding gate line.

Abstract: It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.

Abstract: An electro-optic display having a plurality of pixels is driven from a first image to a second image using a first drive scheme, and then from the second image to a third image using a second drive scheme different from the first drive scheme and having at least one impulse differential gray level having an impulse potential different from the corresponding gray level in the first drive scheme. Each pixel which is in an impulse differential gray level in the second image is driven from the second image to the third image using a modified version of the second drive scheme which reduces its impulse differential The subsequent transition from the third image to a fourth image is also conducted using the modified second drive scheme but after a limited number of transitions using the modified second drive scheme, all subsequent transitions are conducted using the unmodified second drive scheme.

Abstract: A driving apparatus for a display panel is provided. The driving apparatus for the display panel is configured on a film by means of a Chip-on-Film (COF) package. A selection circuit receives multiple driving voltages. A control circuit is coupled to the selection circuit and controls the selection circuit to output one of the multiple driving voltages, so as to drive the display panel.

Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.

Abstract: Provided are gate driver circuit, display panel, display device, and driving method thereof. The gate driver circuit includes cascaded shift registers. Each shift register includes input unit, node control unit, first output unit, and second output unit. first terminal, control terminal, and second terminal of the input unit respectively electrically connected to signal input terminal, first signal terminal, and first node. first terminal, second terminal, third terminal, fourth terminal, first control terminal, second control terminal and fifth terminal of the node control unit respectively electrically connected to the first node, the first signal terminal, first power supply voltage terminal, second power supply voltage terminal, the first node, second signal terminal, and second node. As such, one shift register outputs two control signals, the number of shift registers in the gate driver circuit can be reduced, and the bezel of the display panel and the display device can be reduced.

Abstract: Disclosed is an electronic device including a display panel displaying an image, a source driver supplying a source voltage to the display panel, and a display driver integrated circuit (DDI) including a timing controller controlling the source driver. The timing controller may be configured to identify information associated with a luminance of the image and to set a source bias current for controlling a slew rate of the source voltage based on the luminance of the image. Besides, various embodiments as understood from the specification are also possible.

Abstract: A display device is provided. The device comprises a pixel array, a scanning circuit configured to select a row in the pixel array, and a signal output circuit configured to supply image signals to pixels arranged in the row selected by the scanning circuit. The device displays an image using pixels arranged between an initial line on one side in the pixel array and an end line succeeding the initial line on the other side. The scanning circuit includes a start designation circuit configured to designate the initial line, an end designation circuit configured to designate the end line and a shift register. The shift register is configured to start selection for writing the image signals from the initial line and sequentially select the rows between the initial line and the end line in one frame period for displaying one image.

Abstract: A display device includes a display panel having a curved side or a polygonal side, the display panel including a plurality of pixels in a display region, a gate driver including a plurality of normal stages connected to each other for outputting gate signals to the pixels via a plurality of gate lines, and a plurality of dummy stages between some of the normal stages, and a data driver providing data signals to the pixels via a plurality of data lines.

Abstract: A source driver includes a data latch unit that outputs acquired pixel data, a gradation voltage conversion unit that acquires the pixel data outputted from the data latch unit and converts the pixel data to gradation voltages, an output unit that amplifies and outputs the gradation voltages to source lines, and a timing control unit that controls the timing of the output of the pixel data from the data latch unit. The timing control unit performs control such that the longer a source line is from a source driver to a pixel column, the smaller the timing difference is between acquisition of the pixel data by the data latch unit and the output of the pixel data.

Abstract: A display device includes a substrate that includes a display area for displaying an image and a non-display area surrounding the display area, a plurality of pixels that are disposed in the display area and each include an organic light emitting diode and a pixel circuit portion configured to operate the organic light emitting diode, and a scan driver that is disposed in the non-display area and includes a plurality of stages configured to output scan signals to the plurality of pixels. The plurality of stages may be arranged in n columns, a height of one stage may correspond to a height of n pixels, and n may be an integer of 2 or more.

Abstract: A gate driver and a display device including the same, are discussed. The gate driver includes a plurality of stages which are dependently connected to each other. Each of the plurality of pixels includes an output unit which outputs a gate voltage by a voltage of an RQ node, a voltage of a PQ node, and a voltage of a QB node, a first controller which controls the RQ node, a second controller which controls the PQ node, and a third controller which controls the QB node. The gate voltage is configured by a first clock signal having a first phase and a second clock signal having a first phase which is different from the first phase of the first clock signal.

Abstract: A flat-panel display comprises a display substrate, an array of pixels distributed in rows and columns over the display substrate, the array having a column-control side, and column controller disposed on the column-control side of the array providing column data to the array of pixels through column-data lines. In some embodiments, rows of pixels in the array of pixels form row groups and each column of pixels in a row group receives column data through a separate column-data line. In some embodiments, each pixel in each column of pixels in the array of pixels is serially connected and each pixel in the array of pixels comprises a token-passing circuit for passing a token through the serially connected column of pixels.

Abstract: A gate driving circuit includes a first gate driving circuit and a second gate driving circuit, wherein the m number of first clock signals input to the first gate driving circuit includes an (n+1)-th clock signal and an (n+k)-th clock signal, and the m number of second clock signals input to the second gate driving circuit includes an (n+2)-th clock signal and an (n+k+1)-th clock signal, where the n is any integer, and the k is a natural number of 3 or more, a high level voltage duration of the (n+1)-th clock signal and a high level voltage duration of the (n+k)-th clock signal do not overlap, and a high level voltage duration of the (n+2)-th clock signal and a high level voltage duration of the (n+k+1)-th clock signal do not overlap.

Abstract: A backlight system includes a backlight and a master driving circuit. The backlight includes a plurality of slave driving circuits and a plurality of light sources driven by the plurality of slave driving circuits, wherein the plurality of slave driving circuits are arranged in a matrix of driving rows and driving columns such that first through m-th slave driving circuits, where m is a positive integer greater than one, are arranged in each driving row of the driving rows, and the first through m-th slave driving circuits are connected in a daisy chain structure. The master driving circuit is configured to generate a plurality of input data signals, wherein each input data signal of the plurality of input data signals corresponds to the each driving row, and the each input data signal includes first through m-th packets including luminance data corresponding to the first through m-th slave driving circuits.