Abstract: A display device comprising: a plurality of pixel electrodes supplied with a pixel signal and a display functional layer configured to perform a display operation based on the pixel signal; a plurality of touch detection electrodes configured to output a touch detection signal and perform a touch detection operation; and a controller configured to control the display operation and the touch detection operation.

Abstract: A driver control circuit and a display device are disclosed, where the driver control circuit includes: a first transistor with a first terminal connected with a supply voltage of a main loop, and a second terminal connected with a first ground terminal; and a first control component connected with a control terminal of the first transistor, and configured to control the first transistor to be in a state of incomplete conduction in amplification region, when the supply voltage of the main loop is powered on.

Abstract: A gate driver includes clock signal lines respectively transferring clock signals, at least two of the clock signals being mutually the same; and gate driving units electrically connected to the clock signal lines, respectively and configured to sequentially generate gate signals having a multi-clock pulse based on the clock signals.

Abstract: A display device includes a display panel having a curved side or a polygonal side, the display panel including a plurality of pixels in a display region, a gate driver including a plurality of normal stages connected to each other for outputting gate signals to the pixels via a plurality of gate lines, and a plurality of dummy stages between some of the normal stages, and a data driver providing data signals to the pixels via a plurality of data lines.

Abstract: A display device that achieves both high-accuracy sensing by a touch sensor unit and smooth input using the touch sensor unit is provided. The display device includes a display unit and the touch sensor unit. The touch sensor unit performs touch sensing operation at a different timing from display image rewriting by the display unit, whereby the high-accuracy sensing can be achieved. The display unit has a function of rewriting a display image only in a region that needs to be rewritten. In the case where the entire display region is not necessarily rewritten, the time for the sensing operation by the touch sensor unit can be lengthened, whereby the smooth input can be achieved.

Abstract: A gate driving unit and a gate driving method are provided. The gate driving unit includes an input unit, a driving unit, a pull-down unit, and a pull-down control unit. The pull-down unit has an output terminal of a current stage cascaded signal and an output terminal; in the pull-up phase, the output terminal of the current stage cascaded signal and the output terminal output signal, a voltage of the output terminal of the current stage cascaded signal is pulled down to a first reference low electric level, and a voltage of the output terminal is pulled down to a second reference low electric level.

Abstract: A gate driving circuit includes driving stages for providing gate signals to gate lines of a display panel. A k-th driving stage a k-th driving stage (k being equal to or greater than 2) among the driving stages includes a gate output unit configured to output a clock signal as a k-th gate signal in response to a voltage of a first node, a carry output unit configured to output the clock signal as a k-th carry signal in response to the voltage of the first node, a control unit configured to control a voltage level of the first node in response to a (k?1)th carry signal, a first discharge unit configured to discharge the k-th carry signal to a voltage level in response to the (k?1)th carry signal, and a second discharge unit configured to discharge the k-th carry signal to a voltage level in response to a discharge signal.

Abstract: A shift register unit, a gate driving circuit, a display device and a driving method are provided. The shift register unit includes an input circuit, an output circuit, a first reset circuit, a second reset circuit and a common reset circuit. The input circuit is configured to control a level of a first node in response to an input signal; the output circuit includes an output terminal and is configured to output an output voltage signal to the output terminal under control of the level of the first node; the common reset circuit includes a reset control terminal and is configured to reset the first node when a reset turn-on signal is input to the reset control terminal; and the first reset circuit is configured to provide the reset turn-on signal to the reset control terminal in response to a first reset signal.

Abstract: The display device is provided with a precharge power source that supplies only precharge voltages (precharge voltages corresponding to the maximum gradation value for each of the positive polarity and the negative polarity) corresponding to one gradation value. The source driver includes a data voltage generation circuit configured to generate data voltage depending on input data and an output circuit configured to apply the data voltage to each source bus line after applying precharge voltage. The output circuit changes the length of the precharging period during which the precharge voltage is applied to each source bus line, depending on input data.

Abstract: A flexible display device including a first display area including first data lines arranged in a first direction, first scan lines arranged in a second direction intersecting the first direction, and first pixels arranged in regions defined by the first data lines and the first scan lines, a second display area including second data lines arranged in the first direction, second scan lines arranged in the second direction, and second pixels arranged in regions defined by the second data lines and the second scan lines, a first bending area disposed between the first and second display areas, a first circuit unit disposed adjacent to a first side of the first display area, a second circuit unit disposed adjacent to a second side of the first display area, and a third circuit unit disposed adjacent to a first side of the second display area.

Abstract: A chip-on-film package includes a base substrate on which a first pad region, a second pad region, and a third region located between the first pad region and the second pad region are defined, a dummy pad disposed on the first pad region, input pads disposed on the first pad region, output pads disposed on the second region, a first detection line disposed on the base substrate, and a second detection line disposed on the base substrate. The first detection line is connected to a first input pad and a second input pad via the second pad region to form a first loop between the first input pad and the second input pad, and the second detection line is connected to the dummy pad and the first detection line via the third region to form a second loop between the dummy pad and the first input pad.

Abstract: A display device including: a controller including: a zone splitting block configured to divide input image data into a plurality of partial image data respectively corresponding to a plurality of partial panel zones of the display panel; a plurality of panel zone frequency deciding blocks configured to determine a plurality of driving frequencies for the plurality of partial panel zones by analyzing the plurality of partial image data, respectively; a non-driving period setting block configured to classify a plurality of frame periods into a driving frame period and a non-driving frame period based on a maximum driving frequency of the plurality of driving frequencies; and a scan driver control block configured to provide the scan driver input signal to the scan driver in the driving frame period, and to not provide the scan driver input signal to the scan driver in the non-driving frame period.

Abstract: Provided is an electric field generating substrate and a liquid crystal lens containing the same. The electric field generating substrate contains: a first substrate; and a first electric field generating unit disposed on the first substrate. The first electric field generating unit contains: a first main electrode; a second main electrode; and a first sub-electrode disposed between the first main electrode and the second main electrode. The first sub-electrode electrically connects to the first main electrode and the second main electrode. A first resistor is disposed between the first main electrode and the first sub-electrode, and a second resistor is disposed between the first sub-electrode and the second main electrode. In addition, the first main electrode, the second main electrode and the first sub-electrode are substantially parallel to each other.

Abstract: A display may have rows and columns of pixels that form an active area for displaying images. A display driver integrated circuit may provide multiplexed data signals to demultiplexer circuitry in the display. The demultiplexer circuitry may demultiplex the data signals and provide the demultiplexed data signals to the pixels on data lines. Gate lines may control the loading of the data signals into the pixels. The display may have a length dimension and a width dimension that is shorter than the length dimension. The data lines may extend parallel to the width dimension and the gate lines may extend parallel to the length dimension such that there are more data lines than gate lines in the display. A notch that is free of pixels may extend into the active area. Data lines extending parallel to the width dimension of the display may be routed around the notch.

Abstract: A source driver includes a gamma voltage generator to generate gamma voltages having mutually different voltage levels, a digital-to-analog converter to generate a data voltage corresponding to a grayscale value using the gamma voltages, an output buffer unit to output the data voltage, and a chopping controller to generate a chopping control signal, and to provide the chopping control signal to the output buffer unit. The output buffer unit includes an amplifier connected to an output terminal of the digital-to-analog converter, and a chopping circuit to periodically change a polarity of an offset of the amplifier in response to the chopping control signal. The chopping controller is to change a slew rate of the chopping control signal.

Abstract: An object is to provide a technique capable of increasing a display quality of a liquid crystal display device. A liquid crystal display device includes a liquid crystal panel including a liquid crystal layer with a liquid crystal, an electrode applying voltage to the liquid crystal, and a pair of polarization plates sandwiching the liquid crystal layer. A first voltage is applied to a liquid crystal in a local area in the liquid crystal panel when a transmissivity of the local area is set to a predetermined local minimum value, and a second voltage is applied to a liquid crystal in a remaining area other than the local area in the liquid crystal panel when the transmissivity of the remaining area is set to a predetermined local minimum value. The first voltage is different from the second voltage.

Abstract: It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.

Abstract: According to one embodiment, a display device includes an insulating substrate, a first insulating film, terminal portions and a pattern. The first insulating film covers the insulating substrate. The terminal portions are disposed on the first insulating film. The pattern is between the insulating substrate and the first insulating film. The pattern is formed by a semiconductor or a light-shielding material, and the pattern is covered with the first insulating film. The pattern is located just under a first terminal and a second terminal of the terminal portions.

Abstract: A method of driving a display by communicating with a controller through a first channel and a second channel includes; generating recovery data from a signal received through the first channel during a frame data period, detecting a vertical blank period between frame data periods, checking a training trigger event history during the vertical blank period, and during the vertical blank period, transmitting a training request direct to the first channel through the second channel when there is a training trigger event history.

Abstract: A display device includes a display panel, a first connection circuit board, a second connection circuit board, and a sealing member. The display panel may include an insulation layer, a first pad, and a second pad. A distance between a top surface of the insulation layer and a bottom surface of the second connection circuit board may be substantially the same as that between the top surface of the insulation layer and a top surface of the first connection circuit board.

Abstract: A gate driver and a display device using the same are disclosed. The gate driver includes a plurality of stages connected in a cascade connection manner, and each of the stages include a clock input configured to receive a shift clock signal, a first output terminal, and a second output terminal. Each of the stages generates a first output voltage that is transmitted to another stage through the first output terminal and a second output voltage that is supplied to a gate line of a display panel through the second output terminal. Each of the stages includes a first diode connected between the clock input and the first output terminal.

Abstract: A display device includes: first and second dots arranged on a first horizontal line in a first direction, each of the first and second dots including first to fourth pixels; a switch unit configured to selectively couple first to fourth output lines respectively to the first to fourth pixels of each of the first and second dots, in response to a first control signal and a second control signal; and a data driver configured to supply data voltages to the first to fourth output lines in a time-sharing manner. The data driver may include: a data processor configured to generate data signals corresponding to the first to fourth output lines; and first to fourth digital-to-analog converters (DACs) configured to convert the data signals into the data voltages. Each of the first to fourth DACs may be supplied with a corresponding one of first to fourth gamma voltages.

Abstract: A driving circuit, a driving method and a driving apparatus, wherein the driving circuit includes: a driving signal generation sub-circuit; a plurality of first signal lines, configured to receive the driving signal generated from the driving signal generation sub-circuit; a plurality of second signal lines, configured to output the driving signal to the plurality of pixels in the display panel; a switch sub-circuit, set between the plurality of first signal lines and the plurality of second signal lines, and configured to selectively connect a part of the plurality of second signal lines or the plurality of first signal lines and the plurality of second signal lines; and a control sub-circuit, configured to control turn-on or turn-off of the switch sub-circuit, so that the plurality of pixels of the display panel are driven in a first mode or in a second mode.

Abstract: A gate driving circuit includes a plurality of stages. Adjacent two stages from among the plurality of stages constitute a stage pair. The adjacent two stages in the stage pair include switching elements connected with each other. When a carry signal of an N-th stage in the stage pair has a defect, the N-th stage is configured to output a carry signal of an (N+1)-th stage in the stage pair. N is a positive integer. When a defect has occurred at a carry signal of a stage in a stage pair, the carry signal of the stage having the defect may be repaired by a carry signal of another stage in the stage pair.

Abstract: A display device comprises: a panel comprising a pixel array; a data driver for outputting video data signals to the panel; and a latch part for receiving the video data signals from the data driver and outputting the received video data signals to the pixel array. With this configuration, the number of data drive ICs of the data driver can be reduced while maintaining the panel driving frequency.

Abstract: A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

Abstract: A shift register unit, a driving method, a gate driving circuit and a display device are provided. The shift register unit includes: a starting circuit configured to control, under control of a first clock signal input terminal, turning on or off coupling between a first node and a starting voltage input terminal; a first capacitor circuit, having a first terminal being coupled to a second clock signal input terminal, and a second terminal being coupled to the first node; a first node control circuit configured to control, under control of a third node, turning on or off coupling between the first node and a first level input terminal; a potential control circuit configured to control, under control of the first node, turning on or off coupling between the second node and a second level input terminal; a second capacitor circuit; a second node control circuit; an output circuit; and a third node control circuit.

Abstract: The invention provides a semiconductor device and a shift register, in which low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire. One of a source and a drain of the third transistor is connected to a second wire, the other of the source and the drain thereof is connected to the gate electrode of the second transistor, and a gate electrode thereof is connected to a fourth wire.

Abstract: The present invention teaches a Gate Driver on Array (GOA) circuit for a display panel. The GOA circuit includes a first dummy GOA unit and/or a second dummy GOA unit not connecting scan lines of the display panel's active area, and normal GOA units connecting scan lines of the active area. The normal GOA units are cascaded into a chain. The first dummy GOA unit is cascaded to a first normal GOA unit of the chain and/or the second dummy GOA unit is cascaded to a last normal GOA unit of the chain. A start signal of the display panel's vertical scanning as a cascaded signal is input into the first dummy GOA unit and/or the second dummy GOA unit. The GOA circuit excludes the line of afterimage from the active area, thereby allowing the fast black frame insertion after abnormal shutdown.

Abstract: The disclosure discloses a shift register, a gate drive circuit, a driving method thereof, and a display device, and the shift register includes: an input sub-circuit, an output sub-circuit, and an output control sub-circuit, where the input sub-circuit is configured to provide a signal of a first reference voltage signal terminal to a pull-up node under control of an input signal terminal; the output sub-circuit is configured to provide a signal of a clock signal terminal to a first signal output terminal under control of a potential of the pull-up node; and the output control sub-circuit is configured to provide a signal of the first signal output terminal to a second signal output terminal under joint control of an output control signal terminal, a third reference voltage signal terminal, and a fourth reference voltage signal terminal.

Abstract: Systems, apparatuses and methods may provide for an electronic spine and one or more digital pages removably attached to the electronic spine, wherein the one or more digital pages include a first side with a first flexible display and a second side with a second flexible display. In one example, the system may further include a magnetic interface, wherein the digital page is removably attached to the electronic spine via the magnetic interface.

Abstract: Some embodiments of the present disclosure provide a shift register and a method of driving the same, a gate driving circuit, and a display device. The shift register includes a first input sub-circuit for outputting a voltage on a first control voltage terminal to a pull-up node under control of a first signal input terminal; n output sub-circuits for outputting signal from output clock signal terminals to signal output terminals in sequence under control of the pull-up node; a first pull-down control sub-circuit for outputting a voltage on the first control voltage terminal to a pull-down node under control of a first clock signal terminal; a second pull-down control sub-circuit for pulling down a voltage on the pull-down node to a first voltage under control of the pull-up node; and a pull-down sub-circuit for pulling down a voltage on the pull-up node to the first voltage under control of the pull-down node.

Abstract: A matrix-array detector includes an array of pixels that are sensitive to a physical effect and arranged in a matrix along rows and down columns, each pixel generating a signal according to the physical effect; row conductors, each allowing the pixels of one row to be driven; driver modules delivering selection signals to the row conductors, the driver modules being configured to deliver signals according to either of two levels, one being a high level allowing one of the rows of pixels to be selected and the other being a low level not allowing it to be selected. The detector further comprises impedance modules that are connected to each of the row conductors and configured to decrease the impedance of each row conductor and to keep the impedance of each row conductor low in a phase of reading the array of pixels as long as the corresponding selection signal is at the low level, the impedance modules being separate from the driver modules.

Abstract: A stage and a scan driver including the same for supplying a scan signal using a stage formed of P-type transistors to prevent output of an unwanted noise in a period where the scan signal is not supplied.

Abstract: This display device is provided with: a plurality of pixels (3); a plurality of source lines (SL); a source drive circuit (12a); and a plurality of switches (40, 41). The plurality of pixels are arranged in a matrix, and form a display region (10a) in which an image is displayed. The plurality of source lines (SL) are wired in the row direction of the pixel matrix on the display region, and connected to the respective pixels. The source drive circuit has a plurality of signal lines (PL) through which signals supplied to the respective pixels via the source lines are outputted. The switches are provided between the source lines and the signal lines. More than one of the source lines are wired to the pixels in the same row in the matrix. The source lines (SLe, SLo) for pixels in the same row and one of the signal lines of the source drive circuit, are connected via the switches.

Abstract: An organic light emitting display device including: a display panel including a plurality of pixels; a gate driver including a plurality of stage groups each including at least one stage providing a gate signal to the pixels; a timing controller providing a first stage initiation signal or a second stage initiation signal to the at least one stage; and a first stage initiation line and a second stage initiation line transmitting the first stage initiation signal and the second stage initiation signal from the timing controller to the gate driver.

Abstract: A driving method and a driving device of a display panel, and a display device are provided, wherein, the driving method of the display panel comprises steps of: turning on gates of transistors of an Nth row of pixels at a first rising edge moment of a clock signal; charging the Nth row of pixels according to a data signal; turning on gates of transistors of an (N+1)th row of pixels before a second rising edge moment of the clock signal; charging the (N+1)th row of pixels according to the data signal; wherein the second rising edge moment follows after the first rising edge moment and neighbors the first rising edge moment, where N is a positive integer.

Abstract: A shift register unit and a method for driving the same, a gate driving circuit, and a display apparatus are disclosed. The shift register unit includes: an input circuit configured to transmit an input signal to a pull-up node; an output circuit configured to transmit a clock signal to an output signal terminal under control of a voltage at the pull-up node; a first reset circuit configured to reset the pull-up node to a first level under control of a first reset signal; a first pull-down control circuit configured to control levels at the pull-up node and the output signal terminal under control of a first control signal; and a first voltage control circuit electrically connected to a second control signal terminal, and configured to control a voltage signal waveform at the first pull-down node under control of a second control signal.

Abstract: An array substrate, a touch display panel and a touch display device are provided. In the array substrate, the number of inverters in a second buffer unit is smaller than the number of inverters in a first buffer unit, or a size of an inverter in the second buffer unit is smaller than a size of an inverter in the first buffer unit, or the number of inverters in the second buffer unit is smaller than the number of inverters in the first buffer unit and the size of the inverter in the second buffer unit is smaller than the size of the inverter in the first buffer unit.

Abstract: A gate driver on array (GOA) circuit and a thin film transistor (TFT) substrate are provided. The GOA circuit includes a pull-up control module, a pull-up module, a pull-down module, a pull-down maintaining module, and a switch module. The switch module is configured to be turned off after a preset time delay when the pull-up module outputs a current-level scan signal at a high potential. The bootstrap module is configured to maintain a pull-up control signal at a high potential within the preset time delay of the switch module, and when the switch module is turned off, the bootstrap module cuts off a connection with the current-level scan signal.

Abstract: A shift register unit, a gate driving circuit, a display device and a driving method are disclosed. The shift register unit includes an input circuit, a first reset circuit, an output circuit, and a node control circuit. The input circuit is configured to control a level of a first node in response to an input signal; the first reset circuit is configured to reset the first node in response to the first reset signal; the output circuit is configured to output a driving signal to an output terminal under control of the level of the first node; and the node control circuit is configured to control a level of a second node in response to the driving signal.

Abstract: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

Abstract: A driving method and a driving device of a display panel are provided. The driving method includes: controlling a timing controller to output a start signal to a level shifter; configuring a parameter of a register of the level shifter; and controlling the level shifter to generate a drive signal according to the parameter upon receiving the start signal, and outputting the drive signal to a first drive circuit.

Abstract: An electronic device may include a display such as a light-emitting diode display. The electronic device may be a head-mounted device that provides a virtual reality or augmented reality environment to a user. To reduce artifacts in the display, a display may be operable in both a normal scanning mode and a partial scanning mode. In the normal scanning mode, every row of the display may be enabled to emit light in each frame. In the partial scanning mode, only a subset of the rows of the display may be enabled to emit light in each frame. The display may have a higher refresh rate in the partial scanning mode than in the normal scanning mode. To ensure uniform transistor stress across the display, the scanning driver for the display may scan the disabled rows in the partial scanning mode even though the rows will not be used to emit light.

Abstract: A display apparatus is disclosed, which is capable of reducing the number of output channels in a column driving circuit. The display apparatus comprises a display portion including pixels arranged in pixel areas defined by row line groups and column line groups, a row driving circuit configured to supply a scan control signal to the row line groups, a column driving circuit configured to sequentially output a data signal every horizontal period, and a data distribution circuit configured to sequentially supply the data signal, which is sequentially output from each of output channels of the column driving circuit, to the column line groups in accordance with a data selection signal, wherein a period of the data selection signal is longer than 1 horizontal period.

Abstract: A GOA circuit and a display panel are provided. The GOA circuit could reduce the number of transistors electrically connected to the first node in the GOA circuit. Thus, the number of the current leakage paths is also reduced. In addition, the GOA circuit could real-time compensate the pixel circuit in the blank time period and thus raise the stability of the GOA circuit.

Abstract: According to an aspect, a display device includes: a plurality of sub-pixels, each sub-pixel including at least one memory; a setting circuit configured to select either a first mode in which a still image is displayed or a second mode in which a moving image is displayed; and a switching circuit configured to switch coupling between the sub-pixels and the memories according to the selection made by the setting circuit. The first mode is a mode in which each of the sub-pixels is coupled to one of the at least one memory included in the sub-pixel, and the second mode is a mode including a time period in which at least one of the sub-pixels is coupled to the at least one memory included in another of the sub-pixels.

Abstract: A shift register and a corresponding driving method, a gate driving circuit and a display device, the shift registers includes an input and reset circuit, a first output circuit, a second output circuit, a first pull-down circuit and a second pull-down circuit; the first output circuit and the second output circuit output gate driving signals according to potentials at a first clock signal terminal and a second clock signal terminal respectively, the first pull-down circuit and the second pull-down circuit reset potentials at a pull up node, a first output terminal and a second output terminal according to potentials at a first pull-down node a second pull-down node respectively.

Abstract: A shift register unit cascaded in a gate drive circuit, wherein the shift register unit comprises: a control circuit configured to output a control signal, at least two buffer circuits coupled to the control circuit, each of the at least two buffer circuits configured to output scan signal to a gate line. As such, the scan signals output from the at least two buffer circuits would be synchronized so that the gate lines respectively coupled to the two buffer circuits can be scanned simultaneously.

Abstract: A method implemented in an electronic device is provided. The method includes determining at least one update of content of at least one application, wherein the at least one update is associated with an activity related to the content accessed by a user, generating at least one statement corresponding to the at least one update of the content of the at least one application in accordance with the activity related to the content.