Abstract: A display device includes a substrate on which a display area including a plurality of pixels and a non-display area surrounding the display area are defined, a first voltage line disposed on the substrate in the non-display area, where the first voltage line provides a first voltage to the pixels, a second voltage line disposed on the substrate in the non-display area, where the second voltage line provides a second voltage to the pixels, and a first demux circuit area and a second demux circuit area disposed on the substrate in the non-display area, where the first demux circuit area and the second demux circuit area transmit data signals to the pixels. The first voltage line passes an area between the first demux circuit area and the second demux circuit area.

Abstract: A shift-register unit, a grid driving circuit and a displaying device, which relates to the technical field of displaying. In the present disclosure, the oxide-semiconductor layers of the oxide thin-film transistors may be delimited into regions according to the total channel widths and the channel lengths required by the oxide thin-film transistors in the shift-register unit, wherein the sum of the widths of the independent semiconductor branches obtained by the delimitation is equal to the required total channel width. Accordingly, one oxide thin-film transistor can realize the required total channel width by using the one or more semiconductor branches, to ensure the normal operation of the oxide thin-film transistor, whereby the oxide-semiconductor layers of the different oxide thin-film transistors can be configured differently, to realize the purpose of reducing the border frame of the displaying device.

Abstract: An electronic display includes an active area including multiple pixels. The electronic display also includes a first row driver set including a first column of row drivers and a second column of row drivers. A first active row driver in the first column of row drivers drives a first portion of the multiple pixels, and a first spare row driver in the second column of row drivers is in an inactive state. The electronic display also includes a second row driver set including a third column of row drivers and a fourth column of row drivers. A third active row driver in the third column of row drivers drives a second portion of the multiple pixels, and a second spare row driver in the fourth column of row drivers is inactive.

Abstract: A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.

Abstract: Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

Abstract: To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

Abstract: To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

Abstract: The present application provides a distributed system on panel (SOP) display panel and a display system. The distributed SOP display panel includes a plurality of display modules and a plurality of functional modules. Each display module includes a plurality of display units. The functional modules include first functional modules and a second functional module. The first functional modules are electrically connected to the display units in adjacent display modules, the second functional module is electrically connected to the plurality of display modules, in order to alleviate a technical problem of improper layout of system functions of a conventional SOP display device.

Abstract: A display device includes a substrate including a display area and a non-display area, a pixel unit provided in the display area, and including a first pixel column including a plurality of pixels and a second pixel column including a plurality of pixels displaying a different color from a color of the first pixel column, and data lines which are respectively connected to the first pixel column and the second pixel column, and respectively apply data signals to the first pixel column and the second pixel column, wherein the data line connected to the first pixel column includes sub lines and the data line connected to the second pixel column includes sub lines.

Abstract: A display substrate and manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, and a shift register unit and a first clock signal line that are on the base substrate, the first clock signal line extends along a first direction on the base substrate and is configured to provide a first clock signal to the shift register unit, the shift register unit includes an input circuit, an output circuit, a first control circuit and an output control circuit, and the first control circuit includes a first control switch and a second control switch, an active layer of the first control switch and an active layer of the second control switch are a continuous control semiconductor layer, the control semiconductor layer extends along the first direction.

Abstract: A display device includes: active stages each include a scan output circuit outputting a scan clock signal to a first output terminal and a carry output circuit outputting a carry clock signal to a second output terminal, when a voltage of a first node is at a logic high level. The scan output circuit and carry output circuit output a scan signal of a turn-off level to the first output terminal when a voltage of a second node or a carry signal is at a logic high level. An interval between pulses of the carry clock signal generated during one frame period is the same, and at least two of intervals between pulses of the scan clock signal generated during the one frame period are different from each other.

Abstract: This application provides a signal decoding method, a decoding circuit, and a stylus. In one example, a to-be-measured signal is sampled to obtain a plurality of sampled signals. The to-be-measured signal is a modulation signal that carries an interference signal. The modulation signal is sent by a touch panel of a terminal device. At least two edge signals in the to-be-measured signal are determined based on the plurality of sampled signals. The to-be-measured signal is decoded based on the at least two edge signals to obtain the modulation signal.

Abstract: Disclosed are a driving circuit, a driving method and a display device. The driving circuit (100) comprises: a data writing circuit (101), configured to, under control of a first scanning signal received at the first scanning signal end, write a data signal received at the data signal end into the first node; a control circuit (102), configured to, under control of a third scanning signal received at the third scanning signal end (SCAN3), write a data signal received by the first node (N1) into the second node (N2); and a driving sub-circuit (103), configured to, under control of a data signal received at the second node (N2), use a driving voltage received at the driving voltage end (Vdd) to drive the light-emitting component 104.

Abstract: The disclosure includes: first level shift part generating a voltage signal by converting an input voltage signal into amplitude between first negative and positive polarity power supply voltages; second level shift part generating a first polarity voltage signal by converting the voltage signal into amplitude between a reference and the first positive polarity power supply voltage; third level shift part outputting a first-polarity high voltage signal by converting the first polarity voltage signal into amplitude between a higher second positive polarity power supply voltage and the reference; fourth level shift part generating a second polarity voltage signal by converting the voltage signal into amplitude between the reference and the first negative polarity power supply voltage; and fifth level shift part outputting a second-polarity high voltage signal by converting the second polarity voltage signal into amplitude between a lower second negative polarity power supply voltage and the reference.

Abstract: The present disclosure relates to a gate driving circuit and a display device including the gate driving circuit, and more particularly, to a gate driving circuit having a reduced size and a display device including the gate driving circuit. The gate driving circuit comprises a plurality of dummy stage circuits and stage circuits, which supply gate signals to each gate line and comprise a Q node, a QH node, and a QB node. A gate signal output circuit included in each of the stage circuits can output first to j-th gate signals based on first to j-th scan clock signals or a first low voltage according to the voltage level of the Q node or the voltage level of the QB node.

Abstract: An array substrate and a testing method thereof are provided. The array substrate includes a gate driving circuit, a plurality of clock signal lines and a plurality of testing terminals, wherein a number of the clock signal lines is greater than a number of the testing terminals; the plurality of clock signal lines are connected to the gate driving circuit and the plurality of testing terminals, and at least two clock signal lines are connected to a same testing terminal; and the plurality of testing terminals are configured to connect to a testing device.

Abstract: Provided is a display panel. The display panel includes multiple scanning lines, a gate driver circuit, and a timing controller. The timing controller is configured to: receive multiple data enable signals, generate a gate control signal, and provide the gate control signal for the gate driver circuit. The gate control signal includes a start signal, a first clock signal and a second clock signal. The multiple data enable signals are only within the active cycle. The timing controller is configured to generate a rising edge and a falling edge of the start signal within a time interval formed by a rising edge and a falling edge of a first data enable signal in the Nth frame cycle.

Abstract: Disclosed are a memory device and a read/write method of the memory device and, more particularly, a memory device and a read/write method of the memory device capable of reducing power consumption of a display device by reducing a storage operation and an output operation of the memory device for a plurality of pieces of pixel data.

Abstract: A shift register, a gate driving circuit, and a display panel. The shift register includes a first input module, a second input module, a first output module, a second output module, a first output control module, and a second output control module, where the first input module is configured to control the potential of a first node according to a first start signal and a first clock signal, the second input module is configured to control the potential of a second node according to a second start signal and the first clock signal, and the second start signal and the first start signal have opposite potentials; the first output module includes a first coupling unit configured to couple the potential of a third node according to the potential of a first output terminal in the case where the potential of the first output terminal jumps.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a blanking input circuit, a blanking control circuit, a blanking coupling circuit, a display input circuit and an output circuit. The blanking input circuit is configured to charge a control node in response to a compensation selection control signal, and to maintain a level of the control node. The blanking control circuit is configured to charge a first node, by using a first clock signal, under control of the level of the control node and the first clock signal. The blanking coupling circuit is electrically connected to the control node, and is configured to control, by coupling, the level of the control node in response to the first clock signal.

Abstract: An embodiment is able to improve the pure-color brightness ratio by compensating for image data of a current pixel on the basis of a result of comparing image data of a current pixel with image data of a previous pixel.

Abstract: The circuit includes a first transistor; a second transistor whose first terminal is connected to a gate of the first transistor for setting the potential of the gate of the first transistor to a level at which the first transistor is turned on; a third transistor for setting the potential of a gate of the second transistor to a level at which the second transistor is turned on and bringing the gate of the second transistor into a floating state; and a fourth transistor for setting the potential of the gate of the second transistor to a level at which the second transistor is turned off. With such a configuration, a potential difference between the gate and a source of the second transistor can be kept at a level higher than the threshold voltage of the second transistor, so that operation speed can be improved.

Abstract: A shift-register unit includes a first circuit including a first input circuit coupled via a first node to a first output circuit, and a second circuit including a second input circuit coupled via a second node to a second output circuit. The first input circuit is configured to control a voltage level of the first node in response to a first input signal. The first output circuit is configured to output a shift-register signal and a first output signal in response to the voltage level of the first node. The second input circuit is configured to control a voltage level of the second node in response to the first input signal. The second output circuit is configured to output a second output signal in response to the voltage level of the second node. The first input circuit and the second input circuit have a same circuit structure.

Abstract: Methods of manufacturing a wound monitoring and/or therapy apparatus and/or wound dressing include positioning electronic components and connections in regions of a substrate that are not configured to be perforated. The methods can also include following a set of rules for positioning the components as well as positioning and shaping the connections based on the constraints stemming from, among other things, the positioning of the perforations on the substrate and with the goal of maintaining acceptable levels of signal integrity. The methods further include manufacturing a multi-layered substrate. Wound monitoring and/or therapy apparatus manufactured using such methods are also disclosed.

Abstract: A display device includes gate lines and pixels connected to the gate lines. The display device includes stages which provide gate signals to the gate lines, and first and second gate power lines which transfer a first voltage to the stages. A first stage among the stages includes a first node controller and a first output unit. The first node controller is connected to the second gate power line, and controls a voltage of a first control node. The first output unit is connected to the first gate power line, and outputs a first voltage of the first gate power line as a gate signal in response to a voltage of the first control node.

Abstract: In a semiconductor device and a shift register, low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire.

Abstract: A control method for an electronic apparatus includes obtaining a first positional relationship between eyes of a user and a first display area and a second positional relationship between eyes of the user and a second display area and setting a brightness value of the first display area and a brightness value of the second display area at least based on the first positional relationship and the second positional relationship. The electronic apparatus includes the first display area. The user includes a subject that uses the electronic apparatus. The first display area and the second display area move relative to each other.

Abstract: A data processing method of a driving circuit and a driving circuit are provided. Wherein, the data processing method of the driving circuit can include obtaining a timing parameter, performing data processing based on the timing parameter and obtaining a first processing result, decoding the first processing result according to a preset reference voltage and obtaining a second processing result, and amplifying the second processing result, and outputting an amplified second processing result.

Abstract: A shift register circuit includes a denoising control sub-circuit and a denoising sub-circuit. The denoting control sub-circuit is configured to generate an alternating voltage signal according to a voltage of a first voltage terminal and a signal of a second clock signal terminal in response to a signal of a first clock signal terminal, to rectify the alternating voltage signal and then to output a signal to a first denoising control node, so that the voltage of the first denoting control node is maintained to be a voltage that enables the denoising sub-circuit to be turned on. The denoting sub-circuit is configured to denoise a scan signal output terminal in response to a voltage of the first denoising control node being the voltage that enables the denoising sub-circuit to be turned on.

Abstract: A display device includes a display panel including a first area and a second area spaced apart from the first area in a plan view. The display panel includes a first base layer including a first pixel, a second base layer facing the first base layer and including a second pixel, a first signal line electrically connected to the first pixel of the first area, a second signal line electrically connected to the second pixel of the second area, and a connection line electrically connecting the first signal line and the second signal line.

Abstract: The present application discloses a display panel and a display device. The display panel includes a non-display region and a gate driver on array (GOA) unit region in the non-display region. The GOA unit region includes multi-level GOA units arranged in multiple columns, thereby improving a space limitation problem associated with arranging a plurality of GOA units in a display panel while the display panel achieves high resolution.

Abstract: To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

Abstract: An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 ?m is 1 aA or less.

Abstract: Provided are a display driving method and apparatus, and a display panel and an electronic device. The display driving method is applied to a display panel, and comprises: determining a first charging duration of each display point on the basis of a preset position, in a display panel, of each display point in the display panel; generating, according to the first charging duration of each display point, a display control signal corresponding to each display point; and adjusting a second charging duration of each display point according to the display control signal.

Abstract: A display device includes: a first pixel connected to a first data line and a first scan line; a second pixel connected to the first data line and a second scan line; a first scan driver connected to a first scan start line and the first scan line; and a second scan driver connected to a second scan start line and the second scan line. In a first frame period, the second scan start line is to be suppled with a second scan start signal having a turn-on level, after a first period elapses after a first scan start signal having a turn-on level is supplied to the first scan start line. In a second frame period, a difference between a time at which the first scan start signal having the turn-on level is supplied and a time at which the second scan start signal having the turn-on level is supplied corresponds to a second period. The second period is shorter than the first period.

Abstract: A display device includes a display panel including a plurality of pixels, a plurality of data lines extending in a first direction and coupled to the plurality of pixels, a plurality of first scan lines extending in a second direction different from the first direction and coupled to the plurality of pixels, and a plurality of second scan lines extending in the first direction and coupled to the plurality of first scan lines, a data driver which provides data voltages to the plurality of pixels through the plurality of data lines, and a scan driver which sequentially provides a scan signal to the plurality of pixels on a row-by-row basis through the plurality of second scan lines and the plurality of first scan lines. The data driver and the scan driver are implemented with a data-scan integration chip which outputs the data voltages and the scan signal.

Abstract: A shift register comprises a first shift register unit and a second shift register unit. The first shift register unit comprises a first input circuit connected to a first input terminal and a first pull-up node, a first output circuit connected to the first pull-up node, a first output terminal and a first clock terminal, and a first pull-down circuit. The second shift register unit comprises a second input circuit connected to a second input terminal and a second pull-up node, and a second output circuit connected to the second pull-up node, a second output terminal and a second clock signal.

Abstract: An electronic device including a substrate, a first signal line, a second signal line, a third signal line, a first level shifter, and a second level shifter is provided. The first signal line, the second signal line, and the third signal line are disposed on the substrate. Each of the first signal line, the second signal line, and the third signal line has two endpoints. The second signal line is disposed between the first signal line and the third signal line. The first level shifter is coupled to the first signal line and the third signal line. The second level shifter is coupled to the second signal line. The first level shifter is coupled to the two endpoints of the first signal line and the two endpoints of the third signal line. The second level shifter is coupled to the two endpoints of the second signal line.

Abstract: The present application provides a display driving circuit and a display device, wherein the display driving circuit comprises a plurality of driving units, each of the driving units comprises a plurality of stages of sub driving units, each of the driving units is electrically connected to one of independent triggering units, and the sub driving units in the driving units are electrically connected stage by stage; and the display device comprises the display driving circuit. A structure of the driving circuit can realize partitioned work of the driving circuit, and can reduce power consumption of the display device when the display driving circuit is applied in the display device.

Abstract: Provided are an array substrate and a display device. The array substrate includes: a base substrate including a display area and a peripheral area including a first peripheral area and a corner area; plurality of sub-pixels, data lines, and power lines at the display area; a plurality of control signal lines, data signal input lines, a multiplexing circuit and a first power bus which are at the first peripheral area and the corner area; a plurality of control signal connecting lines electrically connected to the control signal lines, at least partially overlapping with the data signal input lines, and located between the first power bus and the display area; and a plurality of control signal input lines electrically connected to the control signal connecting lines, at least partially overlapping with the first power bus, and on one side of the control signal connecting lines away from the display area.

Abstract: A display device includes a display panel including a first array of light emitters having a first spacing in a first emission region of the display panel and a second array of light emitters having a second spacing in a second emission region of the display panel. The second spacing is distinct from the first spacing. The display device includes an optical filter including a first filter region and a second filter region. The first filter region changes distribution of first light from the first array of light emitters impinging on the first filter region so that the first light has a first distribution after passing through the first filter region. The second filter region changes distribution of second light from the second array of light emitters impinging on the second filter region so that the second light has a second distribution after passing through the second filter region.

Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, a gate driving circuit, power lines, a first signal line group, and a second signal line group. The gate driving circuit includes cascaded shift register units; the power lines are configured to provide power signals to the shift register units; the first signal line group includes at least one clock signal line, and the clock signal line is configured to provide a clock signal to the shift register units; the second signal line group includes a trigger signal line, and the trigger signal line is configured to provide a trigger signal to a first-stage shift register unit; and the gate driving circuit includes at least one transistor, and an extending direction of a channel of the transistor is parallel to an extending direction of the one clock signal line.

Abstract: Provided are a display panel and a display apparatus. The display panel includes a driving array layer having functional layers and insulation layers. The driving array layer includes a first transistor, a second transistor, a first capacitor including a first plate and a second plate, and a second capacitor including a third plate and a fourth plate. An active layer of the first transistor contains silicon, and an active layer of the second transistor contains oxide semiconductor. The first plate and the second plate are located in two of the functional layers, respectively, and the third plate and the fourth plate are located in two of the functional layers, respectively.

Abstract: A display device includes a display panel including pixels, and data lines and gate lines connected to the pixels, a timing controller configured to output source driving bit information and gate driving bit information through an intra-interface signal, a source driver configured to generate data driving signal based on the source driving bit information and to supply the data driving signal to the data lines, and a gate driver configured to generate a gate driving signal based on the gate driving bit information and to supply the gate driving signal to the gate lines, wherein the intra-interface signal is configured with predetermined data transmission units and includes both the source driving bit information and the gate driving bit information every 1 data transmission unit.

Abstract: A gate driver may include: a controller to charge and discharge a first control node that pulls up an output voltage and a second control node that pulls down the output voltage; a first output unit having a first pull-up transistor to apply a gate high voltage to an output node in response to a charging voltage of the first control node, and a first pull-down transistor to apply a gate low voltage to the output node in response to a charging voltage of the second control node; and a switch unit to change a current path between a first output node and a first power line to which a high potential voltage is applied or a second power line to which a first clock signal is applied according to a carry signal transmitted from a previous signal transmission unit and a voltage level of the second control node.

Abstract: An electro-optic display having a plurality of pixels is driven from a first image to a second image using a first drive scheme, and then from the second image to a third image using a second drive scheme different from the first drive scheme and having at least one impulse differential gray level having an impulse potential different from the corresponding gray level in the first drive scheme. Each pixel which is in an impulse differential gray level in the second image is driven from the second image to the third image using a modified version of the second drive scheme which reduces its impulse differential The subsequent transition from the third image to a fourth image is also conducted using the modified second drive scheme but after a limited number of transitions using the modified second drive scheme, all subsequent transitions are conducted using the unmodified second drive scheme.

Abstract: A gate driver and a display device including the gate driver are discussed. The gate driver in one example includes a shift register configured to control charging and discharging of a Q node and a QB node, and i output buffers sequentially connected to the shift register, where i is a natural number of at least 2. Each output buffer is configured to output a gate signal to a corresponding gate line in response to a voltage of the Q node and a voltage of the QB node. The gate driver further includes a dummy output buffer connected to the last stage of the shift register and configured to output a dummy signal to a dummy line in response to the voltage of the Q node.

Abstract: The present invention provides a touch panel and the touch detection circuit thereof, which comprise a gate driving circuit, a source driving circuit, and a detection circuit. The gate driving circuit is coupled to a plurality of gate lines of a display panel, outputs a plurality of gate signals to the plurality of gate lines, and controls state transition of the plurality of gate signals. The source driving circuit is coupled to a plurality of source lines of the display panel. The detection circuit is coupled to the plurality of source lines or to a portion of the plurality of source lines. The detection circuit detects the levels of the plurality of signals on the coupled source lines when the gate signals change states and generates a plurality of detection signals.

Abstract: A display substrate, including: a display region and a peripheral region located on the periphery of the display region. A scan driver circuit is disposed in the peripheral region. A plurality of sub-pixels, and a plurality of first signal lines that are connected to the scan driver circuit and extend in a first direction, are disposed in the display region. The display region includes: a substrate, and a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer that are sequentially disposed on the substrate. The third conductive layer comprises: a plurality of first signal lines, and first electrodes and second electrodes of a plurality of transistors. An insulating layer between the third conductive layer and the first conductive layer is provided with first via holes.

Abstract: A flat panel display device formed in a pentile structure is provided, which includes a pixel portion and a lighting tester. The pixel portion includes a first pixel column, a second pixel column and a third pixel column. In the first pixel column, first pixels for displaying a first color and second pixels for displaying a second color are alternately arranged in a direction the data lines. In the second pixel column, first and second pixels arranged in reverse order of the first pixel column in a direction parallel to the data lines. In the third pixel column, third pixels for displaying a third color are arranged in a direction parallel to the data lines. The lighting tester applies a first voltage to the first pixel column and applies a second voltage to the second pixel column during a first time period. The lighting tester applies the second voltage to the first pixel column and applies the first voltage to the second pixel column during a second time period.