Abstract: A digital-to-analog converter having a structure that converter may decrease an effect of a mismatch between elements and decrease a quantity of the elements. The digital-to-analog converter includes a multiplexer configured to output a first voltage or a second voltage corresponding to an input bit as an input voltage and a recursive switched circuit configured to alternately receive the input voltage and a reference voltage and to output an average value of the input voltage and the reference voltage as an output voltage.

Abstract: A multiplexer applied to a display device includes: a plurality of switching units, electrically coupled to a data driver and a plurality of pixel units, where the switching units are adapted to receive a plurality of input display data signals output by the data driver, and the switching units output a plurality of output display data signals to the electrically coupled pixel units, where each of the switching units includes a plurality of switch units, configuration locations of the switch units in each of the switching units are the same as, and some of the switch units configured at a same configuration location in the different switching units are electrically coupled to different control signal lines and have different wiring lengths, where the wiring lengths are distances between the switch units and the control signal lines.

Abstract: The present disclosure provides a display panel and a display device, including: a display area and a non-display area, that the display area includes data lines, and the non-display area includes a binding area including conductive pads; a multiplex distribution circuit including demultiplexers, that each of demultiplexers includes: one input terminal, N output terminals, N first switching elements; and connecting lines. The one input terminal and the conductive pads are electrically connected, and the N output terminals are electrically connected to the data lines. First electrodes of the N first switching elements are electrically connected to the one input terminal, and second electrodes are electrically connected to the N output terminals. The demultiplexers include at least one first demultiplexer. The N First switching elements of the at least one first demultiplexer are disposed in the display area. N is a positive integer and N?2.

Abstract: A plurality of cascade-connected register circuits which comprises a bidirectional shift register include a top register circuit, a bottom register circuit, and main register circuits. The register circuit has an output circuit which outputs one of four-phase clock pulses when a voltage of a first node is an active level; a second output circuit which outputs a non-active level when a voltage of a second node is the active level; a second node reset circuit which sets the second node to the non-active level when a voltage of a second node reset terminal is the active level. The forward scan signal sets the voltage of the first node of the top register circuit to the active level, and the forward scan signal sets the voltage of the second node reset terminal of the bottom register circuit to the active level.

Abstract: A display control method, a feedback circuit, a display device and an IC circuit are disclosed. The display control method is applied in the display device. The display control method includes: selecting two adjacent common electrodes of a plurality of common electrodes; collecting voltages of the two adjacent common electrodes; comparing the collected voltages of the two adjacent common electrodes and obtaining a comparison result. When the comparison result meets a preset condition, the method further includes compensating input voltages of pixel units in two pixel unit rows of a plurality of pixel unit rows corresponding to the two adjacent common electrodes based on the comparison result, so as to enable the voltages applied on the pixel units in the two pixel unit rows to be consistent.

Abstract: Disclosed herein are a display device capable of reducing the number of transmission lines by enabling a master circuit to perform communication with a plurality of slave circuits, which utilize different interfaces, through a common transmission line in a time divisional manner, and an interface method thereof. A timing controller uses a common transmission line of a gamma voltage generator and a level shifter which respectively utilize first and second interfaces and perform communication using the first and second interfaces in a time divisional manner.

Abstract: The present disclosure provides a touch display panel or a touch display device and a gate driving circuit included in the touch display panel or the touch display device. The gate driving circuit includes a shift register group outputting scan signals during a display driving period and a dummy shift register group outputting dummy signal during a touch driving period. The gate driving circuit transmits a signal output immediately before a display driving period before a touch driving period ends, through dummy shift registers during the touch driving period such that the signal is used for outputting a first scan signal in the next display driving period. Accordingly, it is possible to prevent output reduction of a scan signal at the boundary between the touch driving period and the display driving period and prevent defect in an image due to the output reduction.

Abstract: An object is to provide a display device that performs accurate display. A circuit is formed using a transistor that includes an oxide semiconductor and has a low off-state current. A precharge circuit or an inspection circuit is formed in addition to a pixel circuit. The off-state current is low because the oxide semiconductor is used. Thus, it is not likely that a signal or voltage is leaked in the precharge circuit or the inspection circuit to cause defective display. As a result, a display device that performs accurate display can be provided.

Abstract: A display device includes: a display panel; a gate driving circuit formed at a side of the display panel; and a driving module outputting a plurality of clock signals to the gate driving circuit, wherein the driving module receives a feedback signal from the gate driving circuit and adjusts the clock signals according to the feedback signal.

Abstract: One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.

Abstract: Provided are a display panel and a display device. The display panel includes a drive chip and a switching device, and the drive chip includes a digital interface inputting terminal, a positive driving voltage inputting terminal and a negative driving voltage inputting terminal, and the switching device includes a first switching inputting terminal, a second switching inputting terminal, a third switching inputting terminal, a switching control terminal, a first switching outputting terminal corresponding to the first switching inputting terminal, a second switching outputting terminal corresponding to the second switching inputting terminal and a third switching outputting terminal corresponding to the third switching inputting terminal. The first switching inputting terminal, the second switching inputting terminal, the third switching inputting terminal and the switching control terminal are configured to be electrically connected to a main circuit board.

Abstract: A stage circuit includes an output circuit configured to supply, to a first output terminal, a first clock signal supplied to a second input terminal or to supply a voltage of a second power source supplied to a second power input terminal, in response to voltages of a first node and a second node, an input circuit configured to control voltages of a third node and a fourth node in response to a shift pulse or a gate start pulse supplied to a first input terminal, a third clock signal supplied to a third input terminal, and a fourth clock signal supplied to a fourth input terminal, and a first driver configured to control the voltages of the first and second nodes in response to both the third clock signal and the voltages of the third and fourth nodes.

Abstract: A display device includes a plurality of pixels, a plurality of gate lines, a timing controller, and a gate driver. The gate lines are electrically coupled to the pixels. The timing controller provides an initial pulse signal. The gate driver is electrically coupled to the timing controller and the gate lines and receives the initial pulse signal. The gate driver receives the initial pulse signal with a high level and outputs a plurality of gate signals to the gate lines during a period which is longer than half of a frame of the display device, in response to a scan frequency of the display device changing from a first frequency to a second frequency, where the first frequency is higher than the second frequency.

Abstract: An electro-phoretic display apparatus including an electro-phoretic display panel and a driving circuit is provided. The electro-phoretic display panel includes a display area and a border area. The driving circuit is coupled to the electro-phoretic display panel. The driving circuit is configured to drive the display area to display an image frame according to a first voltage. The driving circuit drives the border area to maintain displaying a white border or a black border according to a second voltage.

Abstract: Each of pixels includes: a transparent upper electrode covering at least a part of the first region and at least a part of the second region; a reflective lower electrode disposed in the second region; a light-emitting film disposed between the transparent upper electrode and the reflective lower electrode, the light-emitting film being configured to emit light in response to supplied electric current; a thin film transistor disposed lower than the reflective lower electrode in the second region, the thin film transistor having a channel made of a transparent oxide; and a transparent low-resistive film that is made of the transparent oxide and interconnects the power-source potential supply line and the transparent upper electrode, the transparent low-resistive film being separate from an oxide film that is made of the transparent oxide and includes the channel and having a resistance lower than a resistance of the channel.

Abstract: A crystal driving circuit comprising a circuit input node and a circuit output node, a high power amplifier having a power consumption of more than 100 ?W, a low power amplifier comprising a power consumption less than 10 ?W, the circuit being arranged to selectively isolate the high power amplifier and associated load capacitance from the circuit input node and the circuit output node.

Abstract: A shift register, a method for driving the same, a gate driver circuit, and a display device are provided. The shift register includes an input circuit, a reset circuit, a first control circuit, a first output circuit, and a second output circuit, where the first output circuit includes two output channels, where one channel is that under the joint control of signals of a first clock signal terminal and a first node, a signal of a first clock signal terminal is provided to a drive signal output terminal of the shift register, and the other channel is that under the joint control of signals of the second clock signal terminal and the first node, a signal of a second clock signal terminal is provided to the drive signal output terminal.

Abstract: A display device has a substrate for disposing a display area having an array of pixels, and control circuits having shift registers and latches to provide image data and timing control signals to the pixels. The control circuits have signal lines electrically connected to a connection cable to receive therefrom data signals indicative of the image data and timing pulses indicative of the timing control signals. The connection cable is also configured to provide reference signals to the shift registers and latches in the control circuits. The data signals are digital signals having an amplitude range greater than the amplitude range of the reference signals. No driver IC is disposed on the substrate to process analog signals. Each of the pixels has three sub-pixels and each of the color sub-pixels has three color sub-areas configured to receive timing control signals from a different scan line.

Abstract: A display device includes a display substrate including a display area and a pad region, a first pad portion including a plurality of first pad terminals, the plurality of first pad terminals being arranged in a first direction, and a printed circuit board (PCB) including a base film and a second pad portion. The second pad is electrically connected to the first pad portion. The second pad portion includes a plurality of second pad terminals electrically connected to the plurality of first pad terminals, and a plurality of first test lines. The plurality of second pad terminals includes a plurality of sub-pad terminals. One of the plurality of first lines is connected to a first sub-pad terminal of the plurality of sub-pad terminals, and a second sub-pad terminal of the plurality of sub-pad terminals is not connected to any of the plurality of first lines.

Abstract: The present disclosure relates to a liquid crystal display, a display panel and a reference voltage control method of a display panel and a reference voltage control device for a display panel. The reference voltage control method of a display panel includes acquiring a refreshing frequency of the display panel; invoking a reference voltage database according to the refreshing frequency, to acquire reference voltage data corresponding to the refreshing frequency; generating a reference voltage adjusting signal for adjusting a reference voltage signal fixedly output by the display panel according to the reference voltage data; and synthesizing the reference voltage adjusting signal and the reference voltage signal fixedly output by the display panel to generate a reference voltage synthesis signal, and outputting the reference voltage synthesis signal to a reference voltage signal input terminal of the display panel.

Abstract: An array substrate and a driving method thereof and a liquid crystal panel are provided. The array substrate includes plural scan lines, plural data lines and plural sub-pixels that are arranged in a matrix and are defined by the scan lines and the data lines, in which every two rows of sub-pixels constitutes a unit, sub-pixels in the same column and in the same unit are connected to the same data line, sub-pixels in the same column but respectively in two adjacent units are connected to different data lines, two adjacent columns of sub-pixels in the same unit are connected to different data lines, and two scan lines in the same unit are conducted at the same time.

Abstract: An electro-optical device includes first and second signal lines extending in directions intersecting each other on a component substrate, a pixel area including a pixel electrode disposed in correspondence with an intersection of the first and second signal lines, a signal output circuit disposed outside the pixel area and outputs a driving signal to the first signal line, and a connection wiring connecting the signal output circuit and the first signal line. An outer peripheral edge of the pixel area has a curved portion or a bent portion in a portion facing the signal output circuit, and the signal output circuit includes a plurality of circuit blocks arranged along the curved portion or the bent portion of the portion facing the signal output circuit with deviated between adjacent circuit blocks in the direction of extension of the first signal line and/or the direction of extension of the second signal line.

Abstract: A display apparatus includes a display panel which displays an image, and includes a gate line and a data line, a gate driving part which outputs a gate signal to the gate line and a data driving part which outputs a data signal to the data line, and selectively outputs first color gamma data, second color gamma data and third color gamma data in response to a selection signal, and generates the data signal using the first color gamma data, the second color gamma data and the third color gamma data.

Abstract: A drive circuit, a display panel, a display device and a drive method. The drive circuit includes a plurality of shift registers; a first switch circuit connected with the shift registers, which is configured to selectively output output signals of the shift registers or a first voltage based on a first control signal and a second control signal; and a second switch circuit connected with the shift registers, which is configured to selectively output the output signals of the shift registers or the first voltage based on a third control signal and a fourth control signal. A set of shift registers can simultaneously or individually drive two display regions.

Abstract: According to one embodiment, a liquid crystal display device includes pixel electrodes including unit pixel electrodes, pixel circuits which apply a white-display voltage or a black-display voltage to the unit pixel electrodes, first and second polarity voltage lines being used in applying the white-display voltage and the black-display voltage to the pixel circuits, and a control unit which divides at least polarity voltage lines into a plurality of blocks, and supplies a polarity inversion signal to the polarity voltage lines to be subjected to polarity inversion driving, in units of one block, wherein the pixel circuits each include a pixel switch, a memory, and a polarity select unit which selects a voltage signal on one of the first and second polarity voltage lines in response to a binary image signal held by the memory.

Abstract: A display device includes a display panel which includes a plurality of gate lines and a plurality of pixels, where each of the pixels is connected to a corresponding gate line among the gate lines, and a gate driving circuit which includes a stage that applies a gate signal to at least one of the gate lines. The gate signal includes a high period in which the gate signal has a high voltage and a low period in which the gate signal has a low voltage having a level less than a level of the high voltage, and the low period includes a falling period in which the low voltage falls to a second level from a first level which is greater than the second level.

Abstract: A data driving circuit of a flat panel display device is disclosed. Digital-to-analog controllers of a digital-to-analog conversion unit and amplifiers of an output amplification unit are configured to be equal in number and a switch array is arranged between the output amplification unit and a pad. Therefore, a settling time can be secured and distortion of a data signal can be prevented by maintaining settling during a next horizontal period and performing overlapping driving.

Abstract: Disclosed is a GOA circuit, and the GOA circuit includes multiple stages of GOA unit circuits. Each stage of GOA unit circuit includes a first scan module, a first clock input module, a first signal port control module, a third signal port control module, a first output module, a first global signal operation module, a second scan module, a second clock input module, a second signal port control module, a fourth signal port control signal module, a second output module and a second global signal operation module. The afterimages that may occur when a power supply of a crystal display panel is abnormally cut off can be avoided by using the disclosed GOA circuit, and thus the user experience can be improved.

Abstract: A driving circuit of a display device includes first and second line buffers, first and second output circuits, and a filtering process circuit. The first line buffer stores a first present data signal and outputs a first previous line data signal, and the second line buffer stores a second present data signal and outputs a second previous line data signal. The filtering process circuit alternately outputs the present data signal as one of the first present data signal and the second present data signal, and outputs a first filtered data signal and a second filtered data signal. The first output circuit receives the first filtered data signal and drives a first data line group of a plurality of data lines, and the second output circuit receives the second filtered data signal and drives a second data line group of the data lines.

Abstract: A mobile device control method for displaying information on a touch screen of a mobile device is provided. The method includes determining a type of a cover for the mobile device, the cover having a screen projection portion, detecting a gesture or a trigger, and displaying a screen corresponding to a current state of the mobile device on the touch screen depending on the type of the cover, in response to the detection of the gesture or the trigger.

Abstract: A display panel and an electroluminescent display using the same are disclosed. The display panel includes a first data line charged with a first data signal, a second data line charged with a second data signal, a first subpixel connected to the first data line, a second subpixel connected to the second data line, a gate line commonly connected to the first and second subpixels and simultaneously supplying a gate signal to the first and second subpixels, a demultiplexer connecting an output terminal of a data driver to the first data line using MUX switch elements and then connecting the output terminal to the second data line using the MUX switch elements, and a switch array supplying a reference voltage to the second data line when the output terminal is connected to the first data line by the demultiplexer using REF switch elements.

Abstract: An electrooptical device includes a plurality of pixels that are disposed corresponding to each of intersection positions at which a plurality of scanning lines and a plurality of data lines intersect with each other, and each of which includes a light emitting element which emits light by a driving current; and a control circuit that performs a control such that the light emitting element emits light or does not emit light. The control circuit causes the light emitting element to transition between a light-emitting state and a non-light-emitting state, in a transition period, in a case where the light emitting element of each pixel corresponding to the unselected scanning line is to transition between a light-emitting state and a non-light-emitting state.

Abstract: A shift register circuit, a driving method, a gate driving circuit and a display device are provided. The shift register circuit includes an input circuit; a reset circuit; a first pull-up node control circuit; a second pull-up node control circuit for controlling the pull-up node to couple to the second level output terminal when a potential of the pull-down node is a first level; a first pull-down node control circuit for controlling the potential of the pull-down node being the first level in the reset phase; a second pull-down node control circuit for controlling the pull-down node to couple to the second level output terminal when the potential of the pull-up node is the first level; a gate drive signal output circuit; and a carry signal output circuit for controlling the carry signal output terminal to output a carry signal under control of the pull-up node and the pull-down node.

Abstract: Provided is a display panel, comprising a substrate, and a display area and a non-display area formed on the substrate; wherein metal traces are disposed on one side of the non-display area to electrically connect an integrated circuit in the non-display area with an external structure integrated with a driver integrated circuit (IC) for driving the integrated circuit in the non-display area by the external structure integrated with the driver IC to illuminate the display area. By bonding the driver IC to the external structure, the area ratio of the bonding area of the driver IC on the display panel is reduced to increase the screen occupation ratio of the display panel.

Abstract: An array substrate, a display panel, a method for driving the display panel and a liquid crystal display device are disclosed. The array substrate includes: N rows of pixel units; N scan lines, each of the N scan lines corresponding to one of the N rows of pixel units, a switch is connected between two adjacent scan lines of the N scan lines; a scanning drive circuit configured to supply a scan activation signal to each of the N scan lines to activate a scan operation; a switch drive circuit configured to supply a drive signal to the switch between ith scan line and (i+1)th scan line in response to the scan activation signal of the ith scan line, to turn on the switch between the ith scan line and the (i+1)th scan line such that the ith scan line is in electrical communication with the (i+1)th scan line.

Abstract: To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension.

Abstract: A gate driving circuit provided in embodiments of the present disclosure includes: N-stage gate driving units, the gate driving unit at each stage of the N-stage gate driving units having a first voltage terminal and a clock signal terminal, and a first transmission path being formed between the first voltage terminal and the clock signal terminal, wherein at each stage, the first transmission path of the gate driving unit is conductive when the gate driving unit is in a non-operative state; and a first voltage line connected to the first voltage terminal of the gate driving unit at each stage. A preset voltage received by a clock signal terminal of a gate driving unit that is in a non-operative state is transmitted to the first voltage line through the first transmission path of the gate driving unit.

Abstract: There are provided a shift register unit and a driving method thereof. The shift register unit includes: an input circuit, whose first terminal receives an input signal of the shift register unit, and second terminal is connected to a pull-up node, the input circuit being configured to output the input signal to the pull-up node; an output circuit, whose first terminal is connected to a clock signal terminal, second terminal is connected to the pull-up node, third terminal is connected to an output terminal of the shift register unit, the output circuit being configured to output a signal of the clock signal terminal to the output terminal under the control of the pull-up node; a pull-up node control circuit, and the pull-up node control circuit being configured to discharge the pull-up node through third power supply voltage terminal under the control of a first power supply voltage terminal.

Abstract: A display device may includes: a substrate including a pixel area and a peripheral area; pixels provided in the pixel area of the substrate, each of the pixels including a light-emitting element provided with a pixel electrode; scan lines and data lines coupled to the pixels; a power line configured to supply driving power to the light-emitting elements, and extending in one direction; and an initialization power line configured to supply initialization power to the light-emitting elements. The power line and the initialization power line may be provided on different layers. The initialization power line may include: first conductive lines extending in a direction oblique to the scan lines and the data lines; and conductive lines intersecting the first conductive lines. The first and second conductive lines may be disposed in areas between the pixel electrodes of adjacent light-emitting elements.

Abstract: The present disclosure provides a scan-driving circuit and a display device. The scan-driving circuit includes a plurality of series-connecting scan-driving units including an input circuit generating a pull-up control signal and a pull-down control signal; a latch circuit pulling up or pulling down a pull-up control signal point; a processing circuit generating a current scan-driving signal, a cache circuit driving an output of a current scan-driving signal, and a reset circuit clearing the pull-up control signal point. Therefore, it improves driving flexibility and reduces driving power consumption of the display device, and is beneficial to narrow bezel design.

Abstract: A driving circuit, an array substrate and a display device are provided. The driving circuit includes a plurality of cascaded shift registers. Each shift register includes a plurality of transistors and at least one capacitor, and a channel width-to-length ratio of at least one transistor is determined by a preset number of pixels in a pixel row driven by the corresponding shift register.

Abstract: A display device includes first and second pixels. The first pixel includes a first high pixel connected to an i-th gate line and a j-th data line and a first low pixel connected to an (i+1)-th gate line and the j-th data line. The second pixel includes a second high pixel connected to the i-th gate line and a (j+1)-th data line and a second low pixel connected to the (i+1)-th gate line and the (j+1)-th data line.

Abstract: In a shift register, a pre-charge unit is configured to receive a first input signal and output a pre-charge signal to a first node, a pull-up unit is configured to output a scan signal to a second node, and a pull-down unit is configured to receive a pull-down control signal. The pull-down control signal switches from a disable voltage to an enable voltage before the display panel switches from a non-display status to a display status.

Abstract: A display device has a display area in a non-rectangular shape, and in the display device, a plurality of rectangular-shaped pixels are arranged in the display area and a non-display area, each pixel being composed of a plurality of subpixels that correspond to a plurality of colors, respectively. The display device includes a brightness value adjustment unit that, during image display, adjusts a brightness value of a boundary pixel that is partially included in the display area and is partially included in the non-display area, in such a manner that the brightness value of the boundary pixel is between a brightness value of a pixel whose subpixels are all included in the non-display area and a brightness value of a pixel that is adjacent to the boundary pixel and whose subpixels are all included in the display area.

Abstract: A thin-film transistor array including an insulating substrate, gate lines formed on the insulating substrate, source lines formed on the insulating substrate, and transistors each being formed on the insulating substrate at a position corresponding to a respective intersection of the gate lines and the source lines, and formed in a matrix including pixels in rows and columns, each of the transistors including a gate electrode connected to each of the gate lines, a source electrode connected to each of the source lines, a drain electrode, and a pixel electrode connected to the drain electrode. Each of the source lines is connected to a column of pixels, and each of the gate lines includes a first portion connected to a predetermined number of pixels in a row and a second portion connected to pixels in an adjacent row.

Abstract: There is provided in the present disclosure a shift register unit, comprising: an input circuit, whose first terminal is connected to a power supply terminal, second terminal is connected to an input terminal, and third terminal is connected to a pull-up node, the input circuit being configured to input a power supply signal input by the power supply terminal to the pull-up node under the control of an input signal; a pull-up control circuit, whose first terminal is connected to a first clock signal terminal, and second terminal is connected to the pull-up node, the pull-up control circuit being configured to control a potential of the pull-up node according to a first clock signal input by the first clock signal terminal; a pull-up circuit, whose first terminal is connected to a first signal terminal, second terminal is connected to an output terminal, third terminal is connected to the pull-up node.

Abstract: An array substrate for lowering switch frequency of drive polarity in data lines is described. The source driver charges a first sub-pixel group having the first polarity on pixel regions wherein the first sub-pixel group comprises a plurality of sub-pixels with the positive polarity disposed in the interlaced positions between data line and the scan lines. The source driver charges a second sub-pixel group having the second polarity on the pixel regions wherein the second sub-pixel group comprises a plurality of sub-pixels with the negative polarity disposed in the interlaced positions between data line and the scan lines. The first sub-pixel group is greater than each pixel region and the second sub-pixel group is greater than each pixel region so that either the switch frequency for driving the first sub-pixel group or the second sub-pixel group is lower than that of the two sub-pixels in the pixel region.

Abstract: It is an object to decrease the number of transistors connected to a capacitor. In a structure, a capacitor and one transistor are included, one electrode of the capacitor is connected to a wiring, and the other electrode of the capacitor is connected to a gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor through the capacitor. Then, on/off of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated. In this manner, deterioration of the transistor can be suppressed.

Abstract: The present disclosure provides a transparent display panel, its manufacturing method and a transparent display device. The transparent display panel comprises a first substrate, a second substrate, a third substrate, a first liquid crystal layer and a plurality of first pixels located between the first substrate and the second substrate; and a second liquid crystal layer and a plurality of second pixels located between the second substrate and the third substrate; the first liquid crystal layer has a larger refractive index than the first substrate and the second substrate; and the second liquid crystal layer has a larger refractive index than the third substrate and the second substrate; after applying voltages to one first pixel and one second pixel, a long axial direction of the first liquid crystal molecules is not parallel to a long axial direction of the second liquid crystal molecules; and at least part of a side surface of the transparent display panel is a light-entering surface.

Abstract: An active matrix substrate is provided with a gate driver including a multi-stage shift register (240). Each stage of the multi-stage shift register has a plurality of oxide semiconductor TFTs, a first input terminal for receiving a set signal, a second input terminal for receiving a clock signal, a third input terminal for receiving a clear signal, and an output terminal for outputting a gate output signal to one of the plurality of gate bus lines. The clock signal and the clear signal have the same high-level potential, and the clock signal and the clear signal have the same low-level potential. The plurality of oxide semiconductor TFTs include a first TFT (101) having a back-gate structure. The main gate electrode of the first TFT (101) is coupled to the third input terminal or a negative power supply voltage VSS. The back-gate electrode of the first TFT has a potential set to a positive power supply voltage VDD or a ground potential GND.