Method and program for designing semiconductor integrated circuit
The method of designing a semiconductor integrated circuit of the embodiment is characterized in: reading from a memory unit a fundamental property value of a cell constituting a semiconductor integrated circuit in a case in which a variation of a property value is not taken into consideration, and reading from a memory unit variation coefficients of the property value of the cell corresponding to a dimension of a transistor constituting the cell; and performing a static timing analysis on the semiconductor integrated circuit by using the read variation coefficients and fundamental property value.
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This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-296098 filed on Oct. 31, 2006, the entire contents of which are incorporated herein by reference.
BACKGROUND1. Field
The embodiment relates to a method of designing and producing semiconductor integrated circuits, and particularly to a method and a program designing semiconductor integrated circuits.
2. Description of the Related Art
Static timing analysis (STA) is conventionally employed as a method of verifying timing in semiconductor integrated circuits (such as an LSI circuit). In STA, timing in circuits is verified on the basis of delay times that are respectively assigned to cells that constitute a semiconductor integrated circuit.
Factors that affect variations in signal propagation delay in LSIs include (1) variations in process properties such as transistor properties of transistors that constitute LSIs, (2) variations in power supply voltage caused by a voltage drop inside the chip, and (3) variations in temperature inside the chip. These variations are called on-chip variations (OCV). It is very difficult to strictly take each OCV into consideration, and in conventional STA, variations of property values (such as delay time, for example) are expressed by uniform variation coefficients for respective cells that constitute LSIs in order to verify whether or not the semiconductor integrated circuit can operate normally. As the uniform variation coefficients, relatively large values are used to cover all the cases.
However, as processes have been miniaturized in recent years, variations in dimensions such as the gate width of transistors that constitute a cell become greater, and the timing margins on designs become greater when uniform variation coefficients are used for each cell, which is problematic in view of design.
Patent Document 1 discloses, as a conventional technique of timing analysis, a method of calculating a delay time; with this method timings can be efficiently verified by calculating a correction value for the variation coefficients on the basis of the function by which the propagation delay time can be approximated as the propagation delay time caused by variations in an actual chip in accordance with the number of cell stages in a signal path, and by calculating the propagation delay time while taking into consideration the corrected variation coefficients.
Patent Document 2 discloses, as another conventional technique, a timing analysis device that can perform accurate timing analysis by calculating the OCV coefficient that has been obtained by taking into consideration the number of cell stages on the basis of the idea that an increased number of cell stages reduces the range of variations of, for example, the delay time because the variations in the cell property are in accordance with the normal distribution.
However, even when these conventional techniques are used, there remains a problem that cannot be solved: the design has further difficulties due to variations in the transistor's dimensions (such as gate width) that will likely become greater as processes are miniaturized.
- Patent Document 1
- Republication of Patent No. WO2003/060776 “METHOD AND SYSTEM FOR CALCULATING DELAY TIME IN SEMICONDUCTOR INTEGRATED CIRCUIT”
- Patent Document 2
- Japanese Patent Application Publication No. 2005-122298 “DEVICE, METHOD, AND PROGRAM FOR ANALYZING TIMING”
The embodiment provides that a method of designing a semiconductor integrated circuit including, reading from a memory unit a fundamental property value of a cell constituting a semiconductor integrated circuit in a case in which variations of a property value are not taken into consideration, and a pair of variation coefficients indicating a variation range of the property value of the cell corresponding to one of the dimensions of a transistor constituting the cell, and performing a static timing analysis on the semiconductor integrated circuit in accordance with the read variation coefficients and the fundamental property value.
In step S1 of a method of designing a semiconductor integrated circuit, shown in
In step S6 of another method of designing a semiconductor integrated circuit, shown in
In the embodiment, it is possible that in step S1 shown in
A design program according to the embodiment causes a computer to execute the design of semiconductor integrated circuits, the design employing the methods described in
As described above, in the embodiment, a fundamental property value, such as a fundamental delay time of a cell when the variations are not taken into consideration, is multiplied by each of the variation coefficients corresponding to one of the dimensions such as the gate width of a transistor constituting the cell, and static timing analysis on the semiconductor integrated circuit is performed.
According to the embodiment, uniform variation coefficients are not used as variations of property values such as the delay time of a cell, and static timing analysis is performed by using the values of the appropriate variation coefficients corresponding to dimensions such as the gate width of the transistors constituting the cell, and thereby a semiconductor integrated circuit is designed. Accordingly, circuits can be designed with a smaller timing margin than that in the case when variation coefficients that are too large are used. Accordingly, it is possible to develop and design products that can sufficiently utilize the performance of transistors, e.g., products that requires a high operation speed.
Next, an example of a cell used for a design method according to the embodiment is explained before the design method for semiconductor integrated circuits according to the embodiment is explained.
In the embodiment, the design is explained of semiconductor integrated circuits with variations in the gate width of a transistor that constitutes a cell such as an inverter taken into consideration. However, processes in preparation phases are performed in which various libraries used in the development phases of a product are created before the actual development phase of the product is performed.
In
Library 2 stores the pair of data including the cell and the value of gate width W. For example, the values of the gate widths W of transistors constituting an inverter cell corresponding to the names of a plurality of inverter cells respectively constituted of transistors with different gate widths W are stored.
In library 3, data of variation coefficients with respect to the value of W is stored. As will be described, this data is stored in the form of a function that provides a value of the variation coefficient corresponding to the interval of a value of W. In other words, the value of the variation coefficient with respect to a plurality of inverter cells having different values of gate width W is obtained through actual measurement, a function providing a relationship between the gate width W and the variation coefficient is obtained in accordance with the measured value, and the equation expressing the function is stored in library 3.
In
In step S15, a property examination is made on a circuit constituted of the cells; specifically, dependence of the property on the gate width W of the transistor constituting the cell is examined. For example, the relationship between the gate width W and the frequency of the ring oscillator constituted of the respective inverter cells is obtained, and in step S16 the relational expression between a gate width W and a property such as a frequency is set, and the relational expression is stored in library 3. This property examination and relational expression will be described in
Specifically, the frequency observation is performed for ring oscillators 10a through 10n to which inverter cells constituted of the transistor having a gate width of, for example, W0 are connected in three stages. The same frequency observation is sequentially performed (step S25) from many ring oscillators having a configuration in which inverter cells are connected in three stages, the inverter cells constituted of a transistor having the gate width of, for example, W1, to many ring oscillators having a configuration in which inverter cells constituted of a transistor having a gate width W5 are connected in three stages.
For example, before the input into the inverter of the first stage in the ring oscillator 10a becomes H and the input into the inverter of the first stage again becomes H in, for example,
Oscillation frequency=1/{(gate delay time×stage number of gate)×2}
In the ring oscillation circuit consisting of the gate (inverter cell) of the (n+1) stages, the gate delay time is given by the equation below.
Gate delay time=1/{oscillation frequency×(2n+2)}
Next, in step S31, the fundamental delay time read process is executed In this process, the delay time of each cell for which variations are not taken into consideration is read from library 1, and fundamental delay time information 22 is created.
Next, in step S32, the process of calculating the delay time variation coefficients is executed. In this process, values of the gate width W of the transistors respectively constituting each cell (for example, cells A and B in
Next, in step S33, the process of calculating the delay times when taking variations into consideration is performed. In this process, delay time information 25 for which variations are taken into consideration is obtained by respectively multiplying the fundamental delay time, i.e., the values of the delay time of each cell when the variations are not taken into consideration, and each of the pair of delay time variation coefficients 23 corresponding to the value of the gate width W of the transistor constituting each cell.
The delay time information 25 for which variations are taken into consideration is used to perform the timing verification process in step S34. Specifically, the delay time information 25 for which variations are taken into consideration is relayed to an STA (Static Timing Analysis) tool 26, a static timing analysis is performed, and an STA result 27 is obtained. Then, if this STA result is satisfactory, the process proceeds to the next step. When this result is not satisfactory, the processes from, for example, the logical design/arrangement wiring process in step S30 are repeated as necessary.
Although in
Examples of data being relayed to the STA tool are explained by referring to
When the STA tool directly reads the fundamental delay time and the variation coefficients of the delay time as described above, the process in step S33 shown in
The effects of the embodiment will be explained by referring to
TPD1×m×(W4F−W1F)
where TPD0 represents the fundamental delay time.
Also, when obtaining the margin reduction amount at the low speed side, W1S of the upper limit value of the variation coefficients is used in conventional methods, and the margin reduction amount at the low-speed side is obtained by the equation below, which assumes that W4S is used in the embodiment.
TPD0×m×(W1S−W4S)
In the above, W4F is greater than W1F as values of the variation coefficients, and W1S is greater than W4S; accordingly, the values of the margin reduction amounts both at the high-speed side and the low-speed side are positive values. Accordingly, it is possible to reduce the timing margin in the design phase.
Additionally, when the variation coefficient W4 is used in a conventional method and the gate width in accordance with the cell that is to be actually used is W1, the timing margin in the design phase is insufficient, and by using the variation coefficient W1 in the embodiment, the insufficiency of the margin can be avoided.
In the above explanations, inverters are used for examples of functions of cells constituted of transistors. However, the functions of cells are not limited to inverters, and the embodiment can be applied to cells having any type of function.
The aforementioned embodiments allow the appropriate design of semiconductor integrated circuits and the development of a product that requires a higher operation speed by reducing timing margins on designs even when processes are miniaturized further and variations in the dimensions of transistors increase.
Other embodiments can be implemented as a semiconductor integrated circuit designed and produced using a method of designing a semiconductor integrated circuit according to any one of the above embodiments, and also can be implemented as a computer readable storage medium storing a program that causes a computer to execute a method of designing a semiconductor integrated circuit according to any one of the above embodiments.
Claims
1. A method of designing a semiconductor integrated circuit, comprising:
- using a computer, reading from a memory unit a fundamental property value of a cell constituting a semiconductor integrated circuit wherein variations of a property value are not taken into consideration for the fundamental property value, and a pair of variation coefficients among a plurality of pairs of variation coefficients wherein each pair in the plurality of pairs of variation coefficients is stored in the memory unit corresponding to one of a plurality of dimensions, each pair in the plurality of pairs of variation coefficients is constituted by an upper limit value of the variation coefficients and a lower limit value of the variation coefficients, the upper limit value and the lower limit value indicate a variation range of the property value, and the pair of variation coefficients to be read is one of the plurality of pairs of variation coefficients corresponding to a dimension of a transistor constituting the cell; and
- using the computer, performing a static timing analysis on the semiconductor integrated circuit in accordance with the read pair of variation coefficients and the fundamental property value,
- wherein the dimension of the transistor is a length or a width.
2. The method of designing a semiconductor integrated circuit according to claim 1, further comprising:
- using the computer, multiplying the upper limit value in the read pair of variation coefficients and the fundamental property value, and
- using the computer, multiplying the lower limit value in the read pair of variation coefficients and the fundamental property value, wherein
- the static timing analysis on the semiconductor integrated circuit is performed by the computer using property values based on the multiplications.
3. The method of designing a semiconductor integrated circuit according to claim 1, wherein:
- the property value of the cell is a delay time.
4. The method of designing a semiconductor integrated circuit according to claim 1, wherein:
- the dimension of the transistor is a gate width of the transistor.
5. A semiconductor integrated circuit designed and produced by using the method of designing a semiconductor integrated circuit according to claim 1.
6. A method of designing a semiconductor integrated circuit, comprising:
- using a computer, reading from a memory unit a fundamental property value of a cell constituting a semiconductor integrated circuit, and a pair of relational expressions constituted by a first relational expression that indicates relation between a dimension of a transistor constituting the cell and an upper limit of variation coefficients and a second relational expression that indicates relation between the dimension of the transistor and a lower limit of the variation coefficients;
- using the computer, calculating an upper limit value and a lower limit value of the variation coefficients of a property value of the cell by using the dimension of the transistor constituting the cell and the read pair of relational expressions; and
- using the computer, performing a static timing analysis on the semiconductor integrated circuit by using the calculated upper limit value, the calculated lower limit value, and the read fundamental property value,
- wherein the dimension of the transistor is a length or a width.
7. The method of designing a semiconductor integrated circuit according to claim 6, further comprising:
- using the computer, multiplying the calculated upper limit value and the read fundamental property value, and
- using the computer, multiplying the calculated lower limit value and the read fundamental property value, wherein
- the static timing analysis on the semiconductor integrated circuit is performed by the computer using property values based on the multiplications.
8. The method of designing a semiconductor integrated circuit according to claim 6, wherein:
- the read pair of relational expressions is a certain one pair in one or more pairs of functional expressions,
- each pair in the one or more pairs of functional expressions is stored in the memory unit corresponding to one of one or more intervals, and
- the certain one pair in the one or more functional expressions corresponds to a certain interval in which the dimension of the transistor constituting the cell is included.
9. The method of designing a semiconductor integrated circuit according to claim 6, wherein:
- the dimension of the transistor is a gate width of the transistor.
10. A non-transitory computer readable storage medium storing a semiconductor integrated circuit designing program, the program causing a computer to execute:
- reading from a memory unit a fundamental property value of a cell constituting a semiconductor integrated circuit wherein variations of a property value are not taken into consideration for the fundamental property value, and a pair of variation coefficients among a plurality of pairs of variation coefficients wherein each pair in the plurality of pairs of variation coefficients is stored in the memory unit corresponding to one of a plurality of dimensions, each pair in the plurality of pairs of variation coefficients is constituted by an upper limit value of the variation coefficients and a lower limit value of the variation coefficients, the upper limit value and the lower limit value indicate indicating a variation range of the property value, and the pair of variation coefficients to be read is one of the plurality of pairs of variation coefficients corresponding to a dimension of a transistor constituting the cell; and
- performing a static timing analysis on the semiconductor integrated circuit in accordance with the read pair of variation coefficients and the fundamental property value, wherein the dimension of the transistor is a length or a width.
11. A non-transitory computer readable storage medium storing a semiconductor integrated circuit designing program, the program causing a computer to execute:
- reading from a memory unit a fundamental property value of a cell constituting a semiconductor integrated circuit wherein variations of a property value are not taken into consideration for the fundamental property value, and a pair of variation coefficients among a plurality of pairs of variation coefficients wherein each pair in the plurality of pairs of variation coefficients is stored in the memory unit corresponding to one of a plurality of dimensions, each pair in the plurality of pairs of variation coefficients is constituted by an upper limit value of the variation coefficients and a lower limit value of the variation coefficients, the upper limit value and the lower limit value indicate a variation range of the property value, and the pair of variation coefficients to be read is one of the plurality of pairs of variation coefficients corresponding to a dimension of a transistor constituting the cell;
- multiplying the upper limit value in the read pair of variation coefficients and the fundamental property value;
- multiplying the lower limit value in the read pair of variation coefficients and the fundamental property value; and
- performing a static timing analysis on the semiconductor integrated circuit in accordance with property values based on the multiplications,
- wherein the dimension of the transistor is a length or a width.
5365463 | November 15, 1994 | Donath et al. |
7131082 | October 31, 2006 | Tsukiyama et al. |
7219320 | May 15, 2007 | Kawano et al. |
7401307 | July 15, 2008 | Foreman et al. |
7487475 | February 3, 2009 | Kriplani et al. |
7669154 | February 23, 2010 | Hosono |
7673260 | March 2, 2010 | Chen et al. |
20040254776 | December 16, 2004 | Andou |
20050081171 | April 14, 2005 | Kawano et al. |
9-311877 | December 1997 | JP |
2001-168200 | June 2001 | JP |
2005-79162 | March 2005 | JP |
2005-122298 | May 2005 | JP |
03/060776 | July 2003 | WO |
- Japanese Notice of Rejection Grounds, Partial English-language translation, mailed Jan. 18, 2011 for corresponding Japanese Patent Application No. 2006-296098.
Type: Grant
Filed: Oct 1, 2007
Date of Patent: Apr 19, 2011
Patent Publication Number: 20080104562
Assignee: Fujitsu Semiconductor Limited (Yokohama)
Inventor: Shigenori Ichinose (Kawasaki)
Primary Examiner: Leigh Marie Garbowski
Attorney: Fujitsu Patent Center
Application Number: 11/865,242
International Classification: G06F 17/50 (20060101);