Semiconductor assemblies with multi-level substrates and associated methods of manufacturing
Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a substrate for carrying a semiconductor die includes a first routing level, a second routing level, and a conductive via between the first and second routing levels. The conductive via has a first end proximate the first routing level and a second end proximate the second routing level. The first routing level includes a terminal and a first trace between the terminal and the first end of the conductive via. The second routing level includes a second trace between the second end of the conductive via and a ball site. The terminal of the first routing level and the ball site of the second routing level are both accessible for electrical connections from the same side of the substrate.
Latest MICRON TECHNOLOGY, INC. Patents:
- Integrated Assemblies Having Transistor Body Regions Coupled to Carrier-Sink-Structures; and Methods of Forming Integrated Assemblies
- System Error Correction Code (ECC) Circuitry Routing
- Memory Circuitry And Methods Used In Forming Memory Circuitry
- SEMICONDUCTOR DEVICE CAPABLE OF SWITCHING OPERATION VOLTAGE
- Memory Circuitry And Methods Used In Forming Memory Circuitry
This application is a divisional of U.S. application Ser. No. 13/206,321 filed Aug. 9, 2011, now U.S. Pat. No. 8,637,987, which is incorporated herein by reference.
TECHNICAL FIELDThe present disclosure is related to semiconductor assemblies with multi-level substrates and associated methods of manufacturing.
BACKGROUNDBoard-on-chip (“BOC”) techniques have been used for packaging high speed memory components.
Over the course of time, manufacturers have made dies smaller and smaller to meet user demands. As the semiconductor dies 104 have become smaller, the number of ball pads 120 and the traces 112 required on the substrate 102 has increased such that the large ball pads 120 can interfere with routes of the traces 112. One conventional solution for dealing with this problem is to use aggressive design rules and wire bond profiles to decrease the sizes of all features on both the semiconductor die 102 and the substrate 104. However, such a conventional technique is still limited due to the number of ball pads 120 that are typically required.
Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. Typical semiconductor assemblies or packages include microelectronic circuits or components, thin-film recording heads, data storage elements, microfluidic devices, and other components manufactured on microelectronic substrates. Substrates can include semiconductor pieces (e.g., doped silicon wafers or gallium arsenide wafers), non-conductive pieces (e.g., various ceramic substrates), or conductive pieces. A person skilled in the relevant art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference to
In the illustrated embodiment, the substrate 202 can include a first side 202a proximate the semiconductor die 204, a second side 202b opposite the first side 202a, and an opening 218 extending through the substrate 202 from the first side 202a to the second side 202b. The opening 218 exposes a connection region 210 on the semiconductor die 204. The connection region includes bond sites 219 that are connected internally to structures within the semiconductor die 204. In other embodiments, the opening 218 may be omitted, for example, if the semiconductor die 204 is coupled to the substrate 202 in a flip-chip configuration.
As shown in
As shown in
As shown in
Preparing the second routing level 202 can include stripping the first conductive material 304a from the first side 301a of a separate non-conductive core 301 (stage 312) and patterning and selectively removing the second conductive material 304b to form a targeted pattern for the second routing level 212 (stage 314). As shown in
As shown in
Even though the wirebonds 214 are shown in
As shown in
One feature of several of the foregoing embodiments is that the traces and the ball sites to which they connect can be located on different levels or strata of the substrate. This arrangement allows the designer greater flexibility when selecting the routes for the traces and the locations for the ball sites because the routes can follow paths that are independent of the ball site locations, so long as individual routes can be connected to the corresponding ball sites with vias, as described above. Another feature of at least some embodiments is that the ball sites on one level of the substrate and portions of the traces on another level of the substrate are both accessible from the same side or face of the substrate. This arrangement allows the manufacturer to access the traces for wirebonding and access the ball sites for depositing solder balls or other electrical couplers with the substrate facing the same direction.
From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the technology. For example, in an embodiment shown in
Certain aspects of the technology described in the context of particular embodiments may be combined or eliminated in other embodiments. Further, while advantages associated with certain embodiments of the invention have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages to fall within the scope of the invention. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein.
Claims
1. A method of processing a substrate for carrying a semiconductor die, comprising:
- forming a first routing level carried by a first non-conductive core;
- forming a second routing level carried by a second non-conductive core;
- generally aligning the first routing level relative to the second routing level;
- fixing the first and second non-conductive cores relative to each other; and
- forming a conductive via between the first and second routing levels, the conductive via having a first end proximate the first routing level and a second end proximate the second routing level, wherein: the first routing level includes a terminal and a first trace electrically connected between the terminal and the first end of the conductive via; the second routing level includes a second trace electrically connected between the second end of the conductive via and a ball site; and the terminal and the ball site are both accessible from the same side of the substrate.
2. The method of claim 1 wherein forming the first routing level includes stripping a first conductive material from a first side of the first non-conductive core and patterning and selectively removing a portion of a second conductive material on a second side of the first non-conductive core.
3. The method of claim 1 wherein forming the second routing level includes:
- stripping a first conductive material from a first side of the second non-conductive core and patterning and selectively removing a portion of a second conductive material on a second side of the second non-conductive core; and
- depositing a solder mask on the patterned second conductive material.
4. The method of claim 1 wherein forming the second routing level includes:
- stripping a first conductive material from a first side of the second non-conductive core and patterning and selectively removing a portion of a second conductive material on a second side of the second non-conductive core;
- depositing a solder mask on the patterned second conductive material; and
- forming ball pads on the second conductive material by selectively removing the deposited solder mask.
5. The method of claim 1, further comprising forming an opening through the first and second routing levels after generally aligning the first routing level to the second routing level.
6. The method of claim 1 wherein forming the first routing level includes forming a first routing level that does not include any ball site.
7. The method of claim 1 wherein fixing the first and second non-conductive cores relative to each other includes bonding the first routing level to a surface of the second non-conductive core.
8. The method of claim 1 wherein the first and second routing levels and the conductive via form a substrate, and wherein the method further comprises:
- mounting a semiconductor die to the substrate; and
- electrically connecting the semiconductor die to the first routing level.
9. The method of claim 1 wherein the first and second routing levels and the conductive via form a substrate, and wherein the method further comprises:
- forming an opening in the substrate;
- mounting a semiconductor die to the substrate; and
- wirebonding the semiconductor die to the terminal of the first routing level first routing level by passing a bond wire through the opening.
10. A method of processing a substrate for carrying a semiconductor die, comprising:
- forming a first routing level on a first substrate;
- forming a second routing level on a second substrate different than the first substrate;
- generally aligning the first routing level relative to the second routing level;
- joining the first and second substrates before forming a conductive via; and
- forming the conductive via between the first and second routing levels, the conductive via having a first end proximate the first routing level and a second end proximate the second routing level, wherein: the first routing level includes a terminal and a first trace electrically connected between the terminal and the first end of the conductive via; the second routing level includes a second trace electrically connected between the second end of the conductive via and a ball site; and the terminal and a ball site are both accessible from the same side of the substrate.
11. The method of claim 10, further comprising:
- mounting a semiconductor die to the first substrate;
- forming an opening at least through the first substrate, the opening exposing a bond site on the semiconductor die; and
- electrically connecting the bond site to the terminal through the opening.
12. The method of claim 11, further comprising attaching a wirebond to the terminal and a solder ball to the pad.
13. The method of claim 10, further comprising forming an opening through the second substrate before joining the first and second substrates, wherein the terminal is exposed through the opening.
14. The method of claim 10, further comprising:
- forming a first opening through the second substrate before joining the first and second substrates; and
- forming a second opening through the first substrate after joining the first and second substrates, wherein the second opening is aligned with the first opening.
15. The method of claim 10 wherein the first routing level is formed on a first side of the first substrate, and wherein the method further comprises:
- stripping a conductive material from a surface on a second side of the first substrate opposite the first side; and
- attaching a semiconductor die to at least a portion of the surface.
16. The method of claim 10, further comprising stripping a conductive material from a surface of the second substrate, and wherein joining the first and second substrates includes attaching the first substrate to at least a portion of the surface.
17. A method for manufacturing a semiconductor assembly, the method comprising:
- patterning a first conductive material to define a first trace and a terminal connected to the first trace, wherein the first conductive material is carried by a first non-conductive core;
- patterning a second conductive material to define a second trace and a pad connected to the second trace, wherein the second conductive material is carried by a second non-conductive core;
- attaching the second non-conductive core to at least a portion of the first trace and a surface of the first non-conductive core;
- forming a conductive via at least through the second non-conductive core, wherein the conductive via electrically connects the first trace with the second trace; and
- forming an opening at least through the second non-conductive core to expose the terminal through the opening.
18. The method of claim 17 wherein:
- the surface of the first non-conductive core is at a first side of the first non-conductive core;
- the opening extends through the first non-conductive core; and
- the method further comprises attaching a semiconductor die to a surface of the first non-conductive core at a second side of the first non-conductive core opposite the first side, wherein a portion of the semiconductor die is exposed through the opening.
19. The method of claim 17 wherein the opening is a first opening, and wherein the method further comprises forming a second opening through the first non-conductive core and adjacent the first opening.
20. The method of claim 19, further comprising attaching a semiconductor die to the first non-conductive core, wherein a portion of the semiconductor die is exposed through the first and second openings.
6430058 | August 6, 2002 | Sankman et al. |
7091622 | August 15, 2006 | Kinsman et al. |
20010010090 | July 26, 2001 | Boyle et al. |
20050253284 | November 17, 2005 | Wang et al. |
20060027919 | February 9, 2006 | Ali et al. |
20060113653 | June 1, 2006 | Xiaoqi et al. |
20070094631 | April 26, 2007 | Galatenko et al. |
20070228577 | October 4, 2007 | Corisis et al. |
20130037949 | February 14, 2013 | Chong et al. |
Type: Grant
Filed: Jan 28, 2014
Date of Patent: Feb 23, 2016
Patent Publication Number: 20140141572
Assignee: MICRON TECHNOLOGY, INC. (Boise, ID)
Inventors: Chin Hui Chong (Singapore), Hong Wan Ng (Singapore)
Primary Examiner: Mark Tornow
Application Number: 14/165,855
International Classification: H05K 3/30 (20060101); H01L 23/13 (20060101); H01L 23/498 (20060101); H05K 3/10 (20060101); H05K 3/34 (20060101); H01L 23/31 (20060101); H01L 23/00 (20060101);