Chip imaging module array

Description

FIG. 1 is a front perspective view of an array of stacked imaging modules that includes a first embodiment of my design, each of the imaging modules including, at its front, a currently unclaimed door that slidable outward to permit the imaging module's receipt of one or more microfluidic chips.

FIG. 2 is a top view of the first embodiment.

FIG. 3 is a bottom view of the first embodiment.

FIG. 4 is a front view of the first embodiment.

FIG. 5 is a rear view of the first embodiment.

FIG. 6 is a right side view of the first embodiment, which is a mirror image of a left side view of the first embodiment.

The first embodiment extends to—but does not include—the dash dot boundary lines drawn around the chip imaging modules at their fronts.

FIG. 7 is a front perspective view of an array of side-by-side imaging modules that includes a second embodiment of my design, each of the imaging modules including, at its front, a currently unclaimed door that slidable outward to permit the imaging module's receipt of one or more microfluidic chips.

FIG. 8 is a top view of the first embodiment.

FIG. 9 is a bottom view of the first embodiment.

FIG. 10 is a front view of the first embodiment.

FIG. 11 is a rear view of the first embodiment; and,

FIG. 12 is a right side view of the first embodiment, which is a mirror image of a left side view of the first embodiment.

The second embodiment extends to—but does not include—the dash dot boundary lines drawn around the chip imaging modules at their fronts.

The evenly-spaced broken lines in the figures depict features of the chip imaging modules that form no part of the claimed design. The unevenly-spaced broken lines in the figures depict boundaries of the claimed design and form no part thereof. Surface shading in the figures is provided solely to indicate contour. Any surfaces of portion of my chip imaging module array not shown in the figure or otherwise described in the specification form no part of the claimed design.

Claims

The ornamental design for a chip imaging module array, as shown and described.