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Description
FIG. 1 is a right side, top and front perspective view of a semiconductor showing our new design.
FIG. 2 is a rear elevational view thereof;
FIG. 3 is a left side view thereof;
FIG. 4 is a bottom view thereof.
Referenced Cited
U.S. Patent Documents
Other references
3208892 | September 1965 | Miller et al. |
3436451 | April 1969 | Wasser |
4012766 | March 15, 1977 | Phillips et al. |
- Electronics, 3-17-1977, p. 89, LSI package, leaded type B. Electronics, 11-24-1977, p. 145, integrated circuit housing.
Patent History
Patent number: D259559
Type: Grant
Filed: Jan 24, 1979
Date of Patent: Jun 16, 1981
Assignee: Hitachi, Ltd. (Tokyo)
Inventors: Hidetoshi Mochizuki (Fuchu), Keizo Otsuki (Higashiyamato), Hideki Kosaka (Kodaira), Gen Murakami (Machida)
Primary Examiner: Susan J. Lucas
Law Firm: Craig and Antonelli
Application Number: 6/6,199
Type: Grant
Filed: Jan 24, 1979
Date of Patent: Jun 16, 1981
Assignee: Hitachi, Ltd. (Tokyo)
Inventors: Hidetoshi Mochizuki (Fuchu), Keizo Otsuki (Higashiyamato), Hideki Kosaka (Kodaira), Gen Murakami (Machida)
Primary Examiner: Susan J. Lucas
Law Firm: Craig and Antonelli
Application Number: 6/6,199
Classifications
Current U.S. Class:
D13/99
International Classification: D1303;
International Classification: D1303;