Electronic device
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Description
FIG. 1 is a front view of an electronic device showing our new design;
FIG. 2 is a rear view thereof;
FIG. 3 is a left side view thereof with a right side view appearing as mirror image to the left side view;
FIG. 4 is a top plan view thereof;
FIG. 5 is a bottom plan view thereof;
FIG. 6 is a perspective view from a view point at the right and above the electronic device in FIG. 1; and,
FIG. 7 is a perspective view from a point at the right and above the electronic device in FIG. 2.
Referenced Cited
Patent History
Patent number: D390832
Type: Grant
Filed: Dec 10, 1996
Date of Patent: Feb 17, 1998
Assignee: Elna Kabushiki Kaisha (Fujisawa)
Inventors: Hiroshi Yanaka (Fujisawa), Hideki Kitamura (Fujisawa)
Primary Examiner: James Gandy
Assistant Examiner: Cathron B. Matta
Law Firm: Kanesaka & Takeuchi
Application Number: 0/63,552
Type: Grant
Filed: Dec 10, 1996
Date of Patent: Feb 17, 1998
Assignee: Elna Kabushiki Kaisha (Fujisawa)
Inventors: Hiroshi Yanaka (Fujisawa), Hideki Kitamura (Fujisawa)
Primary Examiner: James Gandy
Assistant Examiner: Cathron B. Matta
Law Firm: Kanesaka & Takeuchi
Application Number: 0/63,552
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;
International Classification: 1303;