Semiconductor package

Info

Patent number: D395423
Type: Grant
Filed: Mar 13, 1997
Date of Patent: Jun 23, 1998
Assignee: Sony Corporation (Tokyo)
Inventors: Michio Koyama (Tokyo), Yukinobu Wataya (Tokyo)
Primary Examiner: James Gandy
Assistant Examiner: Cathron B. Matta
Law Firm: Foley & Lardner
Application Number: 0/68,117

Description

Description

FIG. 1 is a perspective view of a first embodiment of a semiconductor package showing our new design;

FIG. 2 is a left side elevational view thereof, top plan, bottom plan and right side elevational views are the same image;

FIG. 3 is a front elevational view thereof;

FIG. 4 is a rear elevational view thereof;

FIG. 5 is a perspective view of a second embodiment of a semiconductor package showing our new design;

FIG. 6 is a top plan view of the embodiment of FIG. 5;

FIG. 7 is a left side elevational view of the embodiment of FIG. 5;

FIG. 8 is a front elevational view of the embodiment of FIG. 5;

FIG. 9 is a bottom plan view of the embodiment of FIG. 5;

FIG. 10 is a right side elevational view of the embodiment of FIG. 5;

FIG. 11 is a rear elevational view of the embodiment of FIG. 5;

FIG. 12 is a perspective view of a third embodiment of a semiconductor package showing our new design;

FIG. 13 is a top plan view of the embodiment of FIG. 12;

FIG. 14 is a left side elevational view of the embodiment of FIG. 12;

FIG. 15 is a front elevational view of the embodiment of FIG. 12;

FIG. 16 is a bottom plan view of the embodiment of FIG. 12;

FIG. 17 is a right side elevational view of the embodiment of FIG. 12; and,

FIG. 18 is a rear elevational view of the embodiment of FIG. 12.