Connector for printed circuit boards

- Sony Corporation
Description

FIG. 1 is a front view of a connector for printed circuit boards showing our new design in a first embodiment, while the rear view corresponds to the front view.

FIG. 2 is a top view of said connector for printed circuit boards of the first embodiment.

FIG. 3 is a bottom view of said connector for printed circuit boards of the first embodiment.

FIG. 4 is a left side view of said connector for printed circuit boards of the first embodiment, while the right side view corresponds to the left side view.

FIG. 5 is a sectional view along the line V--V in FIG. 2.

FIG. 6 is a sectional view along the line VI--VI in FIG. 1.

FIG. 7 is a sectional view along the line VI--VI in FIG. 1, wherein said connector for printed circuit boards is shown in a condition connecting two circuit boards, which are drawn in broken lines for illustrative purposes only. The circuit boards drawn in broken lines form no part of the claimed design.

FIG. 8 is a front view of a connector for printed circuit boards showing our new design in a second embodiment, while the rear view corresponds to the front view.

FIG. 9 is a top view of said connector for printed circuit boards of the second embodiment.

FIG. 10 is a bottom view of said connector for printed circuit boards of the second embodiment.

FIG. 11 is a left side view of said connector for printed circuit boards of the second embodiment, while the right side view corresponds to the left side view.

FIG. 12 is a sectional view along the line XII--XII in FIG. 9.

FIG. 13 is a sectional view along the line XIII--XIII in FIG. 8; and,

FIG. 14 is a sectional view along the line XIII--XIII in FIG. 8, wherein said connector for printed circuit boards is shown in a condition connecting two circuit boards, which are drawn in broken lines for illustrative purposes only. The circuit boards drawn in broken lines form no part of the claimed design.

Referenced Cited
U.S. Patent Documents
D312242 November 20, 1990 Tsubokura et al.
D317592 June 18, 1991 Yoshizawa
D357901 May 2, 1995 Horman
D359028 June 6, 1995 Siegel et al.
D396449 July 28, 1998 Taylor
5089929 February 18, 1992 Hilland
Foreign Patent Documents
898318 May 1994 JPX
898319 May 1994 JPX
908880 October 1994 JPX
908881 October 1994 JPX
Other references
  • "Electronic Parts Catalog", Electronic Industries Association of Japan, No. 58, p. 88-13, Oct. 4, 1994 (1995 Edition).
Patent History
Patent number: D411512
Type: Grant
Filed: Jul 9, 1998
Date of Patent: Jun 29, 1999
Assignees: Sony Corporation (Tokyo), Solderless Terminal Mfg. Co., Ltd. (Osaka)
Inventors: Yasuhiro Kataoka (Yokohama), Terumi Nakashima (Takatsuki), Narihiko Hashimoto (Nagoya)
Primary Examiner: Brian N. Vinson
Attorneys: W. F. Fasse, W. G. Fasse
Application Number: 0/90,451
Classifications
Current U.S. Class: Linear Array Of Identical Repeating Ports Or Contacts (i.e., In-line Array) (D13/147)
International Classification: 1303;