Wafer level burn-in tester

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Description

FIG. 1 is a perspective view of the top, front and right side of a wafer level burn-in tester showing our new design;

FIG. 2 is a front view thereof;

FIG. 3 is a right side view thereof;

FIG. 4 is a top plan view thereof;

FIG. 5 is a bottom view thereof; and,

FIG. 6 is a rear view thereof.

Referenced Cited
U.S. Patent Documents
D333144 February 9, 1993 Kolzumi
D352911 November 29, 1994 Yamamoto et al.
D365584 December 26, 1995 Nakagone et al.
5851143 December 22, 1998 Hamid
5929651 July 27, 1999 Leas et al.
Foreign Patent Documents
991054 September 1997 JPX
1009499 May 1998 JPX
Patent History
Patent number: D427088
Type: Grant
Filed: Nov 29, 1999
Date of Patent: Jun 27, 2000
Assignee: Matsushita Electric Industrial Co., Ltd.
Inventors: Yoshihiko Asai (Tokyo), Yoshikazu Ezawa (Kanagawa)
Primary Examiner: Antoine Duval Davis
Law Firm: SAIDMAN DesignLaw Group
Application Number: 0/114,644
Classifications
Current U.S. Class: Electrical Property (D10/75)
International Classification: 1004;