Computer processor enclosure
- IBM
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Description
FIG. 1 is a top, front, left side isometric view of a computer processor enclosure, showing our new design;
FIG. 2 is a front view thereof;
FIG. 3 is a right side, back isometric view thereof;
FIG. 4 is a left side, back isometric view thereof;
FIG. 5 is a top plan view thereof; and,
FIG. 6 is a rear view thereof.
The bottom of the computer processor enclosure is unornamented.
Claims
The ornamental design for a computer processor enclosure, as shown and described.
Referenced Cited
Patent History
Patent number: D467919
Type: Grant
Filed: Jan 30, 2002
Date of Patent: Dec 31, 2002
Assignee: International Business Machines Corporation (Armonk, NY)
Inventors: Richard Andrew Crisp (Rochester, MN), Bob Springer (Rochester, MN)
Primary Examiner: Freda Nunn
Attorney, Agent or Law Firm: James R. Nock
Application Number: 29/154,891
Type: Grant
Filed: Jan 30, 2002
Date of Patent: Dec 31, 2002
Assignee: International Business Machines Corporation (Armonk, NY)
Inventors: Richard Andrew Crisp (Rochester, MN), Bob Springer (Rochester, MN)
Primary Examiner: Freda Nunn
Attorney, Agent or Law Firm: James R. Nock
Application Number: 29/154,891
Classifications