Semiconductor device

- Sharp Kabushiki Kaisha
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Description

FIG. 1 is a top, front and right side perspective view of a semiconductor device according to my design;

FIG. 2 is a front elevational view thereof;

FIG. 3 is a rear elevational view thereof;

FIG. 4 is a top plan view thereof;

FIG. 5 is a bottom plan view thereof;

FIG. 6 is a right side elevational view thereof, the left side elevational view being a mirror image thereof;

FIG. 7 is a view of a further embodiment of a semiconductor device similar to FIG. 1, the broken lines illustrating environmental structure of this embodiment which does not form part of the design of this embodiment;

FIG. 8 is a front elevational view thereof;

FIG. 9 is a rear elevational view thereof;

FIG. 10 is a top plan view thereof;

FIG. 11 is a bottom plan view thereof; and,

FIG. 12 is a right side elevational view thereof, the left side elevational view being a mirror image thereof.

Claims

The ornamental design for a “semiconductor device”, as shown and described.

Referenced Cited
U.S. Patent Documents
D278049 March 19, 1985 Takahashi et al.
D280812 October 1, 1985 Takahashi
5485479 January 16, 1996 Kitamura
5604372 February 18, 1997 Yamaguchi
5748658 May 5, 1998 Nakanishi et al.
6034424 March 7, 2000 Fujimura et al.
Patent History
Patent number: D476296
Type: Grant
Filed: Mar 6, 2002
Date of Patent: Jun 24, 2003
Assignee: Sharp Kabushiki Kaisha (Osaka)
Inventor: Hideshi Koizumi (Nara-ken)
Primary Examiner: Ted Shooman
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: Nixon & Vanderhye
Application Number: 29/156,639
Classifications
Current U.S. Class: Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;