Semiconductor device

- Sharp Kabushiki Kaisha
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Description

FIG. 1 is a top, front, and right perspective of a semiconductor device showing my new design;

FIG. 2 is a front elevational view thereof;

FIG. 3 is a rear elevational view thereof;

FIG. 4 is a top plan view thereof;

FIG. 5 is a bottom plan view; and,

FIG. 6 is a right side elevational view, the left side elevational view being a mirror image thereof.

The broken line showing of the environment is for illustrative purpose only and forms no part of the claimed design.

Claims

The ornamental design for a “semiconductor device”, as shown and described.

Referenced Cited
U.S. Patent Documents
D278049 March 19, 1985 Takahashi et al.
D280812 October 1, 1985 Takahashi
5485479 January 16, 1996 Kitamura et al.
5604372 February 18, 1997 Yamaguchi
5748658 May 5, 1998 Nakanishi et al.
6034242 March 7, 2000 Vuligonda et al.
Patent History
Patent number: D481689
Type: Grant
Filed: Mar 11, 2003
Date of Patent: Nov 4, 2003
Assignee: Sharp Kabushiki Kaisha (Osaka)
Inventor: Hideshi Koizumi (Nara-ken)
Primary Examiner: Philip S. Hyder
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: Nixon & Vanderhye
Application Number: 29/177,395
Classifications
Current U.S. Class: Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;