Portion of a matrix for surface mount package leadframe

- GEM Services, Inc.
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Description

FIG. 1 is a top plan view of a portion of a matrix for surface mount package leadframe showing my new design;

FIG. 2 is a top plan view of an enlarged fragment of the portion of a matrix for surface mount package leadframe; and,

FIG. 3 is a perspective view of a portion of a matrix for surface mount package leadframe.

Claims

The ornamental design for a portion of a matrix for surface mount package leadframe, as shown and described.

Referenced Cited
U.S. Patent Documents
3698074 October 1972 Helda et al.
4118859 October 10, 1978 Busler
4234666 November 18, 1980 Gursky
4298883 November 3, 1981 Komatsu et al.
4633582 January 6, 1987 Ching et al.
4809054 February 28, 1989 Waldner
4818960 April 4, 1989 Satoh et al.
4852250 August 1, 1989 Andrews
4865193 September 12, 1989 Shimamoto et al.
5115299 May 19, 1992 Wright
5554886 September 10, 1996 Song
5900582 May 4, 1999 Tomita et al.
6016918 January 25, 2000 Ziberna
6170151 January 9, 2001 Link et al.
6265761 July 24, 2001 Ghai
6329710 December 11, 2001 Corisis et al.
6389672 May 21, 2002 Ishii et al.
D465207 November 5, 2002 Williams et al.
6486538 November 26, 2002 Reiss et al.
6543512 April 8, 2003 Hamren
6566740 May 20, 2003 Yasunaga et al.
Patent History
Patent number: D488136
Type: Grant
Filed: Jan 3, 2003
Date of Patent: Apr 6, 2004
Assignee: GEM Services, Inc. (San Jose, CA)
Inventors: James Harnden (Hollister, CA), Richard K. Williams (Cupertino, CA), Anthony Chia (Singapore), Chu Weibing (Shanghai), Allen K. Lam (Fremont, CA)
Primary Examiner: Philip S. Hyder
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: Townsend and Townsend and Crew LLP
Application Number: 29/173,646
Classifications
Current U.S. Class: Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;