Base for a semiconductor carrier
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Description
FIG. 1 is a front view of a base for a semiconductor carrier showing our new design, the rear view being a mirror image thereof;
FIG. 2 is a top view thereof;
FIG. 3 is a bottom view thereof, the perforations shown in dashed lines being no part of the claimed design;
FIG. 4 is a right-side view thereof;
FIG. 5 is a left-side view thereof; and,
FIG. 6 is a perspective view thereof.
Claims
The ornamental design for a base for a semiconductor carrier, as shown and described.
Referenced Cited
U.S. Patent Documents
D359028 | June 6, 1995 | Siegel et al. |
5451165 | September 19, 1995 | Cearley-Cabbiness et al. |
5519332 | May 21, 1996 | Wood et al. |
5541525 | July 30, 1996 | Wood et al. |
D401567 | November 24, 1998 | Farnworth et al. |
20010043074 | November 22, 2001 | Hambree et al. |
20040016993 | January 29, 2004 | Ham et al. |
Patent History
Patent number: D516046
Type: Grant
Filed: May 10, 2005
Date of Patent: Feb 28, 2006
Assignee: Yamaichi Electronics Co. (Tokyo)
Inventors: Yuji Nakamura (Tokyo), Katsumi Suzuki (Tokyo), Takahiro Ishibashi (Tokyo), Eiji Kobori (Tokyo)
Primary Examiner: Stella Reid
Assistant Examiner: Selina Sikder
Attorney: Finnegan, Henderson, Farabow, Garrett & Dunner, LLP
Application Number: 29/229,567
Type: Grant
Filed: May 10, 2005
Date of Patent: Feb 28, 2006
Assignee: Yamaichi Electronics Co. (Tokyo)
Inventors: Yuji Nakamura (Tokyo), Katsumi Suzuki (Tokyo), Takahiro Ishibashi (Tokyo), Eiji Kobori (Tokyo)
Primary Examiner: Stella Reid
Assistant Examiner: Selina Sikder
Attorney: Finnegan, Henderson, Farabow, Garrett & Dunner, LLP
Application Number: 29/229,567
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)