Portion of a semiconductor device
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Description
FIG. 1 is a top plan view of portion of a semiconductor device, showing my new design; the opposite side being a mirror image thereof;
FIG. 2 is a front elevational view thereof;
FIG. 3 is a right side elevational view thereof; the opposite side being a mirror image thereof;
FIG. 4 is a rear elevational view thereof; and,
FIG. 5 is an enlarged fragmented rear elevational view thereof, taken along the line 5—5 in FIG. 2.
The broken lines are for illustrative purposes only and form no part of the claimed design.
Claims
The ornamental design for portion of a semiconductor device, as shown and described.
Referenced Cited
U.S. Patent Documents
Foreign Patent Documents
D319814 | September 10, 1991 | Hasegawa et al. |
6268650 | July 31, 2001 | Kinsman et al. |
D457146 | May 14, 2002 | Yamamoto et al. |
6515355 | February 4, 2003 | Yin et al. |
6531335 | March 11, 2003 | Grigg |
D473198 | April 15, 2003 | Ozawa et al. |
20020064901 | May 30, 2002 | Miyazaki et al. |
20020093082 | July 18, 2002 | Miyamoto et al. |
20030064542 | April 3, 2003 | Corisis |
20030165051 | September 4, 2003 | Kledzik et al. |
1127626 | December 2001 | JP |
Patent History
Patent number: D522470
Type: Grant
Filed: Nov 19, 2004
Date of Patent: Jun 6, 2006
Assignee: Kabushiki Kaisha Toshiba
Inventor: Yukiko Mizukoshi (Kita-ku)
Primary Examiner: Stella Reid
Assistant Examiner: Selina Sikder
Attorney: Banner & Witcoff, Ltd.
Application Number: 29/217,557
Type: Grant
Filed: Nov 19, 2004
Date of Patent: Jun 6, 2006
Assignee: Kabushiki Kaisha Toshiba
Inventor: Yukiko Mizukoshi (Kita-ku)
Primary Examiner: Stella Reid
Assistant Examiner: Selina Sikder
Attorney: Banner & Witcoff, Ltd.
Application Number: 29/217,557
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)