Substrate for a semiconductor device

- Kabushiki Kaisha Toshiba
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Description

FIG. 1 is a top plan view of a substrate for a semiconductor device, showing my new design; the opposite side being a mirror image thereof;

FIG. 2 is a front elevational view thereof;

FIG. 3 is a right side elevational view thereof; the opposite side being a mirror image thereof; and,

FIG. 4 is a rear elevational view thereof.

Claims

The ornamental design for a substrate for a semiconductor device, as shown and described.

Referenced Cited
U.S. Patent Documents
D319814 September 10, 1991 Hasegawa et al.
6268650 July 31, 2001 Kinsman et al.
D457146 May 14, 2002 Yamamoto et al.
6515355 February 4, 2003 Jiang et al.
6531335 March 11, 2003 Grigg
D473198 April 15, 2003 Ozawa et al.
20020064901 May 30, 2002 Miyazaki et al.
20020093082 July 18, 2002 Miyamoto et al.
20030064542 April 3, 2003 Corisis
20030165051 September 4, 2003 Kledzik et al.
Foreign Patent Documents
D1145773 July 2002 JP
D1166594 March 2003 JP
D1166916 March 2003 JP
Patent History
Patent number: D523403
Type: Grant
Filed: Nov 19, 2004
Date of Patent: Jun 20, 2006
Assignee: Kabushiki Kaisha Toshiba
Inventor: Yukiko Mizukoshi (Kita-ku)
Primary Examiner: Stella Reid
Assistant Examiner: Selina Sikder
Attorney: Banner & Witcoff, Ltd.
Application Number: 29/217,556