Integrated circuit tag

- Riso Kagaku Corporation
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Description

FIG. 1 is a front elevational view of and integrated circuit tag showing my new design;

FIG. 2 is a is top plan view thereof;

FIG. 3 is a left side elevational view thereof;

FIG. 4 is a right side elevational view thereof;

FIG. 5 is a rear elevational view thereof; and,

FIG. 6 is a bottom plan view thereof;

Claims

The ornamental design for an integrated circuit tag, as shown and described.

Referenced Cited
U.S. Patent Documents
4797785 January 10, 1989 Jorgensen
D359476 June 20, 1995 Sakashita et al.
6072394 June 6, 2000 Hasegawa et al.
6091607 July 18, 2000 McKeown et al.
6327168 December 4, 2001 Campbell
6835412 December 28, 2004 Burke
20050183817 August 25, 2005 Eckstein et al.
Patent History
Patent number: D529000
Type: Grant
Filed: Mar 18, 2004
Date of Patent: Sep 26, 2006
Assignee: Riso Kagaku Corporation (Tokyo)
Inventor: Hiroaki Ishii (Ibaraki-ken)
Primary Examiner: Prabhakar Deshmukh
Assistant Examiner: Selina Sikder
Attorney: Frommer Lawrence & Haug LLP
Application Number: 29/201,582