Semiconductor wafer delivery apparatus
Latest Tokyo Electron Limited Patents:
- IN-SITU HYBRID BONDING TEST MEASUREMENTS
- SEQUENTIAL COMPLIMENTARY FET INCORPORATING BACKSIDE POWER DISTRIBUTION NETWORK THROUGH WAFER BONDING PRIOR TO FORMATION OF ACTIVE DEVICES
- INFORMATION PROCESSING METHOD, COMPUTER PROGRAM, AND INFORMATION PROCESSING APPARATUS
- Plasma processing apparatus and plasma processing method
- Plasma processing apparatus and plasma processing method
Description
The broken line showing in the figures is for illustrative purposes only and forms no part of the claimed design.
Claims
The ornamental design for a semiconductor wafer delivery apparatus, as shown and described.
Referenced Cited
U.S. Patent Documents
| 5636960 | June 10, 1997 | Hiroki et al. |
| 5740059 | April 14, 1998 | Hirata et al. |
| 5772386 | June 30, 1998 | Mages et al. |
| 5826129 | October 20, 1998 | Hasebe et al. |
| 6132160 | October 17, 2000 | Iwai |
| 6234738 | May 22, 2001 | Kimata et al. |
| 6811370 | November 2, 2004 | Buermann |
| 6846149 | January 25, 2005 | Savage et al. |
| 20020044860 | April 18, 2002 | Hayashu et al. |
| 20020182040 | December 5, 2002 | Kimura et al. |
| 20020197138 | December 26, 2002 | Cho et al. |
| 20030133776 | July 17, 2003 | Lee |
| 20040265100 | December 30, 2004 | Ohkawara et al. |
| 20050220581 | October 6, 2005 | Chuang et al. |
| 20070031222 | February 8, 2007 | Hosaka et al. |
Patent History
Patent number: D571739
Type: Grant
Filed: Nov 14, 2005
Date of Patent: Jun 24, 2008
Assignee: Tokyo Electron Limited (Tokyo)
Inventor: Hiroki Hosaka (Nirasaki)
Primary Examiner: Selina Sikder
Attorney: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Application Number: 29/242,544
Type: Grant
Filed: Nov 14, 2005
Date of Patent: Jun 24, 2008
Assignee: Tokyo Electron Limited (Tokyo)
Inventor: Hiroki Hosaka (Nirasaki)
Primary Examiner: Selina Sikder
Attorney: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Application Number: 29/242,544
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)