Semiconductor wafer delivery apparatus
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Description
The broken line showing and the indicia shown in the Figures are shown for illustrative purposes only and form no part of the claimed design.
Claims
The ornamental design for a semiconductor wafer delivery apparatus, as shown and described.
Referenced Cited
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Patent History
Patent number: D571740
Type: Grant
Filed: Nov 14, 2005
Date of Patent: Jun 24, 2008
Assignee: Tokyo Electron Limited (Tokyo)
Inventor: Hiroki Hosaka (Nirasaki)
Primary Examiner: Selina Sikder
Attorney: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Application Number: 29/242,546
Type: Grant
Filed: Nov 14, 2005
Date of Patent: Jun 24, 2008
Assignee: Tokyo Electron Limited (Tokyo)
Inventor: Hiroki Hosaka (Nirasaki)
Primary Examiner: Selina Sikder
Attorney: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Application Number: 29/242,546
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)