Electronic computer with partially transparent input device
- Intel
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Description
Any broken lines in the preceding FIGURES are for illustration only and form no part of the claimed design.
Claims
The ornamental design for an electronic computer with an at least partially transparent input device, as shown and described.
Referenced Cited
U.S. Patent Documents
| D358376 | May 16, 1995 | Poon |
| 6480373 | November 12, 2002 | Landry et al. |
| D616880 | June 1, 2010 | Andre et al. |
| D631043 | January 18, 2011 | Kell |
| 7999792 | August 16, 2011 | Tsuji et al. |
| D649544 | November 29, 2011 | Chiu et al. |
| D658171 | April 24, 2012 | Masui et al. |
| D660835 | May 29, 2012 | Cheng |
| 20050243783 | November 3, 2005 | Lee et al. |
| 20070120762 | May 31, 2007 | O'Gorman |
| 20090179859 | July 16, 2009 | Wisebourt et al. |
| 20090322689 | December 31, 2009 | Kwong et al. |
| 20110242750 | October 6, 2011 | Oakley |
| 20110255727 | October 20, 2011 | Azuchi |
Patent History
Patent number: D694232
Type: Grant
Filed: May 31, 2012
Date of Patent: Nov 26, 2013
Assignee: Intel Corporation (Santa Clara, CA)
Inventors: Peter Adamson (Portland, OR), Gary Paek (Beaverton, OR), Nicholas Oakley (Portland, OR)
Primary Examiner: Freda S Nunn
Application Number: 29/423,475
Type: Grant
Filed: May 31, 2012
Date of Patent: Nov 26, 2013
Assignee: Intel Corporation (Santa Clara, CA)
Inventors: Peter Adamson (Portland, OR), Gary Paek (Beaverton, OR), Nicholas Oakley (Portland, OR)
Primary Examiner: Freda S Nunn
Application Number: 29/423,475
Classifications
Current U.S. Class:
And Touch Type Cursor Pad (D14/318)