Signal I/O module
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Description
The broken lines shown are included for the purpose of illustrating the unclaimed portions of the signal I/O module and form no part of the claimed design.
Claims
The ornamental design for a signal I/O module, as shown and described.
Referenced Cited
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Patent History
Patent number: D772172
Type: Grant
Filed: Jul 25, 2014
Date of Patent: Nov 22, 2016
Assignee: YOKOGAWA ELECTRIC CORPORATION (Tokyo)
Inventors: Naoto Takano (Musashino), Noriaki Senba (Musashino), Kouichirou Shimamura (Musashino), Hiroki Kuraishi (Musashino)
Primary Examiner: Susan E Krakower
Assistant Examiner: Camelia Styles
Application Number: 29/497,558
Type: Grant
Filed: Jul 25, 2014
Date of Patent: Nov 22, 2016
Assignee: YOKOGAWA ELECTRIC CORPORATION (Tokyo)
Inventors: Naoto Takano (Musashino), Noriaki Senba (Musashino), Kouichirou Shimamura (Musashino), Hiroki Kuraishi (Musashino)
Primary Examiner: Susan E Krakower
Assistant Examiner: Camelia Styles
Application Number: 29/497,558
Classifications