Semiconductor wafer processing apparatus

- Lam Research Corporation
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Description

FIG. 1 is a perspective view depicting the overall shape of the semiconductor wafer processing apparatus, showing my new design;

FIG. 2 is a front view thereof;

FIG. 3 is a rear view thereof;

FIG. 4 is a left side view thereof;

FIG. 5 is a right side view thereof;

FIG. 6 is a top plan view thereof; and,

FIG. 7 is a bottom plan view thereof.

The broken line showings of portions of the semiconductor wafer processing apparatus and portions of the semiconductor wafer processing tool illustrate environmental structure, and the broken lines form no part of the claimed design.

The shape of the semiconductor wafer processing apparatus is the feature of the design creation content.

Claims

The ornamental design for a semiconductor wafer processing apparatus, as shown and described.

Referenced Cited
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D900892 November 3, 2020 Zhang
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D928722 August 24, 2021 Kok
D928854 August 24, 2021 Zhang
D929475 August 31, 2021 Tavares Andre
D930054 September 7, 2021 Bangalore Srinivas
Other references
  • Semiconductor Wafer Apparatus. (Design—© Questel) orbit.com. [Online PDF compilation of references] 59 pgs. Print Dates Range Jul. 16, 2019-Jun. 2, 2000 [Retrieved Sep. 13, 2021].
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  • https://www.researchgate.net/publication/35950411_Nonlinear_control_of_a_planar_magnetic_levitation_system_microformLevis, Michel. “Nonlinear Control of a Planar Magnetic Lefitation System.” 2003. University of Toronto.
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Patent History
Patent number: D962881
Type: Grant
Filed: May 6, 2019
Date of Patent: Sep 6, 2022
Assignee: Lam Research Corporation (Fremont, CA)
Inventor: Eller Y. Juco (Tualatin, OR)
Primary Examiner: Manpreet S Matharu
Assistant Examiner: Suzanne E Tisdell
Application Number: 29/690,192