Synchronous burst-access memory

Abstract

A synchronous burst-access memory latches a row address strobe signal, a column address strobe signal, and address signals in synchronization with a clock signal. Data are stored in rows and columns in a memory cell array. Data in a selected row are input and output in serial bursts in synchronization with the clock signal, starting from a selected column. The row and initial column address are provided as external inputs; subsequent column addresses are generated by an internal address counting circuit. A word-line driving circuit for a synchronous memory uses transparent latches to latch the row address strobe signal and address signals, enabling row address decoding to be completed prior to synchronization with the clock signal.

Claims

2. The memory of claim 1, wherein said first internal control signal is generated from said row address strobe signal and said clock signal.

3. The memory of claim 1, wherein said second internal control signal is generated from said column address strobe signal and said clock signal.

4. The memory of claim 1, wherein said memory cells are dynamic memory cells.

5. The memory of claim 1, also comprising frequency-dividing means for dividing said clock signal in frequency before said clock signal is supplied to said latching means, said address counting means, and said input/output means.

6. The memory of claim 5, wherein said frequency-dividing means divides the frequency of said clock signal by an amount selected by an external control signal.

7. The memory of claim 5, wherein said frequency-dividing means divides the frequency of said clock signal by an amount selected by a manufacturing option.

8. The memory of claim 1, also comprising clock control means coupled to said latching means, for blocking input of said clock signal to said address counting means and said input/output means while said column address strobe signal is inactive.

9. The memory of claim 8, wherein said clock control means comprises an OR gate having said clock signal and said column address strobe signal as inputs.

10. The memory of claim 8, wherein said latching means generates a third internal control signal causing said input/output means to cease input and output when said column address strobe signal is inactive.

11. The memory of claim 1, wherein said number is determined by said address signals.

12. The memory of claim 11, wherein said access counting means receives said number from said latching means in synchronization with said clock signal when said column address strobe signal becomes active for a second time after said row address strobe signal becomes active.

13. The memory of claim 11, wherein said access counting means comprises a down-counter preset according to said number, for generating said fourth internal control signal when a certain count is reached.

14. The memory of claim 11, wherein said access clock counting means comprises:

an up-counter for counting said clock signal, thus generating a count value;

a register for storing said number; and

a match-detecting circuit coupled to said counter and said register, for comparing said count value with the contents of said register and generating said fourth control signal when said count value matches said contents of said register.

15. The memory of claim 12, further comprising disabling means coupled to said latching means, for enabling said access counting means to receive said number from said latching means only during a certain interval after said column address strobe signal first becomes active following activation of said row address strobe signal.

16. The memory of claim 15, wherein said disabling means determines said interval by counting.Iadd.the pulses of.Iaddend.said clock signal.

17. The memory of claim 15, further comprising clock control means coupled to said latching means, for blocking input of said clock signal to said address counting means and said input/output means when said column address strobe signal is inactive before and after but not during said interval.

18. The memory of claim 1, also comprising flag output means coupled to said access counting means, for generating a flag signal indicating completion of access.

21. The memory of claim 18, wherein said flag output means has flag shifting means for delaying output of said flag signal by a selectable amount of time.

22. The memory of claim 21, wherein said amount of time is selected by a manufacturing option.

23. The memory of claim 21, wherein said amount of time is selected by an external shift control signal.

24. The memory of claim 23, wherein said access clock counting means generates an ending signal a certain time before said number of clock signals have been counted, and said flag shifting means comprises:

a first tri-state buffer for receiving said ending signal from said access clock counting means;

a delay line for receiving said ending signal from said access clock counting means and generating a delayed ending signal;

a second tri-state buffer coupled to said delay line, for receiving said delayed ending signal from said delay line;

a first inverter coupled to said first tri-state buffer and said second tri-state buffer, for inverting said shift control signal at a point between said first tri-state buffer and said second tri-state buffer; and

a second inverter coupled to said first tri-state buffer and said second tri-state buffer, for inverting either a first output signal of said first tri-state buffer or a second output signal of said second tri-state buffer in response to said shift control signal and generating a third output signal sent to said flag output circuit;

said first tri-state buffer being enabled by said inverted shift control signal by said first inverter;

said second tri-state buffer being enabled by said shift control signal; and

when enabled, both said first tri-state buffer and said second tri-state buffer acting as inverters.

26. The memory device according to claim 25, wherein said first strobe signal defines a first accessible period in every read/write cycle; and wherein said second strobe signal defines second and third accessible periods within the first accessible period defined by said first strobe signal; said first internal address value being outputted from said address buffer means at the beginning of said first accessible period; said second internal address value being outputted from said address buffer means at the beginning of said second accessible period.

28. A memory device to receive a clock signal and first and second strobe signals, said first strobe signal defining a first accessible period in every read/write cycle, said second strobe signal defining second and third accessible periods within the first accessible period defined by said first strobe signal, said memory device comprising:

input/output circuit means for external input and output of data;

a memory cell array having a plurality of memory cell groups, said memory cell groups each having a plurality of memory cells respectively to store data therein;

address buffer means for receiving external address information, said address buffer means outputting a first internal address value in response to said first strobe signal and outputting a second internal address value in response to said second strobe signal;

first decoder means, responsive to said first internal address value, for selecting one of said memory cell groups;

address counter means, responsive to said clock signal, for generating consecutive address values starting from said second internal address value, said address counter means stopping generating consecutive address values during an inaccessible period between said second and third accessible periods;

second decoder means for selecting one of the memory cells in said selected memory cell group in response to each of said consecutive address values; and

data transfer circuit means for consecutively transferring data from said input/output circuit means to said selected memory cell and from said selected memory cell to said input/output circuit means..Iadd.

29. A synchronous burst-access memory to receive a clock signal, a row address strobe signal, a column address strobe signal and address signals, comprising:

a memory cell array having a plurality of memory cells each of which stores data therein;

a latch circuit receiving the row address strobe signal, the column address strobe signal and the address signals in synchronization with the clock signal, said latch circuit generating first and second internal control signals from the received signals;

an input/output circuit coupled to said latch circuit, said input/output circuit receiving and outputting data in synchronization with the clock signal;

a row address decoder coupled to said memory cell array, said row address decoder selecting a row of the memory cells in said memory cell array in response to the first internal control signal;

an address counter coupled to said latch circuit, said address counter generating a consecutive series of column addresses starting from a preset address determined by the address signals and the second internal control signal;

a column address decoder coupled to said address counter, said column address decoder selecting corresponding columns in said memory cell array in response to the consecutive series of column addresses;

a data transfer circuit coupled to said memory cell array and said input/output circuit, said transfer circuit transferring data from said input/output circuit to said memory cell array and from said memory cell array to said input/output circuit, data being transferred to and from memory cells disposed in columns selected by said column address decoder and in the row selected by said row address decoder; and

an access counter coupled to said address counter and said input/output circuit, said access counter generating a fourth internal control signal when a certain number of pulses of the clock signal have been counted thereby, said fourth internal control signal commanding said address counter to cease generating column addresses and said input/output circuit to cease inputting and outputting..Iaddend..Iadd.

30. A synchronous burst-access memory according to claim 29, wherein said first internal control signal is generated from said row address strobe signal and said clock signal..Iaddend..Iadd.31. A synchronous burst-access memory according to claim 29, wherein said latch circuit comprises:

an input latch circuit receiving the clock signal, the row address strobe signal and the column address strobe signal; and

an address buffer receiving the clock signal and address

signals..Iaddend..Iadd.32. A synchronous burst-access memory according to claim 29, wherein said second internal control signal is generated from said column address strobe signal and said clock signal..Iaddend..Iadd.33. A synchronous burst-access memory according to claim 29, further comprising a clock control circuit coupled to said latch circuit, said clock control circuit blocking input of the clock signal to said address counter and said input/output circuit while said column address strobe signal is inactive..Iaddend..Iadd.34. A synchronous burst-access memory according to claim 33, wherein said clock control circuit comprises a gate circuit receiving the clock signal and the column address strobe signal..Iaddend..Iadd.35. A synchronous burst-access memory according to claim 29, wherein said latch circuit generates a third internal control signal causing said input/output circuit to cease input and output when

the column address strobe signal is inactive..Iaddend..Iadd.36. A synchronous burst-access memory according to claim 29, wherein said access counter comprises a down-counter generating said fourth internal control signal when a certain count is reached..Iaddend..Iadd.37. A synchronous burst-access memory according to claim 29, wherein said access counter comprises:

an up-counter counting the clock signal and generating a count value signal;

a register coupled to said latch circuit, the register receiving a current address value signal from the latch circuit; and

a match-detecting circuit coupled to the up-counter and register, the match-detecting circuit comparing the count value signal with the current address value signal and generating the fourth control signal when the count value matches the current address value signal..Iaddend..Iadd.38. A synchronous burst-access memory according to claim 29, further comprising a disabling circuit coupled to said latch circuit, the disabling circuit controlling said access counter to receive the signal from said latch circuit only during a certain interval after said column address strobe signal first becomes active following activation of said row address

strobe signal..Iaddend..Iadd.39. A synchronous burst-access memory according to claim 38, wherein the disabling circuit determines the interval by counting the pulses of clock signal..Iaddend..Iadd.40. A synchronous burst-access memory according to claim 38, further comprising a clock control circuit coupled to said latch circuit, the clock control circuit blocking input of the clock signal to said address counter and input/output circuit when the column address strobe signal is inactive before and after but not during said interval..Iaddend..Iadd.41. A synchronous burst-access memory according to claim 29, further comprising a flag output circuit coupled to said access counter, the flag output circuit generating a flag signal indicating completion of access..Iaddend..Iadd.42. A synchronous burst-access memory according to claim 41, wherein the flag signal is generated when said access counter has counted the number of pulses of the clock signal..Iaddend..Iadd.43. A synchronous burst-access memory according to claim 41, wherein said flag signal is generated a certain time before said access counter has counted said number of pulses of the clock signal..Iaddend..Iadd.44. A synchronous burst-access memory according to claim 41, wherein the flag output circuit includes a flag shifting circuit delaying output of the flag signal by a

selectable amount of time..Iaddend..Iadd.45. A memory device to receive a clock signal and first and second strobe signals, comprising:

an input/output circuit;

a memory cell array having a plurality of memory cell groups, the memory cell groups each having a plurality of memory cells respectively to store data therein;

an address buffer receiving external address signals, said address buffer outputting a first internal address signal in response to the first strobe signal and outputting a second internal address signal in response to the second strobe signal;

a first decoder selecting one of the memory cell groups in response to the first internal address signal;

an address counter generating consecutive address signals starting from the second internal address signal in response to the clock signal;

a second decoder selecting one of the memory cells in the selected memory cell group in response to each of the consecutive address signals;

a data transfer circuit consecutively transferring data from said input/output circuit to the selected memory cell and from the selected memory cell to the input/output circuit; and

an access counter counting pulses of the clock signal and generating an internal control signal to said address counter so as to cause said address counter to cease generating the consecutive address signals when a certain number of pulses of the clock signal have been counted..Iaddend..Iadd.46. A memory device according to claim 45, further comprising a latch circuit having:

an input latch circuit receiving the clock signal, the row address strobe signal and the column address strobe signal; and

an address buffer receiving the clock signal and address signals..Iaddend..Iadd.47. A memory device according to claim 45, further comprising a latch circuit and a clock control circuit coupled to said latch circuit, said clock control circuit blocking input of the clock signal to said address counter and said input/output circuit while said column address strobe signal is inactive..Iaddend..Iadd.48. A memory device according to claim 47, wherein said clock control circuit comprises a gate circuit receiving the clock signal and the column address strobe signal..Iaddend..Iadd.49. A memory device according to claim 45, further comprising a latch circuit wherein said latch circuit generates a third internal control signal causing said input/output circuit to cease input and output when the column address strobe signal is inactive..Iaddend..Iadd.50. A memory device according to claim 45, wherein said access counter comprises a down-counter generating a fourth internal control signal when a certain count is reached..Iaddend..Iadd.51. A memory device according to claim 45, further comprising a latch circuit; and wherein said access counter comprises:

an up-counter counting the clock signal and generating a count value signal;

a register coupled to said latch circuit, the register receiving a current address value signal from the latch circuit; and

a match-detecting circuit coupled to the up-counter and register, the match-detecting circuit comparing the count value signal with the current address value signal and generating the fourth control signal when the count value matches the current address value signal..Iaddend..Iadd.52. A memory device according to claim 45, further comprising a latch circuit and a disabling circuit coupled to said latch circuit, the disabling circuit controlling said access counter to receive the signal from said latch circuit only during a certain interval after said column address strobe signal first becomes active following activation of said row address strobe signal..Iaddend..Iadd.53. A memory device according to claim 52, wherein the disabling circuit determines the interval by

counting the pulses of said clock signal..Iaddend..Iadd.54. A memory device according to claim 52, further comprising a latch circuit and a clock control circuit coupled to said latch circuit, the clock control circuit blocking input of the clock signal to said address counter and input/output circuit when the column address strobe signal is inactive before and after but not during said interval..Iaddend..Iadd.55. A memory device according to claim 45, further comprising a flag output circuit coupled to said access counter, the flag output circuit generating a flag signal indicating completion of access..Iaddend..Iadd.56. A memory device according to claim 55, wherein the flag signal is generated when said access counter has counted the number of pulses of the clock signal..Iaddend..Iadd.57. A memory device according to claim 55, wherein said flag signal is generated a certain time before said access counting means has counted said number of pulses of the clock signal..Iaddend..Iadd.58. A memory device according to claim 55, wherein the flag output circuit includes a flag shifting circuit delaying output of the flag signal by a selectable amount of time..Iaddend..Iadd.59. A memory device to receive a clock signal and first and second strobe signals, said first strobe signal defining a first accessible period in every read/write cycle, said second strobe signal defining second and third accessible periods within the first accessible period defined by said first strobe signal, said memory device comprising:

an input/output circuit;

a memory cell array having a plurality of memory cell groups, said memory cell groups each having a plurality of memory cells respectively to store data therein;

an address buffer receiving external address signals, said address buffer outputting a first internal address signal in response to said first strobe signal and outputting a second internal address signal in response to said second strobe signal;

a first decoder selecting one of said memory cell groups in response to the first internal address signal;

an address counter generating consecutive address signals starting from the second internal address signal in response to the clock signal, said address counter stopping generating consecutive address signals during an inaccessible period between the second and third accessible periods;

a second decoder selecting one of the memory cells in said selected memory cell group in response to each of said consecutive address signals; and

a data transfer circuit consecutively transferring data from said input/output circuit to said selected memory cell and from said selected memory cell to said input/output circuit..Iaddend.