Counting Patents (Class 365/236)
  • Patent number: 10698732
    Abstract: Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for determining that an object implicated in an executing application is to be allocated to memory in an in-memory system, determining a type of the object, and allocating the object to one of a first size of virtual memory page and a second size of virtual memory page of an operating system based on the type of the object.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: June 30, 2020
    Assignee: SAP SE
    Inventor: Ahmad Hassan
  • Patent number: 10579827
    Abstract: User events are processed to estimate a unique user count. An identifier hash, having a bucket index portion denoting one of a plurality hash buckets, is generated for each of the user events. At a processing node, each of the user events is allocated to one of a plurality of processing threads based on the bucket index portion of its identifier hash. A unique user count is estimated as follows: for each user event satisfying at least one query parameter, 1) determine a run length of a second portion of its identifier hash, 2) compare it with a value of the hash bucket denoted by the bucket index portion of that identifier hash, and 3) if the determined run length is greater, change that hash bucket value at that node to match the determined run length. The hash bucket values are used to estimate the unique user count.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: March 3, 2020
    Assignee: Meltwater News International Holdings GmbH
    Inventors: Nicholas Telford, Andi Miller, Alistair Joseph Bastian
  • Patent number: 10447541
    Abstract: Some embodiments provide a method for dynamically implementing quality of service (QoS) for machines of a network. The method identifies a QoS policy rule that defines a QoS policy to be implemented for machines that meet a set of criteria specified by the QoS policy rule. The method dynamically identifies a set of machines that meet the set of criteria. The method configures a set of managed forwarding elements of the network to implement the QoS policy rule for network traffic associated with the set of machines. In some embodiments, the method monitors network events (e.g., user logins, addition of new machines, etc.) and identifies a corresponding QoS policy rule to be enforced at corresponding locations in the network based on the detected event.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: October 15, 2019
    Assignee: NICIRA, INC.
    Inventors: Yogesh Gaikwad, Amol Kanitkar, Shreyas Bhatewara
  • Patent number: 10402202
    Abstract: A pipe latch circuit includes: a pipe latch control block suitable for controlling a plurality of pipe input signals and a plurality of pipe output signals to be activated sequentially or be divided into at least two groups and be activated sequentially by group, depending on a latency setting value, and outputting at least one pipe input signal and at least one pipe output signal; and a pipe latch block coupled between an input node and an output node, and suitable for storing data of the input node in response to the pipe input signal and outputting stored data to the output node in response to the pipe output signal.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: September 3, 2019
    Assignee: SK hynix Inc.
    Inventor: Yun-Gi Hong
  • Patent number: 9891887
    Abstract: A microprocessor prepares a fused multiply-accumulate operation of a form ±A*B±C for execution by issuing first and second multiply-accumulate microinstructions to one or more instruction execution units to complete the fused multiply-accumulate operation. The first multiply-accumulate microinstruction causes an unrounded nonredundant result vector to be generated from a first accumulation of a selected one of (a) the partial products of A and B or (b) C with the partial products of A and B. The second multiply-accumulate microinstruction causes performance of a second accumulation of C with the unrounded nonredundant result vector, if the first accumulation did not include C. The second multiply-accumulate microinstruction also causes a final rounded result to be generated from the unrounded nonredundant result vector, wherein the final rounded result is a complete result of the fused multiply-accumulate operation.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: February 13, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD
    Inventor: Thomas Elmer
  • Patent number: 9851902
    Abstract: To produce output from a memory block, a first index is used to access a pointer, a mode select and a function select from a first memory. The pointer, the mode select and the function select are used to produce a second index. The pointer is used to produce the second index when the mode select is a first value. A function is used to produce the second index when the mode select is a second value. The function select identifies a function to be used to produce the second index. The second index is used to access output from a second memory.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: December 26, 2017
    Assignee: Memobit Technologies AB
    Inventors: Pär S Westlund, Lars-Olof B Svensson
  • Patent number: 9734898
    Abstract: A memory controller includes a state shaping encoder that receives k-bit write data, selects a logical page with reference to state shape mapping information, and changes data of the logical page to decrease an occurrence probability of a high-order program state among program states used to program the k-bit data in multi-level memory cells.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: August 15, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changkyu Seol, Junjin Kong, Hyejeong So, Hong Rak Son
  • Patent number: 9729353
    Abstract: An NFA hardware engine includes a pipeline and a controller. The pipeline includes a plurality of stages, where one of the stages includes a transition table. Both a first automaton and a second automaton are encoded in the same transition table. The controller receives NFA engine commands onto the NFA engine and controls the pipeline in response to the NFA engine commands.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: August 8, 2017
    Assignee: Netronome Systems, Inc.
    Inventors: Gavin J. Stark, Steven W. Zagorianakos
  • Patent number: 9508458
    Abstract: A semiconductor memory device may include: a plurality of first to third memory cells, each memory cell being a DRAM memory cell; a plurality of fuses suitable for storing repair information for replacing failed first memory cells with corresponding second memory cells; a normal operation unit suitable for accessing and refreshing one or more of the first and second memory cells according to the repair information during a normal mode; and a repair operation unit suitable for providing the repair information from the fuses to the third memory cells during a boot-up mode, and for providing the repair information from the third memory cells to the normal operation unit and for refreshing the third memory cells during a normal mode.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: November 29, 2016
    Assignee: SK Hynix Inc.
    Inventor: Sung-Ho Kim
  • Patent number: 9413357
    Abstract: Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: August 9, 2016
    Assignee: Cavium, Inc.
    Inventors: Weihuang Wang, Gerald Schmidt, Srinath Alturi, Weinan Ma, Shrikant Sundaram Lnu
  • Patent number: 9396129
    Abstract: A computational device maintains a first type of cache and a second type of cache. The computational device receives a command from the host to release space. The computational device synchronously discards tracks from the first type of cache, and asynchronously discards tracks from the second type of cache.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: July 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael T. Benhase, Lokesh M. Gupta
  • Patent number: 9349155
    Abstract: A computing apparatus is provided. The computing apparatus includes a memory unit configured to have an address space defined as a multidimensional space having at least two axes, and a memory access unit configured to include a first pointer register storing a first pointer pointing to a row corresponding to the first axis and a second pointer register storing a second pointer pointing to a column corresponding to the second axis.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: May 24, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-Jung Ryu, Sung-Bae Park, Woong Seo, Young-Chul Cho, Jeong-Wook Kim, Moo-Kyoung Chung, Ho-Young Kim
  • Patent number: 9275722
    Abstract: A memory device include a memory array, a transmitter suitable for outputting data to the outside of the memory device, and a data bus suitable for transmitting data of a selected memory cell in the memory array to the transmitter during a read operation. When successive read commands for the same memory cell are applied, data transmission from the memory array to the data bus is blocked, and data previously loaded in the data bus is outputted through the transmitter.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: March 1, 2016
    Assignee: SK Hynix Inc.
    Inventors: Jung-Hwan Ji, Ki-Chon Park, Jin-Youp Cha, Jin-Hee Cho
  • Patent number: 9244857
    Abstract: A lookup circuit evaluates hash functions that map keys to addresses in lookup tables. The circuit may include multiple hash function sub-circuits, each of which applies a respective hash function to an input key value, producing a hash value. Each hash function sub-circuit (which may include a programmable hash table) may multiply bit vectors representing key values by a bit matrix and add a constant bit vector to the results. Each hash value may be used to access a location in a lookup table in memory to obtain its contents (e.g., a key and associated data). The circuit may include a selection sub-circuit that selects the data of one of the identified locations as an output of the lookup circuit (e.g., one whose key matches the input key). The circuit may modify obtained data prior to its selection and may output a signal indicating the validity of input keys.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: January 26, 2016
    Assignee: Oracle International Corporation
    Inventors: Guy L. Steele, Jr., David R. Chase, Nils Gura
  • Patent number: 9153331
    Abstract: A data storage device includes a memory and a controller and may perform a method that includes updating, in a controller of the data storage device, a value of a particular write/erase (W/E) counter of a set of counters in response to an erase operation to a particular region of the non-volatile memory that is tracked by the particular W/E counter and that includes a storage element that is tracked by a particular cell erase counter of the set of counters. The method includes, in response to the value of the particular W/E counter indicating that a count of erase operations to the particular region satisfies a first threshold, initiating a remedial action to the particular region of the non-volatile memory at least partially based on the value of the particular cell erase counter.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 6, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Manuel Antonio D'Abreu, Dimitris Pantelakis, Stephen Skala
  • Patent number: 9070469
    Abstract: A memory device that, in certain embodiments, includes a memory element coupled to a bit-line and a quantizing circuit coupled to the memory element via the bit-line. In some embodiments, the quantizing circuit includes an analog-to-digital converter having an input and output and a digital filter that includes memory. The input of the analog-to-digital converter may be coupled to the bit-line, and the output of the analog-to-digital converter may be coupled to the digital filter.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: June 30, 2015
    Assignee: Micron Technology, Inc.
    Inventor: R. Jacob Baker
  • Patent number: 9042194
    Abstract: A refresh method for a volatile memory device includes refreshing memory cells of a first set of rows of an array at a first refresh rate having a first refresh period, the first refresh rate being a lower rate having a longer refresh period than a second refresh rate having a second refresh period, wherein each memory cell in the first set of rows of the array has a retention time longer than the first refresh period; and refreshing memory cells of a second set of rows of the array at a third refresh rate having a third refresh period, the third refresh rate being a higher rate having a shorter refresh period than the second refresh rate having the second refresh period, wherein at least one memory cell of each row of the second set of rows has a retention time longer than the third refresh period and shorter than the first refresh period. The second refresh period corresponds to a refresh period defined in a standard for the volatile memory device.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul-Woo Park, Joo-Sun Choi, Hong-Sun Hwang
  • Patent number: 9036418
    Abstract: A read voltage generation circuit includes a register unit configured to store an initial read voltage code, a counter circuit configured to change a read voltage code in every read-retry operation, wherein an initial value of the read voltage code is the initial read voltage code; and a voltage generation circuit configured to generate a read voltage corresponding to a read voltage code produced by the counter circuit.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: May 19, 2015
    Assignee: SK hynix Inc.
    Inventor: Seung-Min Oh
  • Patent number: 9007839
    Abstract: A method of reading a nonvolatile memory device comprises applying a read voltage to a memory cell array to read selected memory cells, counting a number of the selected memory cells that have a threshold voltage higher or lower than the read voltage, and comparing the counted number with a reference value to determine a number of bits stored in the selected memory cells.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Sang Lee, Moosung Kim
  • Patent number: 9007862
    Abstract: Components of a memory system, such as a memory controller and a memory device, that reduce delay in exiting self-refresh mode by controlling the refresh timing of the memory device. The memory device includes a memory core. An interface circuit of the memory device receives an external refresh signal indicating an intermittent refresh event. A refresh circuit of the memory device generates an internal refresh signal indicating an internal refresh event of the memory device. A refresh control circuit of the memory device performs a refresh operation on a portion of the memory core responsive to the internal refresh event, at a time relative to the intermittent refresh event indicated by the external refresh signal.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: April 14, 2015
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Brent Haukness, Ian P. Shaeffer, James E. Harris
  • Patent number: 8988962
    Abstract: A refresh circuit and a semiconductor memory device including the refresh circuit are disclosed. The refresh circuit includes a mode register, a refresh controller and a multiplexer circuit. The mode register generates a mode register signal having information relating to a memory bank on which a refresh operation is to be performed. The refresh controller generates a self-refresh active command and a self-refresh address based on a self-refresh command and an oscillation signal. The multiplexer circuit may include a plurality of multiplexers. Each of the multiplexers selects one of an active command and the self-refresh active command in response to bits of the mode register signal. Each of the multiplexers generates a row active signal based on the selected command, and selects one of an external address and the self-refresh address to generate a row address.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Ho Shin, Jung-Bae Lee, Min-Jeung Cho
  • Patent number: 8976621
    Abstract: Subject matter disclosed herein relates to techniques to read memory in a continuous fashion.
    Type: Grant
    Filed: December 24, 2010
    Date of Patent: March 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Yihua Zhang, Jun Shen
  • Patent number: 8971132
    Abstract: The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: March 3, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Kiyohiro Furutani, Seiji Narui
  • Patent number: 8958265
    Abstract: A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: February 17, 2015
    Inventor: Laurence H. Cooke
  • Patent number: 8953403
    Abstract: A semiconductor memory device includes a plurality of banks; a counting block suitable for counting the activation number of the respective banks, and selecting a bank of which the activation number is larger than or equal to a given number; and a refresh control block suitable for performing a normal refresh operation on the banks in response to a refresh command, and performing an additional refresh operation N times on the selected bank, N being a positive integer.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: February 10, 2015
    Assignee: SK Hynix Inc.
    Inventors: Choung-Ki Song, Young-Do Hur, Tae-Woo Kwon
  • Patent number: 8953409
    Abstract: A device includes a control circuit that triggers a first operation every time a specific signal is supplied thereto, and that triggers a second operation in place of the first operation in response to the first specific signal supplied after the number of the first operation performed has reached a predetermined number.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: February 10, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Toru Ishikawa
  • Patent number: 8947954
    Abstract: A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. In another aspect, the two memory cells can be considered a dual bit cell that contains a copying mechanism. There are two interleaved memory planes, assembled from bit cells that contain two bits of information. One bit is the primary bit that corresponds to the normal RAM bit. The second bit is able to receive a copy and hold the primary value. When the copying mechanism is over, the two memory planes may act as two completely independent structures.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: February 3, 2015
    Assignee: Mentor Graphics Corporation
    Inventor: Peer Schmitt
  • Patent number: 8947911
    Abstract: A bit line power implementing circuit is provided, the bit line power implementing circuit has a bit line discharge oscillator to convert the supply voltage to a pulse; a decoder coupled to the bit line discharge oscillator to decode the pulse, and providing a first pulse with a first frequency and a second pulse with a second frequency; a first and a second counters, coupled to the decoder, and receiving the first and the second pulses respectively, and outputting a signal proportional to an average and a minimum read currents respectively; a divider outputting a read current ratio of the average read current to the minimum read current; and a multiplier for multiplying the supply voltage the read current ratio to output a bit line power consumption corresponding to the supply voltage.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: February 3, 2015
    Assignee: United Microelectronics Corp.
    Inventor: Hsi-Wen Chen
  • Patent number: 8934302
    Abstract: A method is provided for operating a nonvolatile memory comprising memory cells stacked on a substrate. The method comprises counting a number of program loops performed in a first program operation of selected memory cells connected to a selected wordline, and controlling an increment of a program voltage between successive program loops of a second program operation of the selected memory cells according to the counted number.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: January 13, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Hun Kwak
  • Patent number: 8929156
    Abstract: A semiconductor memory device includes an internal clock generation unit configured to generate an internal clock including periodic pulses during a period of a test mode; a DQ information signal generation block configured to generate DQ information signals which are sequentially enabled, in response to the internal clock; and a data output block configured to output the DQ information signals to DQ pads during a period of the test mode.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: January 6, 2015
    Assignee: SK Hynix Inc.
    Inventor: Bok Rim Ko
  • Patent number: 8929140
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: January 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Nagashima
  • Patent number: 8902665
    Abstract: A solid state storage system includes a memory area having a plurality of pages and is capable of storing program information about each page. The memory area stores the number of pulse counts applied to each page. A main memory controller receives the program information from the memory area and determines whether to program pages according to the program information. The main memory controller determines whether the program information for a page is at a predetermined amount and if the corresponding page should be programmed again or not.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: December 2, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jin-Chul Kim, Young-Kyun Shin
  • Patent number: 8897093
    Abstract: A controlling method of a connector, the connector, and a memory storage device are provided. The controlling method includes following steps. A first clock signal generated by a first oscillator in the connector is obtained. A second clock signal generated by a second oscillator in the connector is obtained. A frequency shift of the first oscillator is smaller than a frequency shift of the second oscillator. A detection window information corresponding to the second clock signal is corrected according to the first clock signal and the second clock signal. The first oscillator is turned off. A signal stream including a first signal is received. A detection window is generated according to the corrected detection window information and the second clock signal, and whether the first signal is a burst signal is determined according to the detection window. Thereby, the power consumption of the connector is reduced.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: November 25, 2014
    Assignee: Phison Electronics Corp.
    Inventors: Chih-Ming Chen, Ming-Hui Tseng
  • Patent number: 8897084
    Abstract: Techniques are disclosed relating to determining when a data strobe signal is valid for capturing data. In one embodiment, an apparatus is disclosed that includes a memory interface circuit configured to determine an initial time value for capturing data from a memory based on a data strobe signal. In some embodiments, the memory interface circuit may determine this initial time value by reading a known value from memory. In one embodiment, the memory interface circuit further configured to determine an adjusted time value for capturing the data, where the memory interface circuit is configured to determine the adjusted time value by using the initial time value to sample the data strobe signal.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: November 25, 2014
    Assignee: Apple Inc.
    Inventors: Hao Chen, Rakesh L. Notani, Sukalpa Biswas
  • Patent number: 8885438
    Abstract: A startup circuit is disclosed operable to perform a startup operation for an electronic device comprising digital circuitry. The startup circuit comprises a first clock generator operable to generate a first clock comprising a first period, and a second clock generator operable to generate a second clock independent of the first clock. The second clock is operable to clock the digital circuitry and comprises a second period less than the first period. A first counter counts a first number of the second periods over the first period, and the second clock is enabled to clock the digital circuitry in response to the first counter.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: November 11, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventor: Robert P. Ryan
  • Patent number: 8879329
    Abstract: Methods for program verifying, program verify circuits, and memory devices are disclosed. One such method for program verifying includes generating a ramped voltage for a plurality of count values. The ramped voltage is applied to a control gate of a memory cell being program verified. At least a portion of each count value is compared to an indication of a target threshold voltage for the memory cell. When the at least a portion of the count value is equal to the indication of the target threshold voltage indication, sense circuitry is used to check if the memory cell has been activated by the voltage generated by the count. If the memory cell has been activated, an inhibit latch is set to inhibit further programming of the memory cell. If the memory cell has not been activated by the voltage, the memory cell is biased with another programming pulse.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: November 4, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Giovanni Santin, Michele Incarnati
  • Patent number: 8873330
    Abstract: A plurality of address conversion circuits are provided for memory cores respectively, and convert logical address data supplied from outside to physical address data. In an interleave operation, the address conversion circuits output the logical address data as the physical address data without converting the logical address data when a first memory core is to be accessed earlier than a second memory core, whereas output address data obtained by adding a certain value to the logical address data as the physical address data when the second memory core is to be accessed earlier than the first memory core.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumihiro Kono, Kiyotaro Itagaki
  • Patent number: 8873326
    Abstract: A memory device includes a plurality of memory blocks configured to be refreshed in response to respective refresh signals; a command decoder configured to decode an external input command to generate an internal refresh command; a refresh control unit configured to activate a first number of refresh signals corresponding to the first number of memory blocks when the internal refresh command is activated and a first mode is set, and to activate a second number of refresh signals corresponding to the second number of memory blocks when the internal refresh command is activated and a second mode is set, the second number being smaller than the first number; and an address counter configured to change the row address transferred to the memory blocks when a predetermined one of the refresh signals is activated.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: October 28, 2014
    Assignee: SK Hynix Inc.
    Inventor: Yo-Sep Lee
  • Patent number: 8867255
    Abstract: A semiconductor device and method of operation having reduced read time of fuse array information during boot-up operation. When fuse array information is read, only repaired fuse-set information is read such that a read time of the semiconductor memory device is reduced, resulting in an increased read margin.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventors: Joo Hyeon Lee, Jun Hyun Chun, Ho Uk Song
  • Patent number: 8867301
    Abstract: Disclosed herein is a device that includes a command decoder and a latency counter. The command decoder generates a first internal command in response to a first internal clock signal. The latency counter includes: a gate control signal generation unit generating output gate signals in response to a second internal clock signal; delay circuits each receiving an associated one of the output gate signals and generating an associated one of input gate signals; and a command signal latch unit fetching the first internal command in response to one of the input gate signals and outputting the first internal command in response to one of the output gate signals. Each of the delay circuit includes a first delay element that operates on a first power supply voltage and a second delay element that operates on a second power supply voltage different from the first power supply voltage.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: October 21, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Taihei Shido, Chiaki Dono
  • Patent number: 8854917
    Abstract: The column address counter circuit of a semiconductor memory device includes at least one lower bit counter unit configured to generate a first bit of a column address by counting an internal clock, where the first bit is not a most significant bit of the column address, and a most significant counter unit configured to generate the most significant bit of the column address in response to a mask clock, where the mask clock is toggled when the internal clock is toggled by a set number of times.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: October 7, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jee Yul Kim
  • Patent number: 8824219
    Abstract: A semiconductor memory circuit includes: a plurality of memory regions; a plurality of driving units configured to be enabled in response to a plurality of enable signals, respectively, and generate a predetermined voltage used for operations of the plurality of memory regions; and an enable control unit configured to count a control pulse and activate one or more enable signals among the plurality of enable signals.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: September 2, 2014
    Assignee: SK Hynix Inc.
    Inventor: Young Jo Ko
  • Patent number: 8817564
    Abstract: A circuit for sensing a multi-level cell (MLC) comprises a first switch associated with a first read bit, a second switch associated with a second read bit, a first switch control unit to control the first switch in response to a first data bit from a counter, and a second switch control unit to control the second switch in response to a second data bit from the counter.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: August 26, 2014
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Cheng-Hung Tsai
  • Patent number: 8804441
    Abstract: Methods and systems for detection and correction of timing signal drift in memory systems are provided. A start time and an end time of a first time interval is determined with control circuitry such that a last falling edge in a first of a plurality of data strobe sequences received from the memory occurs outside of the first time interval. A start time and an end time of a close-enable time interval is adjusted based at least in part on determining whether a second of the plurality of data strobe sequences occurs within the first time interval. Sampling of data received from the memory is disabled in response to determining that the last falling edge in the second received data strobe sequence occurs within the close-enable time interval.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: August 12, 2014
    Assignee: Marvell International Ltd.
    Inventor: Ross Swanson
  • Patent number: 8804444
    Abstract: A semiconductor device includes a test circuit configured to generate a buffer control signal in response to input data, decode test commands in response to the buffer control signal, and generate test mode signals and a counting enable signal for counting row addresses and column addresses; and a data input/output circuit configured to buffer external commands in response to the buffer control signal and generate the test commands, perform a burn-in test in response to the test mode signals, and perform a read operation for memory cells corresponding to the row addresses and the column addresses.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: August 12, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jin Hee Cho
  • Patent number: 8797821
    Abstract: A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: August 5, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hidetaka Tsuji
  • Patent number: 8797808
    Abstract: A semiconductor device includes: a non-volatile memory unit; a data bus configured to transfer data outputted from the non-volatile memory unit; a selection signal generation unit configured to generate a plurality of selection signals based on a clock; and a plurality of latch sets configured to each be enabled in response to a selection signal that corresponds to the latch set among the selection signals and store the data transferred through the data bus.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: August 5, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jeongsu Jeong
  • Patent number: 8787104
    Abstract: A semiconductor memory device includes a temperature sensor configured to generate a low-temperature signal which is enabled at below first set temperature and a high-temperature signal which is enabled at above second set temperature; a start signal generator configured to receive a refresh command and generate a start signal according to the low-temperature signal; and an address counter configured to count refresh addresses in response to the start signal.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 22, 2014
    Assignee: SK Hynix Inc.
    Inventor: Keun Kook Kim
  • Patent number: 8773889
    Abstract: A semiconductor memory device includes a memory cell array configured of at least a first portion and a second portion each including a plurality of memory cells each with a variable resistor which stores an electrically rewritable resistance value as a data, and a control circuit which controls a first operation including selected one of operations to erase, write and read the data in the first portion and a second operation including selected one of operations to erase, write and read the data in the second portion, the first operation and the second operation being performed in temporally overlapped relation with each other.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Naoya Tokiwa
  • Patent number: 8775701
    Abstract: A source-synchronous capture unit on a receiving circuit includes a first first-in-first-out (FIFO) unit operable to synchronize a write enable signal to generate a synchronized write enable signal that is synchronized with a first free running clock associated with a memory external to the receiving circuit. The write enable sign is generated in response to a read operation by the receiving circuit. The source-synchronous capture unit also includes a second FIFO unit operable to store data from the memory in response to the first free running clock and the synchronized write enable signal, and to output the data in response to a second free running clock associated with the receiving circuit and a read enable signal.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: July 8, 2014
    Assignee: Altera Corporation
    Inventor: Ryan Fung