Timing generator with edge generators, utilizing programmable delays, providing synchronized timing signals at non-integer multiples of a clock signal

Abstract

A system for providing a plurality of synchronous timing signals having period values that are not even multiples of the clock period including a plurality of local edge generators receiving the clock signals, each local generator including local programmable means to count clock signals and provide local outputs upon receiving predetermined clock signals and local programmable delay means for providing a timing signal after a delay interval following each local output, the resolution of the local delay means being greater than that of the clock.

Claims

2. The system of claim 1 wherein said local programmable counting means includes a local counter that counts clock signals and produces an output related to said counted clock signals and a coincidence detector that compares the output of the local counter with an integer number of clock periods corresponding to a desired time value and provides an output to a flip flop, said flip flop being triggered on an immediately following clock signal to provide said local output.

3. The system of claim 2 wherein said coincidence detector is connected to receive said integer number from said first RAM.

5. The system of claim 4 wherein each said lock edge generator comprises means for generating residue values, and wherein said programmable delay means includes a first adder for adding a residue value to a said remainder value to provide a sum as said delay control signal to said delay line.

6. The system of claim 5 wherein said deskew circuit includes a deskew adder for adding said deskew value to the residue and remainder values to provide a sum as said delay control signal to the delay line.

7. The system of claim 6 wherein said means for generating said deskew value is provided by a deskew generator that can vary the deskew value on a cycle-by-cycle basis.

8. A system for providing a plurality of synchronous timing signals having period values that are not even multiples of a clock period comprising

a clock for generating clock signals separated in time by a clock period, and

a plurality of local edge generators connected by respective paths to said clock receiving said clock signals, each said local edge generator including local programmable counting means to provide local outputs upon receiving predetermined clock signals,

means for generating a deskew value to correct for a particular delay in said respective path between said edge generator and said clock, and

local programmable delay means for providing a timing signal after a delay interval following each said local output, said local programmable delay means having a resolution, said local programmable delay means including a deskew circuit for receiving said deskew value, said deskew circuit providing a delay control signal based on said deskew value to said local programmable delay means so that said timing signal is synchronous with timing signals of other local edge generators,

the resolution of said local programmable delay means being greater than that of said clock,

wherein there is a master control circuit that includes said clock and provides master end-of-count pulses and residue values to the local edge generators, said master end-of-count pulses being used to reset said local programmable counting means, said residue values being used by said local programmable delay means in generating said delay control signal.

9. The system of claim 8 wherein said mister control circuit is a period oscillator including master programmable counting means to provide master end-of-count outputs upon receiving predetermined clock signals and master programmable delay means for providing a period output signal after a delay interval following each said master end-of-count output, said master programmable delay means having a resolution, the resolution of said master programmable delay means being greater than that of said clock..Iadd.

10. A method of generating timing pulses in each of a plurality of local circuits in a timing system, said local circuits being included in circuit paths which may have different propagation times wherein the propagation time of a said circuit path may be used as a reference propagation time, the method comprising the steps of:

(a) routing a master clock signal and a period clock signal to each of the plurality of local circuits in conjunction with a digital residue value for each period of the period clock signal representing a delay relative to said period clock signal;

(b) in each local circuit,

(i) generating a programmed delay amount which is expressed as a digital value representing an integer number of periods of the master clock signal and a digital value representing a fractional portion of the master clock signal;

(ii) generating a deskew value which is expressed as at least a digital value representing a fractional portion of the master clock signal, the deskew value being related to the difference in propagation time between said circuit path including the local circuit and a reference propagation time;

(iii) delaying the generation of a timing pulse by a fractional amount of a master clock signal in proportion to at least a combination of the digital residue value, the programmed delay amount which represents a fractional amount of the master clock signal, and the deskew value; and

(iv) delaying the generation of a timing pulse by an integer number of master clock signals in proportion to at least the programmed delay amount representing an integer number of periods of the master clock signal..Iaddend..Iadd.

11. The method of claim 10 wherein the step of delaying the generation of a timing pulse by an integer number of master clock signals comprises delaying the generation of said timing pulse by one or more master clock periods when the combination of the digital residue value, the programmed delay amount which represents a fractional amount of the master clock signal and the deskew value exceeds a full period of the master clock signal..Iaddend.