Abstract: A method for forming a silicon island used for forming a TFT or thin film diode comprises the step of pattering a silicon film with a photoresist mask. In order to prevent the contamination of the semiconductor film due to the photoresist material, a protective film such as silicon oxide is interposed between the semiconductor film and the photoresist film. Also, the protective film is preferably formed by thermal annealing or light annealing in an oxidizing atmosphere.

Abstract: A method of forming a semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprises the following steps. Form over a substrate the combination of a gate oxide layer and a gate layer patterned into gate stacks with sidewalls for an NMOS FET device over a P-well in the substrate and a PMOS FET device over an N-well. Form P− lightly doped S/D regions in the N-well and N− lightly doped S/D regions in the P-well. Form spacers on the sidewalls of the gate stacks. Thereafter form deep N− lightly doped S/D regions in the P-well, and form deep P− lightly doped S/D regions in the N-well. Form heavily doped P++ regions self-aligned with the gate below future P+ S/D sites to be formed self-aligned with the spacers in the N-well, and form heavily doped N++ regions self-aligned with the gate below future N+ S/D sites to be formed self-aligned with the spacers in the P-well.

Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.

Abstract: The method of forming MOS transistors includes the following steps. First, isolation regions are formed in the semiconductor substrate to separate the semiconductor substrate into an ESD protective region and a functional region. A gate insulator layer is formed on the substrate and a polysilicon layer is formed on the gate insulator layer. The polysilicon layer is then patterned to form gate structures on the ESD protective region and the functional region. The semiconductor substrate is doped for forming a first doped region and an insulator layer is formed over the semiconductor substrate. A portion of the insulator layer and a portion of the gate insulator layer are removed to form spacer structures and an insulator block. The semiconductor substrate is doped for forming a second doped region. An insulator opening is defined within the insulator block. The semiconductor substrate is then doped for forming a third doped region.

Abstract: A method of manufacturing a BICMOS integrated circuit including an NPN transistor in a heavily-doped P-type wafer coated with a lightly-doped P-type layer, including the steps of forming an N well of collector of a bipolar transistor; coating the structure with a polysilicon seed layer and opening above collector well portions; growing undoped silicon, then P-type doped silicon to form a single-crystal silicon base region; depositing an insulating layer and opening it; depositing N-type emitter polysilicon and etching it outside useful areas; etching the base silicon outside useful areas; forming spacers; and forming a collector contact area at the same time as the drain implantation of the N-channel MOS transistors.

Abstract: The channel doping profile of a PMOS field effect transistor consists of a shallow distribution of a P-type dopant as a threshold adjust implant, a deeper distribution of an N-type dopant as an buried channel stop implant and a still deeper implantation of an N-type dopant as an antipunchthrough implant. A junction is formed between the P-type threshold adjust implant and the N-type buried channel stop implant at a relatively shallow depth so that the depth of the buried channel region is limited by the buried channel stop implant, reducing the short channel effect. The channel doping profile is formed so that diffsion of impurities from the channel region to the gate oxide is prevented. The buried channel stop implant is made first through a sacrificial oxide layer. The sacrificial oxide is etched and a gate oxide layer and a thin film of polysilicon are deposited on the surface of the gate oxide.

Abstract: A method for forming planarized shallow trench isolation is described. A pad oxide layer is grown over the surface of a semiconductor substrate. A nitride layer is deposited overlying the pad oxide layer. A plurality of isolation trenches are etched through the nitride and pad oxide layers into the semiconductor substrate wherein there are at least one first wide nitride region between two of the trenches and at least one second narrow nitride region between another two of the trenches. A high density plasma oxide layer is deposited over the nitride layer and within the isolation trenches wherein the high density plasma oxide layer fills the isolation trenches and wherein the high density plasma oxide deposits more thickly in the first region over the wide nitride layer and deposits more thinly in the second region over the narrow nitride layer. A photoresist mask is formed over the high density plasma oxide layer.

Abstract: A method for manufacturing a CMOS semiconductor device having a first conductivity type (1st-type) MOS transistor including a gate electrode made of a 1st-type polysilicon film of high impurity concentration and a second conductivity type (2nd-type) MOS transistor including a gate electrode made of a 2nd-type polysilicon film of high impurity concentration on a single semiconductor substrate, comprising the steps of: forming a polysilicon film on the substrate; forming a first resist mask on the polysilicon film so as to cover a 2nd-type MOS transistor formation region, followed by implanting a 1st-type impurity at a high concentration into the polysilicon film by using the first resist mask; removing the first resist mask; forming a second resist mask on the polysilicon film so as to cover a 1st-type MOS transistor formation region, followed by implanting a 2nd-type impurity at a high concentration into the polysilicon film by using the second resist mask; etching the 2nd-type polysilicon film by a specific

Abstract: A capacitor structure and method. The capacitor (12) comprises a HDC dielectric (40) and upper (44) and lower electrodes. The lower electrode comprises polysilicon(31-32), a diffusion barrier (34) on the polysilicon and an oxygen stable material (36) on the diffusion barrier (34). The oxygen stable material (36) is formed by first forming a disposable dielectric layer (50) patterned and etched to expose the area where the storage node is desired and then depositing the oxygen stable material (36). The oxygen stable material (36) is then either etched back or CMP processed using the disposable dielectric layer (50) as an endpoint. The disposable dielectric layer (50) is then removed. The HDC dielectric (40) is then formed adjacent the oxygen stable material (36).

Abstract: A method for fabricating a capacitor. A first metal layer is formed on a provided substrate. A dielectric film is formed on the first metal layer. The dielectric film can be a mono-layer structure or a multi-layer structure comprising various dielectric materials. A rapid thermal process (RTP), such as a rapid thermal annealing, or a plasma treatment is performed to enhance the quality of the dielectric film. A photolithography and etching process is performed to remove a part of the dielectric film and the first metal layer to expose a part of the inter-layer dielectric layer. The remaining first conductive layer is used as a lower electrode. A conventional interconnect process is performed on the exposed inter-layer dielectric layer and on the dielectric film. For example, a glue layer is formed on the exposed inter-layer dielectric layer and on the dielectric film. A second metal layer is formed on the glue layer.

Abstract: A method of fabricating a CVD Ta2O5/Oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFETs is disclosed. In a first embodiment, the surface of a silicon substrate is reacted in N2O or NO ambient to form an oxynitride layer. Tantalum oxide is next chemical vapor deposited, thus forming a Ta2O5/Oxynitride stacked gate insulator. The stacked gate is then completed by depositing titanium nitride as the gate electrode and then patterning and forming the gate structure. In the second embodiment, a gate oxide is first formed on the silicon substrate. Then the gate oxide layer is nitridated in N2O or NO ambient to form the oxynitridated layer, thus forming a two-step oxynitride layer. The tantalum oxide layer and the titanium nitride gate electrode are formed as in the first embodiment.

Abstract: A process flow for forming a polysilicon-to-polysilicon capacitor performs the capacitor anneal step in a nitrous oxide ambient. As a result, a nitroxide layer forms over heavily doped polysilicon of the upper electrode of the capacitor. This nitroxide layer acts as a barrier against the diffusion of oxygen, preventing further oxidation of the heavily doped polysilicon electrode layer during the subsequent seal oxidation step. The nitroxide barrier layer is readily removed along with the other seal oxide layers immediately before formation of the silicided capacitor electrode contacts, without any attendant danger of overetching of gate oxide or spacer structures. Where the gate polysilicon layer is doped immediately after its formation, an additional capacitor anneal step in a nitrous oxide ambient is necessary to form an additional nitroxide layer.

Abstract: A semiconductor device and a manufacturing method for a hyperfine structure wherein contact of a gate electrode with a side-wall composed of a silicon nitride layer within a contact hole due to an alignment deviation may be prevented. The semiconductor device is structured such that the contact hole is formed in an inter-layer insulating layer and the side-wall is formed along a wall surface within the contact hole. A bottom of the side-wall is composed of a silicon oxide layer or a silicon oxide nitride layer, and an upper portion of the side-wall is formed of a silicon nitride layer.

Abstract: A method for forming a cylinder-shaped capacitor for dynamic random access memories (DRAMs) is disclosed. The method includes forming a silicon layer having a gap therein over a semiconductor substrate, followed by conformably forming a first dielectric layer on the silicon layer. Next, a second dielectric layer is formed on the first dielectric layer, filling the gap. After etching back the second dielectric layer, the first dielectric layer is removed until the silicon layer is exposed. Then the second dielectric layer is removed, and the silicon layer is etched using the first dielectric layer as a mask, thus forming a cylinder-shaped structure of the silicon layer over the substrate.

Abstract: The present invention relates to a method for forming rugged polysilicon capacitance electrodes uses for dynamic random access memory processes is disclosed. The method is capable in reducing process time, enhancing yield, and saving production cost. Wherein, the process of the present invention comprises: firstly, a semiconductor wafer is delivered into a low pressure chemical vapor deposition (LPCVD) tube. Herein, a non-doped or doped amorphous silicon layer is deposited on the surface top of electrodes. A rugged polysilicon capacitance is formed on top of the non-doped or doped amorphous silicon layer by using the methods of rising temperature and decreasing pressure. Then, an ion implantation is applied and follows by a wafer cleaning procedure and an annealing process, wherein those procedures are accomplished after the removal of the wafer from LPCVD tube.

Abstract: The invention provides a semiconductor device, having a variety of functions such as a bistable memory and a logic circuit, in which a MOS semiconductor element, a resonance tunnel diode, a hot electron transistor and the like are formed on a common substrate. An n-type Si layer and a p-type Si layer surrounded with an isolation oxide film are formed on an SOI substrate. A mask oxide film and a gate oxide film are formed, and the n-type Si layer is subjected to crystal anisotropic etching by using the mask oxide film as a mask, so as to change the n-type Si layer into the shape of a thin Si plate. After first and second tunnel oxide films are formed on side faces of this n-type Si layer, first and second polysilicon electrodes of a resonance tunnel diode and a polysilicon electrode working as a gate electrode of a MOS semiconductor element are formed out of a common polysilicon film. Thus, a Si/SiO2 type quantum device can be manufactured with ease at a low cost.

Abstract: A method is provided for forming a split-gate flash memory cell having a sharp beak of poly which substantially improves the programming erase speed of the cell. The sharp beak is formed through an extra and judicious wet etch of the polyoxide formed after the oxidation of the first polysilicon layer. The extra oxide dip causes the polyoxide to be removed peripherally thus forming a re-entrant cavity along the edge of the floating gate. The re-entrant beak is such that it does not get damaged during the subsequent process steps and is especially suited for cell sizes smaller than 0.35 micrometers.

Abstract: A method for fabricating a tunnel window in an EEPROM cell that reduces or eliminates the initial active region overlap yet still compensates for tunnel window misalignment. The inventive method accomplishes this by removing a portion of the field oxide layer surrounding an initial active region before depositing the BN+ diffusion layer. This step is performed in order to enlarge the area in which the BN+ diffusion layer is formed to beyond the perimeter of the tunnel window forming a final active region. As a result, the method of the present invention ensures that the tunnel window is fully enclosed by the BN+ diffusion layer despite any tunnel window misalignment that may occur. Reducing the initial active region creates an EEPROM cell with a reduced cell pitch while increasing its coupling ratio.

Abstract: A technique for forming an integrated circuit device having a self-aligned gate layer. The method includes a variety of steps such as providing a substrate (217), which is commonly a silicon wafer. Field isolation regions (201) including a first isolation region and a second isolation region are defined in the semiconductor substrate. A recessed region is defined between the first and second isolation regions. The isolation regions (201) are made using a local oxidation of silicon process, which is commonly called LOCOS, but can be others. A thickness of material (205) such as polysilicon is deposited overlying or on the first isolation region, the second isolation region, and the active region. A step of selectively removing portions of the thickness of material overlying portions of the first isolation region and the second isolation region is performed, where the removing step forms a substantially planar material region in the recessed region.

Abstract: A method for forming a stacked gate of a flash memory cell is described. A first dielectric layer, a conductive layer and a silicon nitride layer are sequentially formed over a substrate. A photoresist pattern is formed over the silicon nitride layer. The silicon nitride layer, conductive layer, first dielectric layer and substrate are etched by using the photoresist pattern as an etching mask until forming a plurality of trenches in the substrate. An insulating layer is formed over the substrate, wherein the insulating layer has a surface level between a top surface of the conductive layer and a bottom surface of the conductive layer. A conductive spacer is formed on the sidewalls of the conductive layer and silicon nitride layer, wherein the conductive spacer and conductive layer serve as a first gate conductive layer. The silicon nitride layer is removed. A second dielectric layer and a second gate conductive layer are formed over the substrate.

Abstract: First and second dummy structures (201 and 202) are formed over a semiconductor device substrate (10). In one embodiment, portions of the first dummy structure (201) are removed and replaced with a first conductive material (64) to form a first gate electrode (71) and portions of second dummy structure (202) are removed and replaced with a second conductive material (84) to form a second gate electrode (91). In an alternate embodiment, the dummy structures (201 and 202) are formed using a first conductive material (164) that is used to form the first electrode (71). The second electrode is then formed by removing the first conductive material (164) from dummy structures (202) and replacing it with a second conductive material (84). In accordance with embodiments of the present invention, the first conductive material and the second conductive material are different conductive materials.

Abstract: A process for significantly reducing the thickness of and improving the quality and uniformity of a native oxide film which is formed during the formation of MOSFET devices on a silicon wafer in a dual thickness gate oxide process. The native oxide forms on exposed silicon surfaces after selectively etching away regions of a first thicker gate oxide and prior to growing a thinner gate oxide. The thinner gate oxide used to form high performance devices is between about 15 and 50 Å thick. The native oxide which forms on the exposed silicon surfaces has an initial thickness of about 10 Å. After the selective regions have been patterned the wafer is cleaned using a totally HF free cleaning procedure and subjected to a low pressure rapid thermal annealing between about 600 and 1,050° C. in an ambient of H2 and N2. The residual oxide thickness is reduced to about 4 Å with an accompanying improvement in thickness uniformity and oxide quality.

Abstract: The invention relates to a method of manufacturing a field effect transistor, in particular a discrete field effect transistor, comprising a source region (1) and a drain region (2) and, between said regions, a channel region (4) above which a gate region (3) is located. The gate region (3) is formed by applying an insulating layer (5) to the semiconductor body and providing this insulating layer with a stepped portion (6) in the thickness direction, whereafter a conductive layer (30) is applied to the surface of the semiconductor body (10), which layer is substantially removed again by etching, so that a part (3A) of the conductive layer (30), which part forms part of the gate region (3) and which lies against the stepped portion (6), remains intact.

Abstract: A process is described for forming a buried, or pocket, ion implant in a semiconductor device. In particular, said pocket is limited to only the drain side of a field effect transistor. To achieve this the photoresist that is used to protect the source and drain regions during ion implantation is located at different distances from the gate pedestal. The photoresist on the source side is placed closer to the gate pedestal than it is on the drain side. As a result, when ions arrive at the surface at a sufficiently shallow angle to be able to penetrate the semiconductor regions immediately beneath the gate oxide, photoresist at the source side blocks the beam while the photoresist on the drain side is far enough away from the gate not to intercept the beam. Thus, a single asymmetrically located pocket is formed in a single step.

Abstract: A method of source/drain and LDD implantation using a single implantation step is described. A gate electrode is formed in an active area on surface of a semiconductor substrate. The gate electrode and the semiconductor substrate are covered with a resist layer. The resist layer in the active area is exposed to lithography source, such as electron-beam direct writing, or other process, wherein a portion of the resist layer overlying the planned LDD regions is exposed to a first energy and a portion of the resist layer overlying the planned source/drain regions is exposed to a second energy greater than the first energy and wherein a portion of the resist layer outside of the active area is not exposed. The resist layer is developed to leave a resist mask having a first thickness in areas not exposed and to leave a resist mask having a second thickness in areas exposed to the first energy and to leave no resist mask in areas exposed to the second energy.

Abstract: To provide a method of fabricating a MOS-type transistor of a LDD structure with a gate electrode made of molybdenum, which brings about a reduction in the amount of overlapping between the gate electrode and source/drain, a gate electrode is made of molybdenum and forms a first pattern. The first pattern is subject to nitriding process to form a second pattern. The second pattern includes an interior electrode layer and a nitride layer located outside of the electrode layer. The thickness of the nitride layer corresponds to the amount of overlapping between the second pattern and source/drain.

Abstract: A semiconductor device in which a salicide structure is applied to a buried gate transistor to largely reduce a difference of level or height in a element and to reduce the resistance of a gate electrode and a source/drain structure, thus enabling reliable high speed operations while maintaining high performance. For manufacturing the semiconductor device, a silicon substrate is formed with a groove for a buried gate. A gate insulating film is formed on the bottom surface of the groove. Then, side-wall insulating films are formed on both side surfaces of the groove in a large thickness as compared with that of the gate insulating film. Next, after a gate electrode is formed from a polycrystalline silicon film, a source/drain structure is formed in the silicon substrate through the gate electrode and the side-wall insulating film. Then, a Ti film is formed and annealed to form silicide layers on the gate electrode and on the source/drain electrodes, thus completing a salicide structure.

Abstract: A method is provided for forming high quality nitride sidewall spacers laterally adjacent to the opposed sidewall surfaces of a gate conductor dielectrically spaced above a semiconductor substrate. In an embodiment, a polysilicon gate conductor is provided which is arranged between a pair of opposed sidewall surfaces upon a gate dielectric. The gate dielectric is arranged upon a semiconductor substrate. Nitride is deposited from a high density plasma source across exposed surfaces of the substrate and the gate conductor. The high density plasma source may be generated within an ECR or ICP reactor containing a gas bearing N2 and SiH4. The energy and flux of electrons, ions, and radicals within the plasma are strictly controlled by the magnetic field such that a substantially stoichiometric and contaminant-free nitride is deposited upon the semiconductor topography. Thereafter, the nitride is anisotropically etched so as to form nitride spacers laterally adjacent the sidewall surfaces of the gate conductor.

Abstract: A method for doping a poly depleted semiconductor transistor, the semiconductor transistor including a gate region, a source region adjacent the gate region and a drain region adjacent the gate region and opposite the source region, the method comprising steps of exposing the gate region to a first ion implantation and shielding the gate region from a second ion implantation step.

Abstract: Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include removing carbonaceous residues by performing a hydrogen ion plasma treatment.

Abstract: A heterojunction bipolar transistor (20) is provided with a silicon (Si) base region (34) that forms a semiconductor junction with a multilayer emitter (38) having a thin gallium arsenide (GaAs) emitter layer (36) proximate the base region (34) and a distal gallium phosphide emitter layer (40). The GaAs emitter layer (36) is sufficiently thin, preferably less than 200 Å, so as to be coherently strained.

Abstract: A process for forming a thick-film resistor whose dimensions can be accurately obtained, thereby yielding a precise resistance value. The method includes providing on a substrate a photoimageable layer that preferably forms a permanent dielectric layer of a multilayer structure. An opening is photodefined in the surface of the photoimageable layer, and then overfilled with an electrically-resistive material to form a resistive mass having an excess portion that lies on the surface of the photoimageable layer surrounding the opening. Following curing which causes the surface of the resistive material to become recessed below the surface of the photoimageable layer, the excess portion of the resistive mass is removed, preferably by abrading or a similar operation, such that the lateral dimensions of the resistive mass are determined by the lateral dimensions of the opening in the photoimageable layer.

Abstract: A process for increasing the sheet resistance and lowering the temperature coefficient of resistance of a thin film resistor deposited on a wafer, the process comprising ramping the temperature of the wafer to an annealing temperature above the decomposition temperature of the thin film resistor using a radiant heat source such that the wafer reaches the annealing temperature within a ramp up time of from about 5 to 10 seconds, and annealing the wafer at the annealing temperature for an annealing period of from about 50 to 85 seconds.

Abstract: A method for fabricating a DRAM cell, on a SOI layer, is described, featuring the incorporation of a two dimensional, trench capacitor structure, for increased DRAM cell signal, and the use of a polysilicon storage node structure to connect the SOI layer to the semiconductor substrate, to eliminate a floating body effect. A two dimensional trench is created by initially forming a vertical trench, through the SOI layer, through the underlying insulator layer, and into the semiconductor substrate. An isotropic etch is than performed to laterally remove a specific amount of insulator layer, exposed in the vertical trench, creating the lateral component of the two dimensional trench. A deposited polysilicon layer, coating the sides of the two dimensional trench, is used as the storage node structure, for the two dimensional, trench capacitor structure, while also connecting the SOI layer to the semiconductor substrate.

Abstract: A method of fabricating a capacitor on a substrate. The method includes sequentially forming a first dielectric layer and an etching barrier layer on the substrate, the etching barrier layer and the first dielectric layer having an opening formed therein. A conductive layer is formed on the etching barrier layer and fills the opening. The conductive layer is patterned to form a raised region on the conductive layer. Isolation spacers and conductive spacers are alternately formed on sidewalls of the raised region. The isolation spacers and the conductive spacers are concentrically layered. The isolation spacers are used as masks to remove the conductive spacers and a portion of the patterned conductive layer. The etching barrier layer is used as an etch stop layer. The isolation spacers and a portion of the patterned conductive layer are removed. The remaining patterned conductive layer forms a storage electrode of the capacitor.

Abstract: A method for forming a capacitor includes forming a substrate having a node location to which electrical connection to a capacitor is to be made; forming an inner capacitor plate over the node location, the inner capacitor plate having an exposed sidewall; forming an oxidation barrier layer over the exposed inner capacitor plate sidewall; forming a capacitor dielectric plate over the inner capacitor plate, the oxidation barrier layer restricting oxidation of the inner capacitor plate sidewall during formation of the capacitor dielectric plate; and forming an outer capacitor plate over the capacitor dielectric plate. A capacitor is further described which includes an inner capacitor plate having at least one sidewall; an oxidation barrier layer positioned in covering relation relative to the at least one sidewall; a capacitor dielectric plate positioned over the inner capacitor plate; and an outer capacitor plate positioned over the capacitor dielectric plate.

Abstract: Integrated circuit capacitor lower electrodes are fabricated by forming a plurality of spaced-apart contact pads on an integrated circuit substrate. A first insulating layer is formed on the integrated circuit substrate including on the contact pads. A plurality of spaced-apart conductive lines is formed on the first insulating layer that are laterally offset from the plurality of spaced-apart contact pads. A second insulating layer is formed on the first insulating layer including on the conductive lines. A buffer layer comprising material that is different from the second insulating layer, is formed on the second insulating layer. Openings are formed that extend through the buffer layer, through the second insulating layer and into the first insulating layer between the conductive lines to expose the contact pads. A conductive layer is formed in the openings and on the buffer layer. The conductive layer is etched between the openings to form the capacitor lower electrodes.

Abstract: A semiconductor device structure with differential field oxide thicknesses. A single field oxidation step produces a nitrided field oxide region (322) that is thinner than a non-nitrided field oxide region (324). The bird's beak (326) of the nitrided field oxide (322) encroaches less into the active cell region than the bird's beak (328) of the thicker non-nitrided field oxide (324). The differential field oxide thicknesses allow isolation of multi-voltage integrated circuit devices, such as flash memory devices, while increasing available active cell area for a given design rule.

Abstract: A method of fabricating a shallow trench isolation (STI). The method forms a spin-on glass layer after removing a pad oxide layer in a STI process in order to fill a cavity formed in an oxide layer in the vicinity of an interface between a STI and a substrate. Then, a planarization process is performed, and the spin-on glass layer is annealed into an oxide layer with good thermal stability.

Abstract: A method for implementing shallow trench isolation by using a non-critical chemical mechanical polishing method in an integrated circuit. After STI regions are etched and insulator oxide layer is deposited and etched back, a planarized insulator oxide layer is formed. The corners of silicon nitride layer over active area are exposed after the etch back step. Then, a silicon nitride cap layer is deposited. A non-critical photoresist patterning is used to expose the bigger active regions. Afterward, the cap layer on the bigger active regions is removed. Thereafter, a non-critical CMP process is used to polish the cap layer on the smaller active regions, then the insulator oxide layer under cap layer is removed by wet etch. Subsequently, a wet etch is used to remove the cap layer and silicon nitride layer. Finally, the shallow trench isolation process is completed after the pad oxide is removed.

Abstract: The present invention relates to a device isolation structure and a device solation method in a semiconductor power IC. The device isolation structure according to the present invention includes: a semiconductor substrate including a high voltage region and a low voltage region; a trench overlapping the high voltage device region of the semiconductor substrate and an interfacing region formed between the high voltage device region and the low voltage device region; a fourth insulating film, a fifth insulating film, and a conductive film sequentially layered in the trench; a first insulating film pattern formed on the semiconductor substrate including the trench; and field insulating films respectively formed on the trench and on a portion of an upper surface of the semiconductor substrate which is exposed out of the first insulating film pattern.

Abstract: A wafer of semiconductor material for fabricating integrated devices, including a stack of superimposed layers including first and second monocrystalline silicon layers separated by an intermediate insulating layer made of a material selected from the group comprising silicon carbide, silicon nitride and ceramic materials. An oxide bond layer is provided between the intermediate layer and the second silicon layer. The wafer is fabricated by forming the intermediate insulating layer on the first silicon layer in a heated vacuum chamber; depositing the oxide layer; and superimposing the second silicon layer. When the stack of silicon, insulating material, oxide and silicon layers is heat treated, the oxide reacts so as to bond the insulating layer to the second silicon layer. As a ceramic material beryllium oxide, aluminium nitride, boron nitride and alumina may be used.

Abstract: In order to provide a semiconductor substrate that can be an SOI substrate suitable for production of high-frequency transistor, the semiconductor substrate is produced by a method of producing the semiconductor substrate having a step of bonding a first base having a semiconductor layer region to a second base and a step of removing the first base while leaving the semiconductor layer region on the second base, wherein a magnitude relation between the concentration of a p-type impurity and the concentration of an n-type impurity in the bonding atmosphere is established according to the composition of the second base.

Abstract: The invention provides a semiconductor wafer cleaving method and apparatus which are used to obtain an ideal vertical cleaved plane of semiconductor wafers. A semiconductor wafer (1) having a scribing mark (2) inscribed on the surface is set on fulcrum members (6a and 6b). The fulcrum members (6a and 6b) are left-right symmetrical centering around the scribing mark (2) and parallel to the scribing mark (2). Fulcrum members (4a and 4b) are disposed left-right symmetrically centering around the scribing mark (2) and in parallel to the scribing mark (2) on the upper side of the semiconductor wafer (1). The fulcrum members (4a and 4b) are disposed outside the fulcrum members (6a and 6b). Load is applied from the fulcrum members (4a and 4b) side, wherein fulcrum forces are caused to operate from the respective fulcrum members (4a, 4b, 6a and 6b) onto the semiconductor wafer (1).

Abstract: An integrated circuit is formed containing a metal-oxide ferroelectric thin film. An voltage-cycling recovery process is conducted to reverse the degradation of ferroelectric properties caused by hydrogen. The voltage-cycling recovery process is conducted by applying from 104 to 1011 voltage cycles with a voltage amplitude of from 1 to 15 volts. Conducting voltage-cycling at a higher temperature in the range 30-200° C. enhances recovery. Preferably the metal oxide thin film comprises layered superlattice material. Preferably the layered superlattice material comprises strontium bismuth tantalate or strontium bismuth tantalum niobate. If the integrated circuit manufacture includes a forming-gas anneal, then the voltage-cycling recovery process is performed after the forming-gas anneal.

Abstract: A process for producing an epitaxial layer with laterally varying doping includes the following steps: (a) applying a patterned insulator layer to a semiconductor body; (b) growing a first epitaxial layer on the semiconductor body and the patterned insulator layer so that monocrystalline regions are formed over the semiconductor body and polycrystalline regions are formed over the patterned insulator layer, the angle of inclination (&agr;) of the interface between the monocrystalline regions and the polycrystalline regions depending on the grain size of the polycrystalline regions; (c) removing the polycrystalline regions and the insulator layer, and (d) growing a second epitaxial layer which, together with the monocrystalline regions of the first epitaxial layer, forms the epitaxial layer.

Abstract: A semiconductor structure including a silicon wafer having silicon regions, and at least one GexSi1−x region integrated within the silicon regions. The silicon and GexSi1−x regions can be substantially coplanar surfaces. The structure can include at least one electronic device configured in the silicon regions, and at least one electronic device of III-V materials configured in said at least one GexSi1−x region. The structure can be, for example, an integrated III-V/Si semiconductor microchip. In accordance with another embodiment of the invention there is provided a method of fabricating a semiconductor structure, including providing a silicon wafer with a surface; forming a pattern of vias within the surface of the wafer; and depositing regions of GexSi1−x within the vias. The method can include the step of processing the wafer so that the wafer and GexSi1−x regions have substantially coplanar surfaces.

Abstract: A MOS transistor has a gate electrode (33) having a T-shaped cross-section. The gate length is defined in a first structuring step by a spacer technique. The area of the gate electrode in the upper region is defined in a second structuring step. The MOS transistor can be produced with a channel length of less than 100 nm.

Abstract: The present invention is to provide a method for fabricating a semiconductor device, including the steps of: (a) forming an insulating layer on a semiconductor substrate; (b) selectively removing the insulating layer and then forming an opening and the residual insulating layer on a bottom of the opening; (c) removing the residual insulating layer by wet etching in order to expose the semiconductor substrate; and (d) burying a conductive layer in the opening and then forming a conductive layer pattern connected to the semiconductor substrate.

Abstract: A method for forming a polysilicon gate electrode. A semiconductor is provided. A gate oxide layer, a partially doped polysilicon layer and an undoped polysilicon are sequentially formed over the semiconductor substrate. The undoped polysilicon layer, the partially doped polysilicon layer and the gate oxide layer are patterned to form a gate electrode.