Patents Issued in January 9, 2001
-
Patent number: 6171940Abstract: A method for forming semiconductor devices having small dimension gate structures is disclosed. The present invention includes a photoresist shrink process and an organic material layer having low dielectric constant in between the polysilicon layer and the anti-reflection layer.Type: GrantFiled: October 1, 1999Date of Patent: January 9, 2001Assignee: United Microelectronics Corp.Inventor: Jui-Tsen Huang
-
Patent number: 6171941Abstract: A method for fabricating a capacitor of a semiconductor memory device includes forming a titanium aluminum nitride layer, satisfying Ti1-xAlxN, where x<1, as a diffusion inhibiting film on a platinum upper layer for forming the capacitor's upper electrode.Type: GrantFiled: December 13, 1999Date of Patent: January 9, 2001Assignee: Hyundai Electronic Industries Co., Ltd.Inventors: Dae-gyu Park, Sang-hyeob Lee
-
Patent number: 6171942Abstract: Conductive lines are formed in integrated circuit memories using a Silicide blocking layer that is self-aligned. The Silicide blocking layer is self-aligned by etching an electrically insulating layer that is formed between a electrically conductive lines on a substrate in an integrated circuit memory. The etching removes the electrically insulating layer from the outer surfaces of the electrically conductive lines, but leaves a portion of the electrically insulating layer on the substrate between the electrically conductive lines. The portion of the electrically insulating layer remaining on the substrate may prevent the formation of a Silicide film on the substrate during a heating step used to form contacts on the outer surfaces of the electrically conductive lines. The self-aligned Silicide blocking layer may allow a reduction in the number of steps in the fabrication of the contacts and reduce the need to align a mask to the substrate to form the Silicide blocking layer.Type: GrantFiled: April 1, 1999Date of Patent: January 9, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Duck-Hyung Lee, Jong-Woo Park
-
Patent number: 6171943Abstract: A method is provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). In one embodiment, a titanium precursor and a silicon precursor are contacted in the presence of hydrogen, to form titanium silicide. In another embodiment, a titanium precursor contacts silicon to form to form titanium silicide.Type: GrantFiled: August 19, 1999Date of Patent: January 9, 2001Assignee: Micron, Technology, Inc.Inventors: Trung T. Doan, Gurtej Singh Sandhu, Kirk Prall, Sujit Sharan
-
Patent number: 6171944Abstract: A method for bringing up lower level metal nodes of multi-layered IC devices (200) includes a step of boring a passage (210) down through the obstructing or non-target metal layers (220) exposing these layers, through the Inter Layer Dielectric layers (230), stopping at the target metal layer (240), and a step of depositing Gallium implanted insulator (250, 260) forming a node structure (280) with a conductive core (250) and an insulative sheath (260). The conductive core (250) brings up the target metal node or layer (240) and the insulative sheath (260) isolates the exposed non-target metal nodes or layers (220) from the target metal node (240) and the conductive core (250).Type: GrantFiled: May 7, 1998Date of Patent: January 9, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Xia Li, Glen Gilfeather
-
Patent number: 6171945Abstract: A method and apparatus for depositing nano-porous low dielectric constant films by reaction of a silicon hydride containing compound or mixture optionally having thermally labile organic groups with a peroxide compound on the surface of a substrate. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a foam structure. The nano-porous silicon oxide based films are useful for filling gaps between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures. Preferred nano-porous silicon oxide based films are produced by reaction of 1,3,5-trisilanacyclohexane, bis(formyloxysilano)methane, or bis(glyoxylylsilano)methane and hydrogen peroxide followed by a cure/anneal that includes a gradual increase in temperature.Type: GrantFiled: October 22, 1998Date of Patent: January 9, 2001Assignee: Applied Materials, Inc.Inventors: Robert P. Mandal, David Cheung, Wai-Fan Yau
-
Patent number: 6171946Abstract: A method of forming a multilayered pattern in an electronic part wherein a pattern of multilayer wiring is formed via insulating layers in which a pattern for a succeeding layer is formed by adjusting to a position and a configuration of the pattern which was already formed by recognizing a position and configuration of the pattern.Type: GrantFiled: July 17, 1997Date of Patent: January 9, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Masahide Tsukamoto
-
Patent number: 6171947Abstract: In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, the substrate and interconnect lines are annealed prior to deposition of an ILD. A post annealing SiON layer is formed by using plasma-enhanced chemical vapor deposition. The deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, with the gases being dispensed at regulated flow rates and being energized by a radio frequency power source. The plasma reacts to form SiON which is deposited on a semiconductor substrate. Additionally, during deposition, minor adjustments are made to deposition temperature and process pressure to control the optical characteristics of the SiON layer. The SiON layer is tested for acceptable optical properties and acceptable SiON layers are coated with a SiO2 layer to complete formation of the ILD. Once the ILD is formed the substrate is in readiness for further processing.Type: GrantFiled: December 8, 1998Date of Patent: January 9, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Suzette K. Pangrle, Paul R. Besser, Minh Van Ngo, Stephan Keetai Park, Susan Tovar
-
Patent number: 6171948Abstract: A semiconductor processing method for filling structural gaps includes depositing a substantially boron free silicon oxide comprising material at a first average deposition rate over an exposed semiconductive material in a gap between wordline constructions and at a second average deposition rate less than the first average deposition rate over the wordline constructions. A reduced gap having a second aspect ratio less than or equal to a first aspect ratio of the original gap may be provided. An integrated circuit includes a pair of wordline constructions separated by a gap therebetween in areas where the wordline constructions do not cover an underlying semiconductive substrate. A layer of substantially boron free silicon oxide material has a first thickness over the substrate within the gap and has a second thickness less than the first thickness over the wordline constructions.Type: GrantFiled: November 2, 1999Date of Patent: January 9, 2001Assignee: Micron Technology, Inc.Inventor: Chris W. Hill
-
Patent number: 6171949Abstract: A method for manufacturing an integrated circuit using damascene processes is provided in which conductive material surfaces subject to chemical-mechanical polishing are passivated after polishing with a dry, low energy, ion implantation passivating process to prevent oxidation and to eliminate a high dielectric constant protective layer. In particular, copper conductive material is subject to nitrogen implantation at or below 100 KeV to produce a protective copper nitride.Type: GrantFiled: June 9, 1999Date of Patent: January 9, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Lu You, Shekhar Pramanick
-
Patent number: 6171950Abstract: A method for forming a multilevel interconnection between a polycide layer and a polysilicon layer is disclosed. The multilevel interconnection comprises: forming a first impurity-containing conductive layer on a semiconductor substrate; forming a first silicide layer, having a first region thinner than a second region, on the first impurity-containing conductive layer; forming an interlayer dielectric layer in other than the first region; forming a contact hole for exposing the first silicide layer of the first region; and connecting a second impurity-containing conductive layer to the first silicide layer through the contact hole.Type: GrantFiled: June 11, 1999Date of Patent: January 9, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-jae Lee, Soo-cheol Lee
-
Patent number: 6171951Abstract: A dual damascene manufacturing method includes utilizing a low dielectric constant material to form the dielectric layers and to prevent current due to the reduced line width. An implanting step is performed on the dielectric layers to reduce the incoherence and fragility of the dielectric layers, to densify the dielectric layers and to protect the dielectric layers from damage in the subsequent processes. The present invention utilizes the hard mask layer formed over the dielectric layer to reduce the difficulty of the depositing process of the barrier layer. The openings formed within the hard mask layer are broad at the top and narrow at the bottom. so that the barrier layer is more easily deposited into the opening and the subsequent deposition step of the conductive material layer is easily performed. Moreover, the hard mask layer can be utilized as the etching stop layer in the CMP process.Type: GrantFiled: October 30, 1998Date of Patent: January 9, 2001Assignee: United Microelectronic Corp.Inventors: Tzung-Han Lee, Tse-Yi Lu
-
Patent number: 6171952Abstract: A method for forming a metallization layer (30). A first layer (14) is formed outwardly from a semiconductor substrate (10). Contact vias (16) are formed through the first layer (14) to the semiconductor substrate (10). A second layer (20) is formed outwardly from the first layer (14). Portions of the second layer (20) are selectively removed such that the remaining portion of the second layer (20) defines the layout of the metallization layer (30) and the contact vias (16). The first and second layers (14) and (20) are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer (20). Further, metal ions deposited on the first layer (14) during a positive duty cycle are removed from the first layer (14) during a negative duty cycle.Type: GrantFiled: March 2, 2000Date of Patent: January 9, 2001Assignee: Micron Technology, Inc.Inventors: Gurtej Sandhu Sandhu, Chris Chang Yu
-
Patent number: 6171953Abstract: A semiconductor device having a barrier film comprising an extremely thin film formed of one or more monolayers each comprised of a two-dimensional array of metal atoms. In one exemplary aspect, the barrier film is used for preventing the diffusion of atoms of another material, such as a copper conductor, into a substrate, such as a semiconducting material or an insulating material. In one mode of making the semiconductor device, the barrier film is formed by depositing a precursor, such as a metal halide (e.g., BaF2), onto the substrate material, and then annealing the resulting film on the substrate material to remove all of the constituents of the temporary heteroepitaxial film except for a monolayer of metal atoms left behind as attached to the surface of the substrate. A conductor, such as copper, deposited onto the barrier film is effectively prevented from diffusing into the substrate material even when the barrier film is only one or several monolayers in thickness.Type: GrantFiled: December 18, 1998Date of Patent: January 9, 2001Assignee: The United States of America as represented by the Secretary of the NavyInventors: Michael F. Stumborg, Francisco Santiago, Tak Kin Chu, Kevin A. Boulais
-
Patent number: 6171954Abstract: A method of forming self-aligned contact comprises the steps of forming a cap layer on top of a gate structure. Then, sidewall spacers are formed on each side of the gate structure, while a self-aligned contact opening is formed above the source/drain region. Next, a polysilicon plug that couples electrically with the source/drain region is formed inside the self-aligned contact opening. A metallic material is deposited to fill the self-aligned contact opening, thereby forming a metal plug. The polysilicon plug and the metal plug together form a self-aligned contact. Alternatively, a polysilicon plug that couples electrically with the source/drain region is formed inside the self-aligned contact opening, and then a non-metallic material is deposited to fill the self-aligned contact opening thereby forming a stud. Subsequently, the stud is removed to form an opening and then a metal plug is formed in the opening. Hence, a self-aligned contact is again formed.Type: GrantFiled: October 1, 1998Date of Patent: January 9, 2001Assignee: United Microelectronics Corp.Inventor: Chen-Chung Hsu
-
Patent number: 6171955Abstract: A method is described for forming a hemispherical grained silicon structure. A patterned amorphous silicon layer is formed over a wafer. The amorphous silicon layer is etched by an etching step with a mixed solution including a hydrofluoric solution and an oxidizing agent. A cleaning step is performed with the hydrofluoric solution. An annealing step is performed to form the hemispherical grained silicon structure.Type: GrantFiled: February 8, 1999Date of Patent: January 9, 2001Assignee: United Semiconductor Corp.Inventor: Shih-Ching Chen
-
Patent number: 6171956Abstract: The method includes forming a metal layer over a substrate. Subsequently, a discrete dot masking is deposited on the surface of the metal layer. A discrete rugged polysilicon or hemispherical grained silicon (HSG-Si) can be chosen as the discrete dot masking. The source gas used to form the discrete rugged polysilicon includes Si2H6 at a temperature of about 400 to 450° C. An anisotropically etching step is performed to etch the metal layer by using the discrete dot masking as an etching mask, thereby forming a surface pattern formed thereon. Then, the discrete dot masking is removed. The metal layer is patterned to a conductive line pattern. An organic material layer with low dielectric constant is formed on the patterned metal layer. A silicon oxide layer is successively formed on the organic material layer, followed by polishing the silicon oxide layer using a chemical mechanical polishing (CMP).Type: GrantFiled: September 8, 1999Date of Patent: January 9, 2001Assignee: Worldwide Semiconductor Manufacturing Corp.Inventor: Chine-Gie Lou
-
Patent number: 6171957Abstract: After a copper film is formed so as to cover a wiring connection hole in an interlayer insulating film of a semiconductor device, an oxidation preventive film for preventing oxidation of copper is formed on the copper film while maintaining a high vacuum atmosphere of 1.33×10−3 Pa or less, and copper of the copper film is pressure-introduced into a void of the wiring connection hole by using a high-temperature, high-pressure inert gas. The oxidation preventive film is a silicon nitride film or a metal film such as a titanium film. The copper film is formed by sputtering by using, as a target, copper having purity of 99.999 wt % (5N) or higher. The amount of impurity gases contained in the high-pressure inert gas is set at 50 vpm or less.Type: GrantFiled: January 20, 1998Date of Patent: January 9, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Kazuyoshi Maekawa
-
Patent number: 6171958Abstract: A process for preparing a diffusion barrier on a semiconductor substrate which comprises: conducting remote plasma-enhanced metal organic chemical vapor deposition of a thin film of TiNx on said substrate using an organotitanium compound under a flow of H2 plasma, wherein x ranges from 0.1 to 1.5, provides a TiNx thin film having a low carbon content and low specific resistivity.Type: GrantFiled: January 14, 1998Date of Patent: January 9, 2001Assignee: Postech Foundation (KR)Inventors: Shi Woo Rhee, Ju Young Yun
-
Patent number: 6171959Abstract: A process for forming a silicided MOS transistor (100) begins by providing source and drain regions (104) and (106) and a gate electrode (110). Silicon nitride spacers (116) are formed adjacent the gate electrode (110). A cobalt layer (118) and an overlying titanium layer (120) are then deposited in contact with the regions (104), (106), and (110). A rapid thermal process (130) is then used to react the titanium, cobalt, and silicon together to form silicide regions (124), (126), and (128), and intermetallic compound layers (132) and (134). The intermetallic compound layers (132) and (134) are then etched using two sequentially-performed wet etch steps (136) and (138). The resulting structure (100) has a nitride spacer (116) and field oxide regions (107) which are free from cobalt residual contamination (38).Type: GrantFiled: January 20, 1998Date of Patent: January 9, 2001Assignee: Motorola, Inc.Inventor: Rajan Nagabushnam
-
Patent number: 6171960Abstract: A method of fabricating copper interconnection is provided comprising forming a dielectric layer with a trench or a via on a semiconductor substrate. A titanium layer is formed on the dielectric layer. A copper layer doped with light silicon is formed in the trench or the via. The copper layer is encapsulated by annealing to make silicon doped in the copper layer diffuse toward the surface of the copper to react with the titanium layer and the gas. It prevents the copper layer from oxidation and diffusion to increase the yield.Type: GrantFiled: April 9, 1998Date of Patent: January 9, 2001Assignee: United Microelectronics Corp.Inventor: Ellis Lee
-
Patent number: 6171961Abstract: To form a wiring electrode having excellent contact function, in covering a contact hole formed in an insulating film, a film of a wiring material comprising aluminum or including aluminum as a major component is firstly formed and on top of the film, a film having an element belonging to 12 through 15 groups as a major component is formed and by carrying out a heating treatment at 400° C. for 0.5 through 2 hr in an atmosphere including hydrogen, the wiring material is provided with fluidity and firm contact is realized.Type: GrantFiled: November 6, 1997Date of Patent: January 9, 2001Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Kunihiko Fukuchi
-
Patent number: 6171962Abstract: An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate without a planarization mask or etch. Embodiments include forming trenches and refilling them with an insulating material which also covers the substrate surface, followed by polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches. A second layer of insulating material is then deposited to fill seams in the insulating material above the small trenches and to fill steps in the insulating material above the large trenches. The insulating material is then planarized.Type: GrantFiled: December 18, 1997Date of Patent: January 9, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Olov Karlsson, Christopher F. Lyons, Basab Bandyopadhyay, Nick Kepler, Larry Wang, Effiong Ibok
-
Patent number: 6171963Abstract: A method for forming a planar structure on a semiconductor substrate is disclosed. The method comprises the steps of: forming an interlayer dielectric atop said substrate; patterning and etching said interlayer dielectric, stopping at said substrate, to form a contact opening; forming a barrier metal layer on the bottom and sidewalls of said contact opening and atop said interlayer dielectric; depositing a conducting layer into said contact opening and atop said barrier metal layer; removing a portion of said conducting layer atop said barrier metal layer, leaving a plug in said contact opening; removing a portion of said barrier layer atop said interlayer dielectric; forming a cap barrier layer on exposed portions of said plug, said barrier metal layer, and said interlayer dielectric; and removing a portion of said cap barrier layer atop said plug.Type: GrantFiled: November 30, 1998Date of Patent: January 9, 2001Assignee: Worldwide Semiconductor Manufacturing CorporationInventor: Chien-Jung Wang
-
Patent number: 6171964Abstract: A method of constructing a conductive via spacer within a dielectric layer located between a first metal layer and a second metal layer includes the steps of depositing a conductive spacer layer within the opening and over the first metal layer. A portion of the conductive spacer layer is removed to leave a conductive spacer within the opening. The second metal layer is deposited over the spacer to complete the connection between the first and second metal layers. The spacer preferably comprises a material selected from the group comprising refractory metal silicides and nitrides. The spacer is preferably tapered and the via may include a glue layer to improve the adherence of the spacer to the dielectric layer.Type: GrantFiled: January 26, 1998Date of Patent: January 9, 2001Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Guy Blalock
-
Patent number: 6171965Abstract: A method for treating a film of material, which can be defined on a substrate, e.g., silicon. The method includes providing a substrate comprising a cleaved surface, which is characterized by a predetermined surface roughness value. The substrate also has a distribution of hydrogen bearing particles defined from the cleaved surface to a region underlying said cleaved surface. The method also includes increasing a temperature of the cleaved surface to greater than about 1,000 Degrees Celsius while maintaining the cleaved surface in a etchant bearing environment to reduce the predetermined surface roughness value by about fifty percent and greater. Preferably, the value can be reduced by about eighty or ninety percent and greater, depending upon the embodiment.Type: GrantFiled: April 21, 1999Date of Patent: January 9, 2001Assignee: Silicon Genesis CorporationInventors: Sien G. Kang, Igor J. Malik
-
Patent number: 6171966Abstract: An improved delineation pattern for epitaxial depositions is created by forming a mask on a single-crystal silicon substrate which leaves an area (10) of the substrate exposed, doping the area with a dopant to create a doped region defined by a periphery, anisotropically, vertically etching the doped region to create a delineation pattern corresponding to the periphery, and then forming an epitaxial layer over the substrate and doped region. The periphery of the delineation pattern has a squared-off delineation step including a first step wall generally perpendicular to the surface of the substrate and a second step wall generally parallel to the surface of the substrate. The squared-off delineation step helps prevent wash-out of the delineation pattern as one or more epitaxial layers are deposited on the substrate.Type: GrantFiled: August 15, 1996Date of Patent: January 9, 2001Assignee: Applied Materials, Inc.Inventors: Thomas E. Deacon, Norma B. Riley
-
Patent number: 6171967Abstract: A metal wire forming method for a semiconductor device includes the step of forming a first insulator film over a substrate having at least a second insulator film formed thereon and a first conductive layer formed on the second insulator film. Next, a photosensitive film is formed on the first insulator film, and the photosensitive film is exposed and developed according to a contact hole pattern. This exposes a portion of the first insulator film, and the exposed portion is then etched using the photosensitive film as a mask to form a contact hole in the first insulator film. The method further includes the steps of exposing and developing the photosensitive film according to a trench pattern which includes the contact hole pattern, and etching the first insulator film using the photosensitive film as the mask so that a trench having a predetermined depth is formed in the first insulator film and the first conductive layer is exposed via the contact hole.Type: GrantFiled: July 11, 1997Date of Patent: January 9, 2001Assignee: LG Semicon Co., Ltd.Inventor: Young-Kwon Jun
-
Patent number: 6171968Abstract: A method of forming damascene structure has a borderless via design. The method forms a first conductive line above a substrate structure, and then forms a first dielectric layer having a via opening that exposes a portion of the first conductive layer. Thereafter, a metallic plug electrically connected to the first conductive line is formed in the via opening. Next, an insulating layer and a second dielectric layer are sequentially formed over the first dielectric layer. Subsequently, the second dielectric and the insulating layer are patterned to form a trench. Then, portions of the insulating layer at the bottom of the trench are removed to form cavity regions. Finally, a second conductive line that connects electrically with the metallic plug is formed.Type: GrantFiled: August 24, 1998Date of Patent: January 9, 2001Assignee: United Microelectronics Corp.Inventor: Chen-Chung Hsu
-
Patent number: 6171969Abstract: A semiconductor device and method having mesas with uniformly-doped regions 18. A semiconductor substrate 10 is uniformly-doped and then, mesas 12 are formed in the semiconductor surface. Advantages of the invention include a mesa 12 having a uniformly-doped surface, solving the problem of non-uniformity of doping density caused by lateral ion straggling found in the prior art. Another advantage of the invention is a structure having evenly-doped mesas yet undoped trenches.Type: GrantFiled: March 11, 1999Date of Patent: January 9, 2001Assignee: Texas Instruments IncorporatedInventor: Keith A. Joyner
-
Patent number: 6171970Abstract: A method for etching a platinum surface 200. The method includes the step of forming a hardmask 202 including titanium, aluminum, and nitrogen on the platinum surface. The hardmask covers portions of the platinum surface. The method further includes removing platinum from uncovered portions of the surface with a plasma including a nitrogen-bearing species. The etch chemistry may also comprise an oxygen-bearing species.Type: GrantFiled: January 27, 1999Date of Patent: January 9, 2001Assignee: Texas Instruments IncorporatedInventors: Guoqiang Xing, Abbas Ali, Theodore S. Moise
-
Patent number: 6171971Abstract: A dielectric wiring structure and method of manufacture therefor. Successively formed wiring layers synergistically combine with subsequently formed sidewall supports spanning two or more layers to form a self supporting air dielectric interconnection matrix. Wires are supported by vertical nitride sidewalls which are, in turn, held in place and supported by the wires. After forming the complete wiring-sidewall structure, SiO2 between and under the wires is removed using gaseous HF at a partial pressure between 5 and 30 Torr. The metal wires may be clad with nitride for short and oxidation protection. Because sidewalls are formed after wiring, with the wiring at each level providing support definition, complex support alignment is unnecessary.Type: GrantFiled: July 30, 1999Date of Patent: January 9, 2001Assignee: International Business Machines CorporationInventor: Wesley Charles Natzle
-
Patent number: 6171972Abstract: A method for forming micromachined devices out of a polycrystalline silicon substrate using deep reactive ion etching to form the micromachined device. The method comprises the steps of providing a bulk material substrate of polycrystalline silicon, and etching the bulk material using deep reactive ion etching to form the micromachined device. The present invention also includes a method for forming a micromachined device comprising the steps of providing a first layer of single crystal silicon and etching a first set of elements on the first layer. The method further includes the steps of providing a second layer of single crystal silicon, etching a second set of elements on the second layer, and joining the first and second layers together such that the crystal planes of the first layer and the second layer are misaligned and such that the first set and the second set of elements are properly aligned.Type: GrantFiled: November 13, 1998Date of Patent: January 9, 2001Assignee: Rosemount Aerospace Inc.Inventors: Mehran Mehregany, Christopher A. Bang, Kevin C. Stark
-
Patent number: 6171973Abstract: A process for etching a gate conductor material in the fabrication of MOS transistors is presented. A hard mask layer composed of silicon oxynitride is formed upon a gate conductor layer. The hard mask layer is preferably patterned using a resin layer. The patterned hard mask layer is preferably used to form a patterned gate conductor. The gate conductor is preferably composed of polycrystalline silicon or a silicon-germanium alloy.Type: GrantFiled: December 11, 1998Date of Patent: January 9, 2001Assignee: France TelecomInventors: Patrick Schiavone, Fr{acute over (e)}d{acute over (e)}ric Gaillard
-
Patent number: 6171974Abstract: A plasma etch process for oxide having high selectivity to silicon is disclosed comprising the use of a mixture of SiF4 and one or more other fluorine-containing etch gases in an etch chamber maintained within a pressure range of from about 1 milliTorr to about 200 milliTorr. Preferably, the etch chamber also contains an exposed silicon surface. The plasma may be generated by a capacitive discharge type plasma generator, if pressures of at least about 50 milliTorr are used, but preferably the plasma is generated by an electromagnetically coupled plasma generator. The high selectivity exhibited by the etch process of the invention permits use of an electromagnetically coupled plasma generator which, in turn, permits operation of the etch process at reduced pressures of preferably from about 1 milliTorr to about 30 milliTorr resulting in the etching of vertical sidewall openings in the oxide layer.Type: GrantFiled: January 24, 1992Date of Patent: January 9, 2001Assignee: Applied Materials, Inc.Inventors: Jeffrey Marks, Jerry Yuen-Kui Wong, David W. Groechel, Peter R. Keswick, Chan-Lon Yang
-
Patent number: 6171975Abstract: In a wet-chemical treatment of a semiconductor substrate with a chemical treatment fluid containing ammonia and hydrogen peroxide, an experiment is carried out in a system where the concentrations of chemical species are known, to experimentally previously determine a relation between an etching rate of an SiO2 film with a mixture of ammonia and hydrogen peroxide and the concentrations of the dissolved chemical species (calculated by a chemical equilibrium analysis) or the temperature of the chemical treatment fluid, and the determined relation is then expressed. The concentrations of the chemical species are calculated by the chemical equilibrium analysis on the basis of values measured by a chemical treatment fluid composition monitor at a suitable interval and values measured by a fluid temperature sensor, and in accordance with the expressed relation, the etching rate of the SiO2 film with the chemical treatment fluid is calculated at the suitable interval.Type: GrantFiled: March 26, 1998Date of Patent: January 9, 2001Assignee: NEC CorporationInventors: Ushio Hase, Kenichi Yamamoto, Ichiro Miyazawa
-
Patent number: 6171976Abstract: A method of chemical-mechanical polishing. A die region and a scribe line region are defined on a wafer. A dummy pattern is formed in the scribe line region. A dielectric layer is formed to cover the dummy pattern and the wafer. The dielectric layer is planarized by chemical-mechanical polishing.Type: GrantFiled: March 2, 1999Date of Patent: January 9, 2001Assignee: United Semiconductor Corp.Inventor: Chih-Hung Cheng
-
Patent number: 6171977Abstract: A semiconductor wafer having an impurity diffusion layer formed in an inner surface of a trench is cleaned. The semiconductor wafer is inserted into a furnace, and NH3 gas is introduced into the furnace in the low-pressure condition to create an atmosphere in which the temperature is set at 800° C. to 1200° C. and the partial pressures of H2O and O2 are set at 1×10−4 Torr or less. A natural oxide film formed on the inner surface of the trench is removed, and substantially at the same time, a thermal nitride film is formed on the impurity diffusion layer. Then, a CVD silicon nitride film is formed on the thermal nitride film without exposing the thermal nitride film to the outside air in the same furnace. Next, a silicon oxide film is formed on the CVD nitride film. As a result, a composite insulative film formed of the thermal nitride film, CVD silicon nitride film and silicon oxide film is obtained. Then, an electrode for the composite insulative film is formed in the trench.Type: GrantFiled: December 30, 1996Date of Patent: January 9, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Kasai, Takashi Suzuki, Takanori Tsuda, Yuuichi Mikata, Hiroshi Akahori, Akihito Yamamoto
-
Patent number: 6171978Abstract: This invention relates to the fabrication of integrated circuit devices and more particularly to an improved, graded, silicon oxynitride process step, in order to form an unconventional dielectric layer, having an adjustable effective dielectric constant, for the purpose of fabricating capacitors for both DRAM and Logic technologies. During the special CVD process for the oxynitride layer, its composition is varied such that three distinct regions are created in the direction of film growth. The dielectric property of the lower region is close to silicon oxide, the dielectric property of the upper region is close to silicon oxynitride and the dielectric property of the intermediate transition zone is between that of silicon oxide and oxynitride.Type: GrantFiled: May 27, 1999Date of Patent: January 9, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Shih-Chi Lin, Fu-Jier Fahn, Jenq-Dong Sheu
-
Patent number: 6171979Abstract: Using a CVD method, there is deposited, on a semiconductor substrate, a first silicon oxide layer on which a porous layer is then deposited. The porous layer is then etched to form a wiring groove. Using a CVD method, a second silicon oxide layer is deposited throughout the surface of the porous layer, and the first and second silicon oxide layers are etched to form a through-hole therein. Then, a conductive layer is deposited throughout the surface of the semiconductor substrate. Then, the conductive layer is subjected to CMP to form a wiring layer composed of the conductive layer.Type: GrantFiled: October 26, 1998Date of Patent: January 9, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Nobuo Aoi
-
Patent number: 6171980Abstract: In a semiconductor device fabrication process, a method of, and apparatus for, coating a semiconductor wafer with polyimide so that excess polyimide is removed from the wafer edge, back side and coating process area and is conveniently drained. The method comprises the injection into the chamber of a developer, such as dilute TMAH, that mixes with the excess polyimide. The soluble mixture of TMAH and excess polyimide may then be drained into a bulk drain, obviating the accumulation of excess polyimide in the coater cup. The method is implemented through an assembly that includes a coater cup, spin chuck disposed within the coater cup, and a pair of nozzles intruding into the coater cup at a lower portion of the cup. A fist nozzle operates to inject developing fluid onto the back side of the wafer in the cup, and a second nozzle, positioned nearer the center of the cup and the spin chuck, operates to inject rinsing fluid.Type: GrantFiled: August 5, 1999Date of Patent: January 9, 2001Assignee: NEC Electronics, Inc.Inventors: Mark J. Crabtree, Joseph T. Siska
-
Patent number: 6171981Abstract: An electrode passivation layer of a semiconductor device and a method for forming the same having improved corrosion-resistance and oxidation-resistance are disclosed, the electrode passivation film including a semiconductor substrate; a conductive layer pattern formed on the semiconductor substrate; and an amorphous passivation film formed on the conductive layer pattern.Type: GrantFiled: March 23, 1998Date of Patent: January 9, 2001Assignee: LG Semicon Co., Ltd.Inventor: Jeong Soo Byun
-
Patent number: 6171982Abstract: An SOI substrate having on the surface thereof a single crystal silicon film formed on an insulator is heat-treated in a hydrogen-containing reducing atmosphere in order to smooth the surface and reduce the boron concentration without damaging the film thickness uniformity in a single wafer and among different wafers. The method is characterized in that the single crystal silicon film is arranged opposite to a member of non-oxidized silicon for heat treatment.Type: GrantFiled: December 22, 1998Date of Patent: January 9, 2001Assignee: Canon Kabushiki KaishaInventor: Nobuhiko Sato
-
Patent number: 6171983Abstract: This invention relates to fluorochemical compositions, their preparation and their use as water- and oil-repellents, and substrates treated therewith. The fluorochemical composition comprises a mixture of fluorochemical compounds and/or polymers, each component having at least two fluoroaliphatic groups and a large hydrocarbon moiety such as derived from dimer acids, and the polymer having at least one fluoroaliphatic group and a plurality of said hydrocarbon moiety.Type: GrantFiled: September 8, 1999Date of Patent: January 9, 2001Assignee: 3M Innovative Properties CompanyInventors: Dirk M. Coppens, Richard J. Grant
-
Patent number: 6171984Abstract: This invention relates to generally to geosynthetic materials which can be used for earthen reinforcement, and more particularly to a novel geosynthetic material exhibiting less strain under an initial tensile load then presently available geosynthetic materials.Type: GrantFiled: December 3, 1997Date of Patent: January 9, 2001Assignee: PPG Industries Ohio, Inc.Inventors: John N. Paulson, Mikhail M. Girgis, Jeffrey A. Neubauer, Narasimhan Raghupathi
-
Patent number: 6171985Abstract: A low trauma pressure-sensitive adhesive coated substrate comprising a sheet material, tape or laminate structure designed to adhere to skin or like surfaces. The pressure-sensitive adhesive layer of this adhesive coated substrate is a fibrous adhesive layer generally having a basis weight of from 5 to 200 g/m2 applied to a conformable backing or substrate. The fibrous adhesive layer has a textured outer face and persistent porosity between discrete adhesive fibers. Generally, the fibrous adhesive layer has a MVTR (measured by ASTM E 96-80 at 40° C.) of at least 1000 g/m2/day, preferably at least 6000 g/m2/day.Type: GrantFiled: December 1, 1997Date of Patent: January 9, 2001Assignee: 3M Innovative Properties CompanyInventors: Eugene G. Joseph, Richard Ferber, Donald Battles, Joseph Tucker
-
Patent number: 6171986Abstract: A process for making bioactive glasses is described including preparing a reaction mixture of reactants capable of forming a sol-gel, aging the reaction mixture, near equilibrium drying a gel resulting from the reaction mixture, and heating the -near equilibrium-dried gel described. Also described are near equilibrium-dried bioactive glass compositions.Type: GrantFiled: January 13, 1998Date of Patent: January 9, 2001Assignee: USBiomaterials Corp.Inventors: Jipin Zhong, David C. Greenspan
-
Patent number: 6171987Abstract: A glass composition comprising, in mole percent of the total composition: glass-forming compounds in a total amount of 75 to 85%, wherein said glass forming compounds comprise 40 to 65% SiO2, 10 to 20% Bi2O3 and 0.1 to 3% Al2O3, and glass modifiers in a total amount of 15 to 25%, wherein said glass modifiers comprise 1 to 23 % ZnO, 0.1 to 5% CuO, 0.1 to 5 CaO and 0.1 to 2% MgO, thick film formulations containing said composition and uses thereof.Type: GrantFiled: August 28, 1998Date of Patent: January 9, 2001Assignee: Ben-Gurion University of the NegevInventor: Jacob Hormadaly
-
Patent number: 6171988Abstract: The dielectric constant of low loss tangent glass-ceramic compositions, such as cordierite-based glass ceramics, is modified over a range by selective addition of high dielectric constant ceramics, such as titanates, tantalates and carbides and metals, such as copper. The low loss tangent is retained or improved over a range of frequencies, and the low CTE of the glass-ceramic is maintained. BaTiO3, SrTiO3 and Ta2O5 produce the most effective results.Type: GrantFiled: July 30, 1999Date of Patent: January 9, 2001Assignee: International Business Machines CorporationInventors: Benjamin V. Fasano, Robert A. Rita
-
Patent number: 6171989Abstract: A silver-colored sintered product having excellent corrosion resistance containing titanium, carbon and boron as indispensable constituent elements, and including in the sintered product composition a titanium boride phase or a boride phase which contains titanium as a chief metal element and a titanium carbide phase or a carbide phase which contains titanium as a chief metal element and a method of producing the same. The sintered product has a flexural strength of not smaller than 700 MPa, a Vickers' hardness of not smaller than 9.0 GPa and a fracture toughness of not smaller than 5.0 MPa·m½.Type: GrantFiled: June 19, 1997Date of Patent: January 9, 2001Assignee: Kyocera CorporationInventor: Nobuo Yoshida