Patents Issued in February 20, 2001
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Patent number: 6191024Abstract: An apparatus is provided for manufacturing a semiconductor package of the type in which a gap between a semiconductor chip and a mount board is filled with a resin. The apparatus includes resin supply means for supplying the resin along one side of the semiconductor chip, and resin supply control means for controlling the amount of resin supplied by the resin supply means such that more resin is supplied near the central portion of the semiconductor chip than near the end portions of the semiconductor chip. Also provided is a method that includes the steps of connecting the semiconductor chip and the mount board, and supplying the resin along one side of the semiconductor chip in such a manner that more resin is supplied near a central portion of the semiconductor chip than near the end portions of the semiconductor chip.Type: GrantFiled: April 20, 1999Date of Patent: February 20, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Takahito Nakazawa, Hiroshi Nomura, Yumiko Ohshima
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Patent number: 6191025Abstract: A method of fabricating a damascene structure for copper conductors. Layers of first, second, and third dielectric are formed on a silicon substrate having devices formed therein. The second dielectric will subsequently act as an etch stop. The third dielectric is a sacrificial layer used to protect the second dielectric. Contact holes are then etched in the layers of first, second, and third dielectric. A first barrier metal and a first conductor metal are then deposited filling the contact hole. The first barrier metal and first conductor metal are then removed down to a level between the original top surface of the layer of third dielectric and the top surface of the second dielectric using a method such as chemical mechanical polishing. The sacrificial third dielectric protects the layer of second dielectric during the chemical mechanical polishing. A layer of fourth dielectric is then deposited.Type: GrantFiled: July 8, 1999Date of Patent: February 20, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chung-Shi Liu, Chen-Hua Yu
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Patent number: 6191026Abstract: A semiconductor manufacturing process with improved gap fill capabilities is provided by a three step process of FSG deposition/etchback/FSG deposition. A first layer of FSG is partially deposited over a metal layer. An argon sputter etchback step is then carried out to etch out excess deposition material. Finally, a second layer of FSG is deposited to complete the gap fill process.Type: GrantFiled: January 9, 1996Date of Patent: February 20, 2001Assignee: Applied Materials, Inc.Inventors: Virendra V. S. Rana, Andrew Conners, Anand Gupta, Xin Guo, Soonil Hong
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Patent number: 6191027Abstract: A method of fabricating a semiconductor device include the steps of: providing a substrate having an insulating layer thereon; forming a connection hole including a first sub-hole and a second sub-hole mutually connected in the insulating layer, wherein the first sub-hole has a first diameter and the second sub-hole has a second diameter larger than the first diameter; forming a first conductive layer over the substrate; removing the first conductive to a thickness so as to form a side wall spacer film on a side wall of the second sub-hole and a plug film in the first sub-hole; forming a barrier metal layer over the substrate to cover the side wall spacer and the plug film; forming a second conductive layer over the substrate to fill space in the connection hole; and chemical mechanical polishing the second conductive layer.Type: GrantFiled: September 2, 1999Date of Patent: February 20, 2001Assignee: Yamaha CorporationInventor: Masayoshi Omura
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Patent number: 6191028Abstract: A method of patterning a dielectric layer. On a substrate having a metal wiring layer formed thereon, a dielectric layer and a masking layer are formed. A cap insulation layer is formed on the masking layer before patterning the dielectric layer. In addition, a dual damasecence process is used for patterning the dielectric layer.Type: GrantFiled: April 14, 1998Date of Patent: February 20, 2001Assignee: United Microelectronics, CorpInventors: Yimin Huang, Tri-Rung Yew
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Patent number: 6191029Abstract: A damascene process is described. An opening is formed in a dielectric layer. The opening is filled with a conductive plug. The conductive plug is etched back to substantially reduce the thickness of the conductive plug in the dielectric layer. A conformal top barrier layer is formed over the conductive plug.Type: GrantFiled: September 9, 1999Date of Patent: February 20, 2001Assignees: United Silicon Incorporated, United Microelectronics Corp.Inventors: Hsi-Mao Hsiao, Chun-Lung Chen, Shin-Fa Lin
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Patent number: 6191030Abstract: In a photo-lithographic step for providing contact points to lower layers of a semiconductor device, an anti-reflective coating (ARC) layer, such as FLARE 2.0™, is used to provide a good contact points to an underlayer. After the contact points are made, the anti-reflective coating layer is removed, with the removal being performed in a same step in which a photo-resist is removed from the semiconductor device. In an alternative configuration, the ARC layer remains in the semiconductor device after the fabrication process is competed, thereby acting as an interlayer dielectric during operation of the semiconductor device.Type: GrantFiled: November 5, 1999Date of Patent: February 20, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Ramkumar Subramanian, Suzette K. Pangrle, John G. Pellerin, Ernesto A. Gallardo
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Patent number: 6191031Abstract: Upon forming a groove and a connection hole by a dual damascene process, there is a problem in that the connection hole has a bowing shape, and it is difficult to form a shape of the connection hole in a good and stable manner. A process for producing a multi-layer wiring structure is provided, which comprises a step of forming an inter level dielectric film 15 covering a lower layer wiring 14; a step of forming a connection hole 16 in the inter level dielectric film 15 to reach the lower layer wiring 14; a step of forming an inter metal dielectric film 17 filling the connection hole 16 on the inter level dielectric film 15, with an insulating material having an etching rate larger than an etching rate of the inter level dielectric film 15; and a step of forming a concave part 18 in the inter metal dielectric film 17, and selectively re-opening the connection hole 16 with respect to the inter level dielectric film in such a manner that the connection hole is continuous to the concave part 18.Type: GrantFiled: September 14, 1999Date of Patent: February 20, 2001Assignee: Sony CorporationInventors: Mitsuru Taguchi, Shingo Kadomura
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Patent number: 6191032Abstract: It has been observed that Si introduced into an Al metal line of an Al, Ti, and Si-containing layer stack of an integrated circuit, at concentrations uniformly less than the solid solubility of Si in Al, results in a reduction in Al metal line voiding. Such voiding is a stress induced phenomenon and the introduction of Si appears to reduce stresses in the Al metal lines. By controlling Ti deposition conditions to achieve desired thickness and grain-size characteristics of the Ti underlayer, a self-regulating filter for introduction of Si into the Al metal layer is provided. Si is introduced into the Al metal layer by migration through a suitably deposited Ti layer, rather than during Al layer deposition.Type: GrantFiled: February 4, 1997Date of Patent: February 20, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Don A. Tiffin, William S. Brennan, David Soza, Patrick L. Smith, Allen White, Tim Z. Hossain
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Patent number: 6191033Abstract: Methods of forming, in an integrated circuit, aluminum-silicon contacts with a barrier layer is disclosed. The barrier layer is enhanced by the provision of titanium oxynitride layers adjacent the silicide film formed at the exposed silicon at the bottom of the contact. The titanium oxynitride may be formed by depositing a low density titanium nitride film over a titanium metal layer that is in contact with the silicon in the contact; subsequent exposure to air allows a relatively large amount of oxygen and nitrogen to enter the titanium nitride. A rapid thermal anneal (RTA) both causes silicidation at the contact location and also results in the oxygen and nitrogen being gettered to what was previously the titanium/titanium nitride interface, where the oxygen and nitrogen react with the titanium metal and nitrogen in the atmosphere to form titanium oxynitride. The low density titanium nitride also densifies during the RTA.Type: GrantFiled: November 28, 1997Date of Patent: February 20, 2001Assignee: STMicroelectronics, Inc.Inventors: De-Dui Liao, Yih-Shung Lin
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Patent number: 6191034Abstract: A method of forming minimal gaps or spaces in conductive lines pattern for increasing the density of integrated circuits by first forming an opening in an insulating layer overlying the conductive line by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening, and using the sidewalls as a mask to remove, preferably by etching, a portion of the conductive line pattern substantially equal in size to the reduced opening.Type: GrantFiled: April 5, 1999Date of Patent: February 20, 2001Assignee: Advanced Micro DevicesInventors: Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Christopher A. Spence, Raymond T. Lee, John C. Holst, Stephen C. Horne
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Patent number: 6191035Abstract: In a CVD vacuum chamber processing system for depositing a blanket of refractory material, such as tungsten, upon a frontside of a semiconductor wafer, an inert gas, such as argon is directed to the backside of the wafer in a manner so as to prevent the chamber reaction gases from reacting with polysilicon or other materials on the backside of the wafer as well as to prevent the deposition of the blanket material on the backside of the wafer. This method alleviates the problems of particulate generation and loss of wafer backside datum surface due to the inadvertent buildup of unwanted materials. The wafer is placed on a heater platen and is secured by a specified range of vacuum pressures. The wafer is exposed to specified ranges of chamber pressure during the deposition phase. During the purge phase, the chamber pressure is reduced and the wafer chucking pressure is increased to a specified range. The method is terminated with the equalization of pressure between the front and backside of the wafer.Type: GrantFiled: May 17, 1999Date of Patent: February 20, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Kuo-Hsien Cheng, Chen-Mei Fan
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Patent number: 6191036Abstract: A method of predicting etch efficacy of vias in a semiconductor manufacturing process wherein a photo focus exposure matrix (FEM) array is used as a via etch monitor. The FEM is an array of matrices wherein each array has a different size set of vias. The matrices in the array start with a size approximately double the minimum dimension of vias in the wafer and decrement in size to a size approximately half the minimum dimension.Type: GrantFiled: April 12, 1999Date of Patent: February 20, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Allen S. Yu, Paul J. Steffan, Bharath Rangarajan
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Patent number: 6191037Abstract: Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect of the invention is directed toward a method for planarizing a microelectronic-device substrate assembly by removing material from a surface of the substrate assembly, detecting a first change in drag force between the substrate assembly and a polishing pad indicating that the substrate surface is planar, and identifying a second change in drag force between the substrate assembly and the polishing pad indicating that the planar substrate surface is at the endpoint elevation. After the second change in drag force is identified, the planarization process is stopped.Type: GrantFiled: September 3, 1998Date of Patent: February 20, 2001Assignee: Micron Technology, Inc.Inventors: Karl M. Robinson, Pai Pan
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Patent number: 6191038Abstract: A polishing pad is fixed on a polishing platen mounted to be rotatable. An abrasive supply tube supplies an abrasive onto the polishing pad. A substrate holder is mounted to be rotatable above the polishing pad, holds a substrate to be polished and presses the substrate against the polishing pad, thereby polishing the substrate. A dresser is mounted to be rotatable above the polishing pad, and dresses the polishing pad. A torque detector detects the rotation torque of the polishing platen or the rotation torque of the substrate holder. A dresser controller makes the dresser dress the polishing pad if the rotation torque detected by the torque detector is equal to or smaller than a predetermined value.Type: GrantFiled: September 1, 1998Date of Patent: February 20, 2001Assignee: Matsushita Electronics CorporationInventors: Hideaki Yoshida, Masashi Hamanaka
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Patent number: 6191039Abstract: An improved and new process for fabricating a planarized structure of polysilicon plugs, embedded in silicon oxide has been developed. The planarizing method comprises a two-step CMP process in which the first. CMP step comprises chemical-mechanical polishing using a first polishing slurry which is selective to polysilicon and the second CMP step comprises chemical-mechanical polishing using a second polishing slurry which polishes both polysilicon and silicon oxide. The processing time of the two-step CMP process is significantly less than the processing time of a one-step CMP process requiring an over-polish period. This reduced processing time reduces the cost of the CMP operation and at the same time produces a product with superior planarity and without reliability degradation due to residues of polysilicon.Type: GrantFiled: November 5, 1998Date of Patent: February 20, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chung-Long Chang, Syun-Ming Jang
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Patent number: 6191040Abstract: A surface treatment method for use in integrated circuit fabrication includes providing a substrate assembly having a surface. A liquid is provided adjacent the surface resulting in an interface therebetween. An electrical potential difference is applied across the interface and the surface is treated as the electrical potential difference is applied across the interface. The liquid may be a planarization liquid when the treatment of the surface includes planarizing a substrate assembly or the liquid may be a coating material when the treatment of the surface includes applying a coating material on the surface.Type: GrantFiled: December 17, 1999Date of Patent: February 20, 2001Assignee: Micron Technology, Inc.Inventor: Thomas R. Glass
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Patent number: 6191041Abstract: A method of fabricating semiconductor device. First, a masking layer having an opening pattern is formed on a material layer, and then a mask spacer is formed on the sidewall of the opening. The opening is filled with an insulating layer to cover the material layer exposed by the opening. The masking layer and the mask spacer are removed, allowing the remaining insulating layer to be a mask for defining a pattern of the material layer. Then, the material layer not covered by the insulating layer is removed. The insulating layer is removed again to expose the patterned material layer.Type: GrantFiled: April 16, 1999Date of Patent: February 20, 2001Assignee: United Microelectronics Corp.Inventor: Kuan-Yang Liao
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Patent number: 6191042Abstract: A method of fabricating a node contact opening includes formation of a dielectric layer on a substrate. An opening is formed with C4F8/Ar/CH2F2 as an etchant. A portion of the dielectric layer under the opening is etched with CHF3/CO as an etchant until the substrate is exposed. A node contact opening is formed.Type: GrantFiled: February 8, 1999Date of Patent: February 20, 2001Assignee: United Microelectronics Corp.Inventors: Chien-Hua Tsai, Kuo-Chi Lin
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Patent number: 6191043Abstract: A method of etching a silicon layer in a plasma etching reactor to form an ultra deep opening is disclosed. The method includes the steps of providing a semiconductor substrate including the silicon layer into the plasma etching reactor and flowing an etching gas that includes an oxygen reactant gas, a helium gas, and an inert bombardment-enhancing gas into the plasma etching reactor. The method further includes striking a plasma using the etchant gas chemistry, and then providing an additive gas having SF6 into the plasma etching reactor subsequent to striking the plasma. The method continues with etching an opening at least partially through the silicon layer using this plasma.Type: GrantFiled: April 20, 1999Date of Patent: February 20, 2001Assignee: Lam Research CorporationInventor: Darrell McReynolds
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Patent number: 6191044Abstract: An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having reduced polysilicon gate length, reduced parasitic capacitance and gradual doping profiles is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a polysilicon gate, wherein the polysilicon gate comprises sidewalls with re-entrant profiles, and implanting the semiconductor substrate with a dopant to penetrate portions of the sidewalls to form one or more graded shallow junctions with gradual doping profiles. The gradual doping profiles reduce parasitic capacitance and minimize hot carrier injections.Type: GrantFiled: October 8, 1998Date of Patent: February 20, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Allen S. Yu, Patrick K. Cheung, Paul J. Steffan
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Patent number: 6191045Abstract: In order to provide a method of treating a multilayer including metal and polysilicon for use in a conductor or a gate electrode of a semiconductor device with high accuracy at a high selectivity, the temperature of a sample is maintained at 100° C. or higher at the time of etching a metal film to increase the etch rate of the metal film. In order to suppress the etch rate of a polysilicon film and prevent side etching, an oxygen gas is added to a gas containing a halogen element. In order to suppress the etch rate of a silicon oxide film at the time of etching the polysilicon film, the etching is performed with etch parameters which are divided into those for the metal film and those for the polysilicon film. In the etching performed to the multilayer containing metal and polysilicon, by etching the metal film at a high temperature of 100° C. or higher, the etch rate of the metal film becomes high. Consequently, there is no partial etch residue of the metal film and a barrier film.Type: GrantFiled: April 30, 1999Date of Patent: February 20, 2001Assignee: Hitachi, Ltd.Inventors: Motohiko Yoshigai, Hiroshi Hasegawa, Hiroshi Akiyama, Takafumi Tokunaga, Tadashi Umezawa, Masayuki Kojima, Kazuo Nojiri, Hiroshi Kawakami, Kunihiko Katou
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Patent number: 6191046Abstract: A method of reworking a photoresist used to pattern a semiconductor structure is provided. A dielectric layer is formed over an anti-reflective coating, the anti-reflective coating covering a first underlayer, the first underlayer covering a second underlayer. A first photoresist layer is formed and patterened over the dielectric layer to yield a desired photoresist pattern. An undesired feature in the patterned first photoresist layer is determined. The patterned first photoresist layer is removed. A second photoresist layer is formed and patterned over the dielectric layer. Exposed portions of the dielectric layer, the anti-reflective coating and the first underlayer are etched. A thin photoresist layer is formed over exposed portions of the second underlayer. A CMP process is performed to remove the dielectric layer. The thin photoresist layer is stripped.Type: GrantFiled: March 11, 1999Date of Patent: February 20, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Bhanwar Singh, Sanjay K. Yedur, Bharath Rangarajan
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Patent number: 6191047Abstract: The present invention is directed toward building a microelectronic device in which a semiconductor substrate has thereon an etch buffer layer used in a processing method in which the buffer layer will act as an etch uniformity aid. In a method of making the microelectronic device, a semiconductor substrate is covered with an etch buffer layer and with an insulative layer. A first etch is performed by patterning and etching through a mask. The first etch penetrates the insulative layer, forms a cavity therein, and is selective to the buffer layer so as to expose the buffer layer. A second etch is performed that is selective to the insulative layer and the semiconductor substrate, and is not selective to the buffer layer. The buffer layer can be an insulative material of a type other than the material of the insulative layer or the buffer layer can also be of a conductive material.Type: GrantFiled: June 20, 2000Date of Patent: February 20, 2001Assignee: Micron Technology, Inc.Inventors: Li Li, Zhiqiang Wu, Kunal R. Parekh
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Process for manufacturing composite glass/Si substrates for microwave integrated circuit fabrication
Patent number: 6191048Abstract: A method of forming a glass layer on a substrate of material, for example, silicon, with the glass layer having a coefficient of thermal expansion which substantially matches the substrate. A slurry comprising glass powder and a solvent is applied to the substrate, as for example, by pouring, and a multi-step heating process is carried out with over-pressures of a highly diffusive gas such as hydrogen first, followed by a non-diffusive gas such as nitrogen to thereby create a glass layer having reduced bubbles and fewer bubbles than has heretofore been achieved.Type: GrantFiled: December 31, 1997Date of Patent: February 20, 2001Assignee: The Whitaker CorporationInventors: Kevin Glenn Ressler, Jim-Yong Chi -
Patent number: 6191049Abstract: Method for forming an oxide film in a semiconductor device, is disclosed, which is suitable to form oxide films of different thicknesses in a device region, to which driving voltages of different levels are applied respectively, including the steps of providing a semiconductor substrate, forming an insulating film on the semiconductor substrate, injecting first, and second impurity ions into the semiconductor substrate through the exposed insulating film after masking required regions of the insulating film, removing the insulating film, and forming first, and second oxide films having thicknesses different from each other on regions of the semiconductor substrate having the impurity ions are injected and the impurity ions are not injected thereto, respectively.Type: GrantFiled: December 9, 1998Date of Patent: February 20, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Du Heon Song
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Patent number: 6191050Abstract: A method of forming an interlayer dielectric on a semiconductor device is disclosed. First, a phosphorous doped oxide layer is deposited on the semiconductor device to fill gaps and provide phosphorous for gettering. Then, an undoped oxide layer is deposited and planarized using chemical mechanical polishing (CMP). The undoped oxide layer is denser than the phosphorous doped oxide layer, so the undoped oxide layer can be polished more uniformly than the phosphorous doped oxide layer and can serve as a polish stop for a subsequent tungsten plug polish. Also, the denser undoped oxide layer serves as a more effective moisture barrier than the doped oxide layer. Overall fabrication process complexity can be reduced by performing both oxide depositions in a single operation with no intervening densification or CMP steps.Type: GrantFiled: May 4, 1999Date of Patent: February 20, 2001Assignee: Intel CorporationInventor: Ebrahim Andideh
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Patent number: 6191051Abstract: A gate oxide layer grown on a semiconductor wafer is liable to be contaminated by organic compound particles in a clean room between the growth of the oxide and the next deposition step, and the semiconductor wafer is sealed in ozonic ambience in a vessel coated with an inner wall of ozone-proof material such as chromium oxide so that the ozone decomposes the organic compound particles without producing new particles.Type: GrantFiled: March 17, 1999Date of Patent: February 20, 2001Assignee: NEC CorporationInventor: Yuji Shimizu
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Patent number: 6191052Abstract: The invention provides a method for fabricating ultra-shallow, low resistance junctions. In the preferred embodiment, a nitrogen containing screen oxide layer is formed on an undoped area of a substrate by poly re-oxidation using rapid thermal processing in a nitrogen containing atmosphere. Impurity ions are implanted into the substrate, in the undoped area, through the nitrogen containing screen oxide layer to form lightly doped source and drain regions. A post-implant anneal is performed on the lightly doped source and drain regions using a rapid thermal anneal in a nitrogen containing atmosphere. The nitrogen containing screen oxide layer: prevents surface dopant loss during post implant anneal; prevents gate oxide degradation during ion implantation and screen oxide stripping; and acts as a diffusion barrier, reducing oxygen enhanced diffusion. Alternatively, the poly re-oxidation can be performed in an O2 atmosphere followed by a rapid thermal anneal in a nitrogen containing atmosphere.Type: GrantFiled: January 25, 1999Date of Patent: February 20, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventor: Jyh-Haur Wang
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Patent number: 6191053Abstract: An improved method and apparatus for coating semiconductor substrates with organic photoresist polymers by extruding a ribbon of photoresist in a spiral pattern which covers the entire top surface of the wafer. The invention provides a more uniform photoresist layer and is much more efficient than are current methods in the use of expensive photoresist solutions. A wafer is mounted on a chuck, aligned horizontally and oriented upward. An extrusion head is positioned adjacent to the outer edge of the wafer and above the top surface of the wafer with an extrusion slot aligned radially with respect to the wafer. The wafer is rotated and the extrusion head moved radially toward the center of the wafer while photoresist is extruded out the extrusion slot. The rotation rate of the wafer and the radial speed of the extrusion head are controlled so that the tangential velocity of the extrusion head with respect to the rotating wafer is a constant.Type: GrantFiled: June 10, 1998Date of Patent: February 20, 2001Assignee: Silicon Valley Group, Inc.Inventors: Jung-Hoon Chun, James Derksen, Sangjun Han
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Patent number: 6191054Abstract: In forming a film by a chemical vapor deposition (CVD) process using, as a source material, an organometallic complex dissolved in a solvent, a method for reducing the quantity of carbon compounds mixed into the film is provided. According to this method, a nonpolar solvent is used for dissolving the organometallic complex or an organometallic compound therein. Unlike a polar group contained in a polar solvent, the nonpolar solvent includes no organic molecular group with a large molecular weight to be coordinated with the organometallic complex. Thus, electrical interaction between the organometallic complex and the solvent can be suppressed, and the quantity of carbon compounds mixed into the film can be reduced as a result.Type: GrantFiled: October 6, 1999Date of Patent: February 20, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takashi Ohtsuka, Michihito Ueda
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Patent number: 6191055Abstract: A diaper construction is provided with an external porous reinforcement strip at the front part of the outside of the diaper, which strip provides reinforcement against an adhesive fastening tab and provides an oil contamination tolerant adhesion surface.Type: GrantFiled: October 28, 1998Date of Patent: February 20, 2001Assignee: 3M Innovative Properties CompanyInventors: Charles E. Boyer, III, Robert J. Kinney, Ramsis Gobran, Ruben E. Velasquez Urey, Roland R. Midgley
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Patent number: 6191056Abstract: This invention relates to metallized, particularly aluminized, fabrics which are coated with specific polyurethane finishes and primer coatings comprising novel phosphate-containing primers. Such specific polyurethanes are cross-linked when reacted with the primer coatings and applied in latex form. Upon impregnation within metal-coated fabrics, these particular polyurethanes encapsulate the metal particles and provide vastly improved washfastness properties to the fabrics and thus ensure the retention of substantially all the metal coating within and on the target fabric. The phosphate-containing primer provides remarkably improved adhesion between the metal and the polyurethane for excellent durability and washfastness. The primer compositions as well as the methods of producing a metallized coated with a primed polyurethane encapsulant are also provided.Type: GrantFiled: September 20, 1999Date of Patent: February 20, 2001Assignee: Miliken & CompanyInventors: Kirkland W. Vogt, Kristen K. Arthur
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Patent number: 6191057Abstract: An insulation product includes an elongated batt of fibrous insulation material, and a facing adhered to a major surface of the batt, wherein the facing is a coextruded polymer film of barrier and bonding layers, with the bonding layer having a softening point lower than the softening point of the barrier layer, with the bonding layer being one or more materials of the group consisting of ethylene N-butyl acrylate, ethylene methyl acrylate and ethylene ethyl acrylate, and wherein the facing has been heated to a temperature above the softening point of the bonding layer, but below the softening point of the barrier layer, whereby the facing is adhered to the batt by the attachment of the bonding layer to the fibers in the batt due to the softening of the bonding layer.Type: GrantFiled: August 31, 1999Date of Patent: February 20, 2001Assignee: Owens Corning Fiberglas Technology, Inc.Inventors: Bharat D. Patel, Weigang Qi, Dallas L. Dudgeon, Matthew C. Brokaw, Larry J. Grant, Russell M. Potter
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Patent number: 6191058Abstract: A glass-ceramic substrate for a magnetic disk suitable for use as a contact recording type magnetic disk includes alpha-cristobalite (alpha-SiO2) and lithium disilicate (Li2O·2SiO2) as main crystal phases. The ratio of alpha-cristobalite/lithium disilicate is within a range from 0.20 to less than 0.25, a grain diameter of crystal grains is within a range from 0.1 &mgr;m to 1.0 &mgr;m, surface roughness (Ra) of the substrate after polishing is within a range from 2 Å to 9 Å.Type: GrantFiled: April 29, 1999Date of Patent: February 20, 2001Assignee: Kabushiki Kaisha OharaInventor: Katsuhiko Yamaguchi
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Patent number: 6191059Abstract: Silicate based glass compositions with metal silicide compounds included in the composition as performance modifiers to impart desirable color and improved energy absorbance properties. The metal silicides are added to the batch glass composition in amounts greater than 0.05 weight percent prior to melting. The composition and method result in a finished glass suitable for use in architectural and automotive glazings.Type: GrantFiled: December 30, 1998Date of Patent: February 20, 2001Assignee: Libbey-Owens-Ford Co.Inventor: Srikanth Varanasi
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Patent number: 6191060Abstract: A method for efficient reclamation of metal catalyst species from aqueous extract streams diaryl cabonate synthesis, comprising treating a metal-containing aqueous extract stream of a mixture from the production of diaryl carbonates with a precipitating agent effective to selective precipitate one or more metal catalyst species from the extract. Use of these methods substantially reduces both financial and environmental concerns for the preparation of diaryl carbonates.Type: GrantFiled: December 18, 1998Date of Patent: February 20, 2001Assignee: General Electric CompanyInventor: John Yaw Ofori
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Patent number: 6191061Abstract: In an exhaust gas in an oxygen-rich atmosphere, a method of purifying an exhaust gas and a catalyst for purifying an exhaust gas, which can exhibit a high NOx conversion securely, are provided. Disclosed is a method of purifying an exhaust gas that reduces and purifies NOx in an exhaust gas in an oxygen-rich atmosphere. Here, as a catalyst for purifying an exhaust gas, a loading layer comprising zeolite is loaded with alumina sulfate and cerium sulfate-zirconium composite oxide, and Pt is loaded on these. And, in a temperature range where HC are not oxidized, the HC are adsorbed and held by the zeolite, the HC, which the zeolite releases at the temperature increment, are subjected to cracking by the zeolite, the alumina sulfate and the cerium sulfate-zirconium composite oxide, and the thus produced low-grade HC are turned into reducing agents, thereby reducing and purifying the NOx in the exhaust gas.Type: GrantFiled: December 29, 1999Date of Patent: February 20, 2001Assignee: Toyota Jidosha Kabushiki KaishaInventors: Toshihiro Takada, Hiroaki Takahashi, Masaru Ishii, Saeko Kurachi
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Patent number: 6191062Abstract: A photocatalytic functional material having an excellent photocatalytic activity even by a low temperature heat treatment and having a high mechanical strength of the surface. The photocatalytic functional material of the present invention comprises a surface layer (a photocatalytic functional layer) containing a photocatalyst, an electron trapping metal and a photodegradation-resistant matrix. Though the major proportion of the photocatalyst (TiO2 particles, and the like) in the photocatalytic functional layer are covered with the photodegradation-resistant matrix (a thermosetting resin, and the like), the electron-trapping metal effectively traps the electrons generated by the photocatalytic reaction, retains positive holes and generates active oxygen species, so that the photocatalytic function such as deodorant and antimicrobial activities can be fully exhibited.Type: GrantFiled: May 15, 1997Date of Patent: February 20, 2001Assignee: Toto Ltd.Inventors: Makoto Hayakawa, Makoto Chikuni, Toshiya Watanabe
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Patent number: 6191063Abstract: A catalyst comprising rhodium and a compound of the formula (I) in which m is a number from 1 to 1000; x is a number from 0 to 4; W is a group of the formulae —CH2—CH2—, —CH(CH3)CH2—or —CH2CH(CH3)—; R is hydrogen, a straight-chain or branched C1-C5— alkyl radical; or a group of the formulae where a, b, c, d and e independently of one another are a number from 0 to 1000, at least one of the numbers a, b, c, d and e being greater than 0; R5, R6, R7, R8 and R9 are identical or different and are hydrogen, C1-C5-alkyl or a group of the formula R1 and R2 are identical or different and are a straight-chain, branched or cyclic C1-C30-alkyl radical or C6-10-aryl radical, which is unsubstituted or substituted by from one to five C1-C3-alkyl radicals, and L is C1-C5-alkyl, C1-C5-alkoxy, NO2, NR3R4, where R3 and R4 independently of one another are hydrogen or C1-C4-alkyl, or L is Cl or OH, for hydroformylation reType: GrantFiled: July 1, 1999Date of Patent: February 20, 2001Assignee: Celanese GmbHInventors: Sandra Bogdanovic, Carl-Dieter Frohning, Helmut Bahrmann, Matthias Beller, Steffen Haber, Hans-Jerg Kleiner
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Patent number: 6191064Abstract: A catalyst composition suitable for the conversion of n-butane to butenes. The same catalyst composition that with chlorination is further suitable, when used in the conversion of n-butane, for the production of an increased amount of BTX (benzene-toluene-xylene) and greater selectivity to the production of isobutylenes than attained with the unchlorinated catalyst. A process for the preparation of catalyst compositions suitable for the conversion of n-butane. Use of the catalyst compositions in processes for the conversion of n-butane.Type: GrantFiled: June 22, 2000Date of Patent: February 20, 2001Assignee: Phillips Petroleum CompanyInventors: An-hsiang Wu, Charles A. Drake
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Patent number: 6191065Abstract: A catalyst for the production of alkenylaromatics from alkylaromatics, wherein the catalyst is predominantly iron oxide, an alkali metal compound and less than about 100 ppm of a source for a noble metal, such as palladium, platinum, ruthenium, rhenium, osmium, rhodium or iridium. Additional components of the catalyst may include compounds based on cerium, molybdenum, tungsten and other such promoters. Also a process for the production of alkenylaromatics from alkylaromatics using this catalyst.Type: GrantFiled: January 26, 1999Date of Patent: February 20, 2001Assignees: Nissan Girdler Catalysts Company, United Catalysts Inc.Inventors: David Williams, Yuji Mishima, Andrzej Rokicki, Kazuhiko Shinyama, Dennis Smith
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Patent number: 6191066Abstract: Cobalt catalysts, and processes employing these inventive catalysts, for hydrocarbon synthesis. The inventive catalyst comprises cobalt on an alumina support and is not promoted with any noble or near noble metals. In one aspect of the invention, the alumina support preferably includes a dopant in an amount effective for increasing the activity of the inventive catalyst. The dopant is preferably a titanium dopant. In another aspect of the invention, the cobalt catalyst is preferably reduced in the presence of hydrogen at a water vapor partial pressure effective to increase the activity of the cobalt catalyst for hydrocarbon synthesis. The water vapor partial pressure is preferably in the range of from 0 to about 0.1 atmospheres.Type: GrantFiled: May 26, 1999Date of Patent: February 20, 2001Assignee: Energy International CorporationInventors: Alan H. Singleton, Rachid Oukaci, James G. Goodwin
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Patent number: 6191067Abstract: A continuous fiber of titania are made having an average diameter per a monofilament of from 5 to 50 &mgr;m, which has a BET specific surface area of 10 m2/g or more, a pore volume of 0.05 cc/g or more, a volume of pores having a pore diameter of not less than 10 angstroms being 0.02 cc/g or more and an average tensile strength per a monofilament of 0.1 GPa or more, or which has an average tensile strength per a monofilament of 0.5 GPa or more.Type: GrantFiled: March 10, 2000Date of Patent: February 20, 2001Assignee: Sumitomo Chemical, Ltd.Inventors: Hironobu Koike, Yasuyuki Oki, Yoshiaki Takeuchi
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Patent number: 6191068Abstract: A composition comprising magnesium sulfite, triple super phosphate, and one of limestone and hydroboracite, useful for heavy metal stabilizing, controlling pH and/or removing acid gas from a solid, semi-solid, liquid or gaseous matrix.Type: GrantFiled: February 4, 1999Date of Patent: February 20, 2001Assignee: Bhat Industries, Inc.Inventor: Vasanth K. Bhat
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Patent number: 6191069Abstract: A thermal transfer image receiving sheet comprising a substrate sheet and a dye receptive layer formed on at least one side of said substrate sheet, wherein a hydrophilic porous layer comprising a thermoplastic resin and hydrophilic porous particles, and an electric conductive releasing layer comprising cationic acrylic resin and cellulose acetate, are formed in this order on the opposite side of the surface on which is formed said dye receptive layer of said substrate sheet.Type: GrantFiled: December 1, 1998Date of Patent: February 20, 2001Assignee: Dai Nippon Printing Co., Ltd.Inventor: Yoshihiko Tamura
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Patent number: 6191070Abstract: Pyrimidinone derivatives of the general formula: wherein R1 is hydrogen or alkyl; R2 is haloalkyl; R3 is nitrogen or CH; G is optionally substituted ethylene, trimethylene, or vinylene; and Q is selected from several optionally substituted or heterocyclic-condensed phenyl groups, are useful as the active ingredients of herbicides because of their excellent herbicidal activity.Type: GrantFiled: September 4, 1998Date of Patent: February 20, 2001Assignee: Sumitomo Chemical Company, LimitedInventors: Takashi Komori, Hisayuki Hoshi
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Patent number: 6191071Abstract: The invention concerns novel plant-treatment agents comprising: at least one thermoplastically processable biodegradable polyester amide, optionally in a mixture with one or a plurality of further thermoplastically processable, biodegradable polymer components; at least one agrochemical substance; and optionally additives. The invention further concerns a process for preparing these agents, and their use in the application of agrochemical substances.Type: GrantFiled: May 4, 1999Date of Patent: February 20, 2001Assignee: Bayer AktiengesellschaftInventors: Joachim Simon, Hanns Peter Müller, Uwe Priesnitz, Hans-Georg Rast
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Patent number: 6191072Abstract: A cutting line for a rotating-line trimmer that simultaneously applies herbicide as vegetation is cut. The herbicidal cutting line comprises a flexible cutting-line core (13) herbicidal coating (15) that covers all or part of the line core and a thin protective shield (17) covering all or part of the herbicidal coating. As vegetation is cut, protective shield (17) ruptures exposing herbicidal coating (15) to vegetation. The cutting line is used with existing line trimmers in applications in which vegetation regrowth is objectionable.Type: GrantFiled: December 21, 1998Date of Patent: February 20, 2001Inventor: Niall Duffy
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Patent number: 6191073Abstract: The invention relates to a series of layers containing at least one layer on the basis of REBa2CU3O7-Z or with a comparable crystallographic structure, wherein said layer is connected to a non-superconductive layer. The only material chosen for the non-superconductive layer is material containing atomic components which are chemically compatible with the superconductive material of the high temperature superconductive layer. Such a series of layers enables a multilayer system or also a cryogenic component, e.g. a Josephson contact, to be formed.Type: GrantFiled: February 27, 1999Date of Patent: February 20, 2001Assignee: Forschungszentrum Julich GmbHInventors: Ricardo Hojczyk, Ulrich Poppe, Chunlin Jia