Abstract: There is provided a method for fabricating a ferroelectric capacitor which comprises the steps of: forming a bottom electrode over a substrate on which a predetermined lower structure is formed; forming a thin film of polycrystalline strontium bismuth tantalate (SBT) over the entire structure; forming an amorphous thin film of SBT on the polycrystalline film of SBT; and forming an upper electrode on the amorphous film of SBT. Though the amorphous thin film of SBT is lower in dielectric constant than the polycrystalline thin film of SBT so as not to have the properties of ferroelectric, it does not have crystalline grain boundary and, thus, does not form the path for transferring material. Therefore, the amorphous thin film of SBT can block the path of leakage current. It also results in complement of bismuth lost in the processes of deposition and thermal treatment for crystallization of the ferroelectric film of SBT at a high temperature.

Abstract: The present invention provides a substantially single crystal PGO film with optimal the ferroelectric properties. The PGO film and adjacent electrodes are epitaxially grown to minimize mismatch between the structures. MOCVD deposition methods and RTP annealing procedures permit a PGO film to be epitaxially grown in commercial fabrication processes. These epitaxial ferroelectric have application in FeRAM memory devices. The present invention deposition method epitaxially grows ferroelectric Pb5Ge3O11 thin films along with c-axis orientation.

Abstract: A yield enhancement technique for integrated circuit processing which reduces the deleterious effects of H2O contamination which is absorbed by conventional dielectric films resulting in an undesired subsequent out-diffusion of hydrogen when the integrated circuit die is subsequently subjected to relatively high processing temperatures such as those experienced in CERDIP packaging. The technique disclosed comprises the formation of an interlevel dielectric layer having hydrophilic properties (for example, 7.5% phosphorus doped TEOS) at least partially surrounding a device on the integrated circuit which layer is then subjected to an annealing operation to drive off at least a portion of any moisture present therein.

Abstract: An improved method for specifying and reliably detecting endpoints in processes such as plasma etching, where the signal-to-noise ratio has been severely degraded due to factors such as “cloudy window” and low ratio of reactive surface area to non-reactive surface area. The improved method of the invention samples signals produced by photo sensitive equipment, digitally filters and cross-correlates the data, normalizes the data using an average normalization value, and provides further noise reduction through the use of three modes of endpoint specification and detection. The three modes of endpoint specification and detection require a pre-specified number of consecutive samples to exhibit a certain behavior before the endpoint is deemed detected and the process terminated as a result. The three modes of endpoint specification and detection also permit a very fine control of the etch time by permitting the user to adjust the specified endpoint by gradations of the sampling period.

Abstract: The present invention relates to a method for actually measuring misalignment of a via. According to the invention, a via is formed by etching an inter metal dielectric (IMD) layer using a photoresist with a via pattern as a mask so that via pattern can be accurately transferred to the inter metal dielectric layer. Then a patterned metal interconnection line underlying the inter metal dielectric layer is etched using the patterned inter metal dielectric layer as a mask and followed by a process of stripping the inter metal dielectric layer. After that, an actual misalignment can be detected by measuring relative distance between the patterned metal interconnection line and the via thereon through Scanning Electron Microscopy (SEM), by which overlay specifications for OSI instrument can be verified and adjusted.

Abstract: In one aspect, the invention encompasses a method of forming a semiconductor device. A masking material is formed over a semiconductor substrate. A mold is provided, and the mold has a first pattern defined by projections and valleys between the projection. The masking material is pressed between the mold and the substrate to form a second pattern in the masking material. The second pattern is substantially complementary to the first pattern. The mold is removed from the masking material, and subsequently the masking material is utilized as a mask during etching of the semiconductor substrate. In another aspect, the invention encompasses a method of forming a field emission display. A first material layer is formed over a conductive substrate, and a masking material is formed over the first material layer. A mold is provided over the mask material, and the mask material is pressed between the mold and the first material layer to pattern the masking material.

Abstract: A method for forming an emitter tip for use in a field emission device. An emitter layer is provided over a substrate. The emitter layer is overlaid with a blanket dielectric which is in turn overlaid by a masking layer. In a first etching operation, a masking island and an underlying dielectric island are formed from the masking layer and the blanket dielectric, respectively. These islands serve as a masking structure during subsequent etching processes by which an emitter tip is formed from the emitter layer. Accordingly, a second etching operation is conducted, whereby an etch chemistry which exhibits both isotropic and anisotropic characteristics is used to remove a portion of the emitter layer by undercutting beneath the masking structure. A third etching operation is conducted, wherein the etch chemistry is substantially more anisotropic than the etch chemistry of the second etching operation.

Abstract: This patent describes a method of manufacturing a linear spring electromagnetic grill ink jet print head wherein an array of nozzles are formed on a substrate utilising planar monolithic deposition, lithographic and etching processes. Multiple ink jet heads are formed simultaneously on a single planar substrate such as a silicon wafer. The print heads can be formed utilising standard VLSIULSI processing and can include integrated drive electronics formed on the same substrate. The drive electronics preferably being of a CMOS type. In the final construction, ink can be ejected from the substrate substantially normal to the substrate plane.

Abstract: A p type semiconductor layer, an i type amorphous photoelectric conversion layer and an n type semiconductor layer of an amorphous type photoelectric conversion unit are formed in separate deposition chambers, respectively. A p type semiconductor layer, an i type crystalline photoelectric conversion layer and an n type semiconductor layer of crystalline type photoelectric conversion unit are formed continuously in one deposition chamber. Accordingly, a method of manufacturing a tandem type thin film photoelectric conversion device is obtained by which a tandem type thin film photoelectric conversion device having superior performance and high quality can be formed by a simple apparatus at a low cost with superior productivity.

Abstract: A liquid crystal array and associated drive circuitry are monolithically formed on a silicon-on-sapphire structure, and are fabricated by a method comprising the steps of: a) forming an epitaxial silicon layer on a sapphire substrate to create a silicon-on-sapphire structure; b) ion implanting the epitaxial silicon layer; c) annealing the silicon-on sapphire structure; d) oxidizing the epitaxial silicon layer to form a silicon dioxide layer from a portion of the epitaxial silicon layer so that a thinned epitaxial silicon layer remains; e) removing the silicon dioxide layer to expose the thinned epitaxial silicon layer; f) fabricating an array of pixels from the thinned epitaxial silicon layer wherein each of the pixels includes a liquid crystal capacitor; and g) fabricating integrated circuitry from the thinned epitaxial silicon layer which is operably coupled to modulate the pixels.

Abstract: A method of manufacturing an active panel results in a gate pad being formed so as to prevent being damaged by a probe pin during an auto probe testing process. An active panel made by the method includes a pad including a first conductive material an insulating layer on the pad, at least one contact hole exposing a portion of the pad, the insulating Layer covering a middle portion of the pad and a pad terminal connected to the pad through the at least one contact hole.

Abstract: A light-emitting-diode array is formed on a substrate having an upper layer of a semiconducting material and a lower layer of an insulating or semi-insulating material. The upper layer is divided into blocks by isolation channels that cut completely through the upper layer. The light-emitting diodes, which are formed by selective diffusion of an impurity into the upper layer, are arranged in a single row, with at least two light-emitting diodes in each block of the upper layer. Each block has a block electrode that drives the light-emitting diodes in the block. The row of light-emitting diodes is paralleled by a number of shared lines which cross the isolation channels. Each shared line is coupled to a plurality of light-emitting diodes in different blocks.

Abstract: A metal surface having optimized reflectance is created utilizing the following process steps alone or in combination: 1) performing alloy/sintering of the metal-silicon interface prior to a chemical mechanical polish of the intermetal dielectric before the reflective metal electrode is formed; 2) chemical-mechanical polishing the intermetal dielectric layer again after vias are formed; 3) forming a metal adhesion layer composed of collimated titanium over the underlying dielectric; 4) depositing metal upon the adhesion layer at as low a temperature as feasible to maintain small grain size; 5) depositing at least the first layer of the reflectance enhancing coating on top of the freshly deposited metal prior to etching the metal; and 6) depositing the initial layer of the reflective enhancing coating at a temperature as close as possible to the temperature of formation of the metal electrode layer in order to suppress hillock formation in the metal. Deposition of the REC serves two distinct purposes.

Abstract: To accomplish both higher performance of a crystal and lower cost in a semiconductor member, and to produce a solar cell having a high efficiency and a flexible shape at low cost, the semiconductor member is produced by the following steps, (a) forming a porous layer in the surface region of a substrate, (b) immersing the porous layer into a melting solution in which elements for forming a semiconductor layer to be grown is dissolved, under a reducing atmosphere at a high temperature, to grow a crystal semiconductor layer on the surface of the porous layer, (c) bonding another substrate onto the surface of the substrate on which the porous layer and the semiconductor layer are formed and (d) separating the substrate from the another substrate at the porous layer.

Abstract: An interlace grid array package structure and method of manufacture that utilizes a single sided molding method whose connection with an integrated circuit board is through the underside of the package's plastic body. Therefore, only the alternating contact points arranged into a grid array are exposed for connection after a surface mount operation. Hence, the leads of a lead frame are not protrudent. Therefore, the problem of bent leads is eliminated and the overall package area and thickness is reduced. Since the alternating contact point design of a grid array package increases connection pitch, short-circuiting of neighboring contact points is greatly reduced and a higher yield is obtained.

Abstract: An integrated circuit package for improved warp resistance and heat dissipation is described. The LOC package includes: an integrated circuit die having an upper, active face, and a multi-layered, substantially planar lead frame mounted to the active face of the die, where the lead frame is preferably comprised of layers configured as Cu/INVAR/Cu or Cu/Alloy 42/Cu. The choice of the middle layer of the lead frame is selected to minimize the warping forces on the package such that the coefficient of thermal expansion of the composite lead frame approximates that of silicon. The copper layers of the lead frame provide improved heat dissipation.

Abstract: The specification describes techniques for soldering IC chips, or other components, to interconnection substrates using a patterned epoxy layer to define the solder interconnections. The epoxy layer is photodefined to form openings that expose the bonding sites on the IC chip (or alternatively the interconnect substrate). Solder paste is deposited in the openings. With the IC chip and the interconnect substrate aligned together, the solder paste is heated to reflow the solder and solder bond the IC chip to the substrate. Heating is continued to cure the epoxy, which serves the function of the conventional underfill. The shape of the solder interconnection is defined by the lithographically formed openings, and the interconnections can be made with very fine pitch. The application of the epoxy underfill in this manner assures complete filling of the gap between the IC chip and the interconnection substrate.

Abstract: An electronic component is mounted on a substrate such as a circuit board by means of a soldering process such as reflow soldering. The circuit board has a thermal via hole therethrough to provide a heat dissipation path from the top surface to the bottom surface of the circuit board, for dissipating heat from the electronic component. To prevent molten solder from penetrating through the via hole during the soldering process, the via hole is sealed prior to the soldering process. The via hole is sealed from the bottom surface of the substrate by carrying out a screen printing process including at least two printing passes to print a sealing material into the open hole of the thermal via.

Abstract: The invention concerns a process and a connecting arrangement for producing a chip card, wherein a semiconductor chip on a module is fitted in an opening in a card carrier with the attainment of an electrical and mechanical connection. In accordance with the invention, in place of connections which were hitherto necessary involving a force-locking relationship and/or involving the materials being bonded together, recourse is made to inductive and/or capacitive coupling between the module and the IC-card. For that purpose the module and the card correspondingly have coils and/or capacitive coupling surfaces for signal transmission purposes.

Abstract: A chip scale packaging method is used to package a single-sided substrate and one or more semiconductor chips. The nonconductive surface of the substrate is provided with one or more chip-implanting adhesive areas by stenciling. The adhesive areas are provided with one or more through holes. The chips are implanted in the adhesive areas of the substrate such that the active surface of each chip is in contact with the adhesive area, and that the bonding pads of the active surface of the chip are corresponding in location to the through holes. Upon completion of the chip implantation, the substrate and the implanted chips are heated under pressure before the bonding pads are connected with the conductive surface of the substrate by a plurality of metal bonding wires. The chips and the through holes are subsequently provided with a passivation layer. Finally, the conductive surface of the substrate is implanted with a plurality of spherical bonding points in a grid array fashion.

Abstract: A stacked semiconductor package with ultrahigh integration and a fabrication method thereof according to the present invention are provided to meet the requirements of a system device of being miniaturized and light-weighted and having high efficiency. Also, there is provide a jig for package aligning to fabricate the stacked semiconductor package. The semiconductor package according to the present invention is fabricated by mounting a second-type package including a molding portion and leads exposed at a lower surface of the molding portion of the second-type package on a first-type package including a molding portion and leads, each of being formed in a ‘J’ shape, which are respectively extended out of both sides of the molding portion. Here, uppermost surfaces of the leads of the first-type package are welded by solder to bottom surfaces of the leads of the second-type package.

Abstract: A semiconductor device has an integrated heat sink. A package body encapsulates a die and a leadframe. A heat sink is in thermal contact with the die and the leadframe. The heat sink is encapsulated in the package body. The heat sink has a connector (e.g.

Abstract: A method of forming a semiconductor package that includes at least one structure having a central hole formed at a center portion of the structure, a plurality of outer holes around the center hole, and a plurality of conductor pieces buried in the outer holes; at least one TAB having lead lines extending from sides of the TAB, the TAB having a configuration substantially corresponding to the central hole of the structure and formed over the central hole of the structure; and a molding material covering at least a portion of the TAB.

Abstract: This invention is directed to a semiconductor rectifier chip comprised of a semiconductor dice with at least one P-N junction, and the entire cutting surface of the dice sealed a passivation glass to omite the use of a expansion plate. The rectifier chip is made of negative or positive silicon semiconductor wafer that has been subjected to standard wafer diffusion process to form P30 -N-N+ or N+-P-P+ layer construction, then to cut into a plurality of dices which having a cutting surface, the cutting surface from N30 to P+ of the dice is sealing by the passivation glass to omite the use of the expansion plate, and the electrode ohmic contact metal for soft soldering or hard brazing purpose is made on both sides of the dice simultaneously.

Abstract: Power semiconductor devices having overlapping floating field plates include a primary field plate and a plurality of floating field plates which are formed on an electrically insulating region and capacitively coupled together in series between an active region of a power semiconductor device and a floating field ring. Preferably, the capacitive coupling is achieved by overlapping at least portions of the floating field plates. According to one embodiment, a power semiconductor device comprises a semiconductor substrate having a first region of first conductivity type therein extending to a face thereof and a second region of second conductivity type in the first region of first conductivity type and forming a P-N junction therewith.

Abstract: A process of forming a silicon thin film includes the steps of: irradiating a pulsed rectangular ultraviolet beam on an amorphous or polycrystalline silicon layer formed on a base body, to thereby form a silicon thin film composed of a group of silicon single crystal grains which are each approximately rectangular-shaped and which are arranged in a grid pattern on the base body. In this process, the moved amount of a ultraviolet beam irradiating position in a period from completion of an irradiation of the rectangular ultraviolet beam to starting of the next irradiation of the rectangular ultraviolet beam is specified at 40 &mgr;m or less, and a ratio of the moved amount to a width of the rectangular ultraviolet beam measured in the movement direction thereof is in a range of 0.1 to 5%. Further, a selected orientation of the silicon single crystal grains to the surface of the base body is approximately the <100> direction.

Abstract: A semiconductor device array having silicon device islands isolated from the substrate by an insulator. High array density is achieved by forming source and drain interconnects in the space between the islands. Also disclosed are processes for forming and programming such arrays.

Abstract: The present invention is directed to method for manufacturing a liquid crystal display apparatus in which a thin film transistor formed by successively depositing on a glass substrate a gate electrode, a gate insulating film, an active layer made of amorphous silicon, a source electrode and a drain electrode is used for driving liquid crystal. The method includes steps of: forming the gate electrode by patterning a gate metal layer coating the glass substrate by a wet etching process using an etchant containing cerium ammonium nitrate; removing an etching reaction product adhering on the substrate by washing it with a hydrofluoric acid solution; and forming the gate insulating film.

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs are provided on an SOI substrate. The thickness of a thin film on the substrate is varied to adjust the threshold voltage. The threshold voltage can be varied by roughly 240 mV. The thickness of the thin film can be adjusted through a LOCOS process.

Abstract: A semiconductor device comprises: a semiconductor substrate; a field oxide film formed in the semiconductor substrate, the field oxide film having element forming regions on both sides thereof; a pair of MOS transistors formed in the element forming regions on both sides of the field oxide film, each of the transistors having a gate oxide film, a gate electrode and a pair of source/drain regions; an interlayer insulating film covering the semiconductor substrate, the field oxide film and the transistors; a local interconnect formed by embedding a conductive material in a first opening formed in the interlayer insulating film, the first opening being arranged above the field oxide film and having a greater width than the field oxide film, an inner one of the pair of source/drain regions of each of the pair of transistors being exposed to the first opening, the inner one of the pair of source/drain regions of one of the pair of transistors being electrically connected to the inner one of the pair of source/drai

Abstract: A method is disclosed to provide for more robust latchup-immune CMOS transistors by increasing the breakover voltage VBO, or trigger point, of the parasitic npn and pnp transistors present in CMOS structures. These goals have been achieved by adding a barrier layer to both the n-well and p-well of a twin-well CMOS structure, thus increasing the energy gap for electrons and holes of the parasitic npn and pnp transistor, respectively.

Abstract: Improved trench forming methods for semiconductor substrates using BSG avoid the problems associated with conventional TEOS hard mask techniques. The methods comprise: (a) providing a semiconductor substrate, (b) applying a conformal layer of borosilicate glass (BSG) on the substrate; (c) forming a patterned photoresist layer over the BSG layer whereby a portion of a layer underlying the photoresist layer is exposed, (d) anisotropically etching through the exposed portion of the underlying layer, through any other layers lying between the photoresist layer and the semiconductor substrate, and into the semiconductor substrate, thereby forming a trench in the semiconductor substrate. Preferably, one or more dielectric layers are present on the substrate surface prior to application of the BSG layer. One or more chemical barrier and/or organic antireflective coating layers may be applied over the BSG layer between the BSG layer and the photoresist layer.

Abstract: A method for forming a capacitor structure of semiconductor is disclosed. The method includes the following steps. First of all, a first oxide layer is deposited. A first nitride layer is formed. Consequentially, a portion of the first nitride layer and a portion of the first oxide layer are all etched. Then, the first polysilicon layer is formed. The portion of the first polysilicon layer is reduced to a specified thickness. Next, boron phosphorus silicon glass layer blankly and conformably is formed. Then, a portion of said boron phosphorus silicon glass layer is etched. A second polysilicon layer is deposited. Next, a portion of the second polysilicon layer is etched back. Next, the boron phosphorus silicon glass layer is etched. Then, the first polysilicon layer is etched back. A second nitride layer is formed. Next, a second oxide layer is deposited. Finally, a conductive layer is formed as a top plate of capacitor, whereby a capacitor structure is completed and there are a top plate and a bottom plate.

Abstract: A method of manufacturing a semiconductor apparatus comprises the steps of forming, on a surface of a semiconductor substrate, an MIS transistor including a drain region and a source region each formed of an impurity diffusion region, forming an insulation film on the semiconductor substrate after the MIS transistor has been formed, selectively forming contact holes in the insulation film, embedding, into the contact hole, a capacitor contact plug having a lower end which is in contact with one of the drain region and the source region of the MIS transistor, forming a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode on the insulation film after the capacitor contact plug has been formed, and forming an electric wire for establishing a connection between the upper electrode of the ferroelectric capacitor and an upper surface of the capacitor contact plug.

Abstract: A fully self-aligned method for fabricating a transistor is described. The source/drain contact opening is formed in the forming step of the gate to avoid the problem of misalignment. Therefore, the complex processes and the poly pad layer of the conventional method are not needed. A fully self-aligned method for fabricating memory is described. The memory cell and logic circuit regions have the same height during the formation process of the memory.

Abstract: Disclosed herein is an arrangement of memory cells in which the spacing between back-to-back trench capacitors is defined at less than 1 F spacing. A pure phase edge mask is used to define such trench patterns having less than 1 F spacing. The reduction in the trench-to-trench spacing results in increased separation between the trench and the near edge of the gate conductor. This increase in the trench to gate conductor spacing, in turn, permits the channel doping concentration to be decreased, with a corresponding increase in ON current to be realized. In alternative embodiments, a pure phase edge mask or a blocked phase edge mask can be used to define trench patterns in which the width of trenches is increased to form storage capacitors having higher capacitance. In such embodiments, the spacing between back-to-back trenches can be reduced, such that the total separation between the outer edges of adjacent trenches is maintained at about 3 F or less.

Abstract: An integrated circuit comprising stacked capacitor memory cells having sub-lithographic, edge-defined word lines and a method for forming such an integrated circuit. The method forms conductors adjacent to sub-lithographic word lines in order to couple a stacked capacitor to the access transistor of the memory cell. The conductors are bounded by the word lines. The bit line and capacitor are formed with a single mask image in such a manner as to self-align the bit line and the capacitor and to maximize the capacitance of the memory device. The method may be used to couple any suitable circuit element to a semiconductor device in an integrated circuit having edge-defined, sub-lithographic word lines.

Abstract: A square spacer and method of fabrication. The method includes forming a spacer film on a mandrel positioned on a substrate, forming an oxide film on the spacer film, performing a first etching, and performing a second etching. The spacer film is formed on perpendicular first and second sides of the mandrel. A first region and a second region of the spacer film are on the first side and the second side of the mandrel, respectively. The spacer film may include a conductive material such as polysilicon or tungsten. The spacer film may alternatively include an insulative material such as silicon dioxide, silicon nitride, or silicon oxynitride. The oxide film is formed such that a first region and a second region of the oxide film are on the first region and the second region of the spacer film, respectively. The oxide film may include silicon dioxide. The first etching etches away the first region of the oxide film and a portion of the first region of the spacer film.

Abstract: A fabrication method for a capacitor is proposed, beginning with a semiconductor substrate having a bit line and a planarized first dielectric layer formed thereon. A first silicon nitride layer is formed on the first dielectric layer, followed by forming in sequence a second dielectric layer and a second silicon nitride layer on the first silicon nitride layer. A photolithography and etching process is performed to form an opening in the second dielectric layer and the second silicon nitride layer. A conducting spacer is formed on a sidewall of the opening. With the spacer serving as a mask, the first silicon nitride layer and the first dielectric layer are etched to form a terminal contact opening. A conducting layer is then formed to cover the second silicon nitride layer and to fill the terminal contact opening, while the conducting layer on the second silicon nitride layer is removed by etching back.

Abstract: An Ir—M—O composite film has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer made from the same variety of M transition metals, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir—M—O conductive electrode/barrier structures are useful in nonvolatile FeRAM devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices.

Abstract: The fabrication method results in a stacked capacitor, in particular for use in a semiconductor memory device. The stacked capacitor has a semiconductor substrate of a first conductivity type and a well of a second conductivity type formed in the substrate. A stack of alternating first conductive layers of the first conductivity type and second conductive layers of the second conductivity type, with the interposition of respective insulation layers are formed on the semiconductor substrate. Two neighboring insulation layers are connected to one another on a first side of the stack by insulation bridges in such a way as to provide continuous insulation of the second conductive layers toward the first side. A first spacer, which is provided on the first side of the stack, forms a first capacitor connection and is preferably connected to the semiconductor substrate and to the first conductive layers.

Abstract: A high dielectric constant memory cell capacitor and method for producing the same, wherein the memory cell capacitor utilizes relatively large surface area conductive structures of thin spacer width pillars or having edges without sharp corners that lead to electric field breakdown of the high dielectric constant material. The combination of high dielectric constant material in a memory cell along with a relatively large surface area conductive structure is achieved through the use of a buffer material as caps on the thin edge surfaces of the relatively large surface area structures to dampen or eliminate the intense electric field which would be generated at the corners of the conductive structures during the operation of the memory cell capacitor had the caps not been present.

Abstract: A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes a floating gate with high data retention. A tungsten damascene local interconnect structure includes a silicon nitride etch stop layer which is formed using Plasma Enhanced Chemical Vapor Deposition (PECVD) at a temperature of at least 480° C. such that the etch stop layer has a very low concentration of hydrogen ions. The minimization of hydrogen ions, which constitute mobile positive charge carriers, in the etch stop layer, minimizes recombination of the hydrogen ions with electrons on the floating gate, and thereby maximizes data retention of the device.

Abstract: The semiconductor device includes a silicon substrate, field effect transistors, a flash memory and a separating portion. A plurality of field effect transistors are formed on semiconductor substrate. A flash memory is formed on semiconductor substrate. Separating portion includes a separation electrode. Separating portion electrically separates the plurality of field effect transistors from each other. Separating portion is formed insulated on silicon substrate. Flash memory includes a floating gate electrode and a control gate electrode. Floating gate electrode is formed insulated on silicon substrate. Control gate electrode is formed insulated on floating gate electrode. Separation electrode and floating gate electrode have approximately the same thickness.

Abstract: A method for forming an electrically-programmable read-only-memory (EPROM) or a flash memory cell is disclosed. The EPROM or flash memory cell provides both source-side and drain-side injection, along with a reduced cell size, by forming the memory cell in a trench. The drain is formed in the top surface of the substrate, the source is formed in the bottom surface of the trench, and the stacked gate is formed over the sidewall of the trench.

Abstract: A new method of fabricating a stacked gate Flash EEPROM device having an improved stacked gate topology is described. Isolation regions are formed on and in a semiconductor substrate. A tunneling oxide layer is provided on the surface of the semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. The first polysilicon layer is polished away until the top surface of the polysilicon is flat and parallel to the top surface of the semiconductor substrate. The first polysilicon layer is etched away to form the floating gate. The source and drain regions are formed within the semiconductor substrate. An interpoly dielectric layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly dielectric layer. The second polysilicon layer and the interpoly dielectric layer are etched away to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate.

Abstract: A MOSFET and IGBT are described that exhibit high breakdown voltage together with low on-resistance. This is achieved by providing an N type shunt that extends from the N+ drain (for power MOSFETs) or P+ emitter (for IGBTs), through the N− region to a short distance below the gate oxide. To manufacture such a shunt, an epi wafer with N− epitaxy is first provided on top of an N+ (for power MOSFET) or P+ (for IGBT) layer. Through a suitable mask (contact or freestanding) on the top surface, the wafer is then subjected to bombardment by protons or deuterons. Because of ion transmutation doping, a region of N type material forms wherever the surface is not masked. By controlling the energies of the ions, this region is caused to extend below the wafer's surface so as to just contact the N+ or P+ layer or even to go through it.

Abstract: A method and structure for manufacturing an integrated circuit device includes forming a storage device in a substrate, lithographically forming a gate opening in the substrate over the storage device, forming first spacers in the gate opening, forming a strap opening in the substrate using the first spacers to align the strap opening, forming second spacers in the strap opening, forming an isolation opening in the substrate using the second spacers to align the isolation opening, filling the isolation opening with an isolation material, removing the first spacers and a portion of the second spacers to form a step in the gate opening, (wherein the second spacers comprise at least one conductive strap electrically connected to the storage device) forming a first diffusion region in the substrate adjacent the conductive strap, forming a gate insulator layer over the substrate and the step, forming a gate conductor over a portion of the gate insulator layer above the step, forming a second diffusion region in th

Abstract: A semiconductor device includes a plurality of conductive layers that are formed on the substrate. Two electrically intercoupled sections of a read-only storage element, such as a fuse element, which together compose the storage element, are each formed in a different one of the conductive layers. The storage element has a storage state, and each section has a conductivity. One can change the storage state of the storage element by changing the conductivity of one of the sections. Additionally, multiple storage elements may be coupled in parallel to form a storage module. Each of the storage elements of the storage module may include multiple storage sections that are each formed in a different conductive layer. The storage elements may store the version number of the mask set used to form the semiconductor device. Alternatively, a conductive layer is formed on a substrate, and one or more read-only storage elements are formed in the conductive layer.

Abstract: The present invention provides a method of forming a high quality thin oxide on a semiconductor body. A sacrificial oxide is formed on the semiconductor and then etched to eliminate the surface contamination of the semiconductor body. Then, an EEPROM oxide is formed following by an arsenic implant. Next the EEPROM oxide on the semiconductor body is then prepared by thin oxide growth. The thin oxide is preferably formed in a steam ambient. Subsequently, the oxide is annealed under nitrous oxide ambient using a combination of in-situ and RTP annealing process.