Abstract: A method of fabricating a mask read-only memory. Before carrying out a code implantation, a coding mask is used as an etching mask to remove a portion of the inter-metal dielectric layer and the inter-layer dielectric layer above the coding positions, thereby forming a contact window. The code implantation is subsequently carried out so these ions can easily reach the coding positions via the contact opening.

Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.

Abstract: A fabrication method of a semiconductor device with an IGFET is provided, which makes it possible to decrease the current leakage due to electrical short-circuit between a gate electrode and source/drain regions of the IGFET through conductive grains deposited on its dielectric sidewalls. After the basic structure of the IGFET is formed, first and second single-crystal Si epitaxial layers are respectively formed on the first and second source/drain regions by a selective epitaxial growth process. Then, the surface areas of the first and second single-crystal Si epitaxial layers are oxidized, and the oxidized surface areas of the first and second single-crystal Si epitaxial layers are removed by etching.

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silkcon layer is then formed over the gate insulator layer. An first dielectric layser is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, of the first silicon layer, and of the first dielectric layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended source/drain junction in the substrate under a region uncovered by the gate region. An undoped spacer structure is formed on sidewalls of the gate region and a second silicon layer is formed on the semiconductor substrate. The first dielectric layer is then removed and another doping step is performed to dope the first silicon layer and the second silicon layer. A series of process is then performed to form a metal silicide layer on the first silicon layer and the second silicon layer and also to diffuse and activate the doped dopants.

Abstract: Methods of fabrication of a lateral RF MOS device having a non-diffusion connection between source and substrate are disclosed. In one embodiment, the lateral RF MOS device has an interdigitated silicided gate structure. In another embodiment, the lateral RF MOS device has a quasi-mesh silicided gate structure. Both sides of each gate are oxidized thus preventing possible shorts between source and gate regions and between drain and gate regions. The top of each gate is silicided once the protective layer of silicon nitride is removed.

Abstract: A method for counter-doping gate stack conductors on a semiconductor substrate, which substrate is provided with narrow space array regions (i.e., memory device regions) having a plurality of capped gate stack conductors spaced a first distance apart, and wide space array regions (i.e., logic device regions) having a plurality of gate stack conductors spaced a second distance apart, wherein the first distance is narrow in relation to the second distance.

Abstract: A method of performing tilted implantation for pocket, halo and source/drain extensions in ULSI dense structures. The method overcomes the process limit, due to shadowing effects, in dense structures, of using large angle tilted implant techniques in ULSI circuits. A gate opening in an oxide layer is defined and partially filled by insertion of nitride spacers to define an actual gate window opening. The small angle tilted implant technique has the equivalent doping effect of large angle tilted implants, and circumvents the maximum angle limit (&thgr;MAX) that occurs in the large angle implant method. The small angle tilted implant technique also automatically provides self alignment of the pocket/halo/extension implant to the gate of the device.

Abstract: A method of for fabrication a metal oxide semiconductor transistor is described. A substrate with an isolation structure thereon is provided. A gate oxide layer is formed on the substrate. A polysilicon layer is formed on the gate oxide layer. The polysilicon layer is patterned to form a gate on the gate oxide layer. An offset spacer is formed on the sidewall of the gate. A source/drain extension is formed in the substrate on two sides of the gate by ion implantation. An insulating spacer is formed on the sidewall of the offset spacer. A source/drain region is formed in the substrate by ion implantation using the gate, the offset spacer and the insulating spacer as a mask. Salicide is formed on the gate and on the surface of the source/drain region. After forming the salicide, the offset spacer is removed. After removing the offset spacer, a halo doped region is formed in the substrate below the source/drain extension by ion implantation.

Abstract: The present invention relates to a method of fabricating a MOS transistor on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate. A gate is first formed in a predetermined area on the surface of the semiconductor wafer. A first ion implantation process is then performed to form a doped area on the surface of the silicon substrate adjacent to the gate, the doped area serving as a heavily doped drain (HDD). A uniform and oxygen-free dielectric layer is formed on the surface of the semiconductor wafer that covers the gate. A spacer is formed on each wall of the gate. Finally, a second ion implantation process is performed to form a source and a drain on the surface of the silicon substrate adjacent to the spacer.

Abstract: A method for providing triangle shapes of high-density plasma CVD film, thereby the grad and source/drain implantation can be applied in the same step, and an offset source/drain mask layer can be eliminated. A substrate is provided incorporating a device, wherein the device is defined as a high-voltage MOS region. Sequentially, a plurality of field oxides are formed on the substrate, one of the field oxides is spaced from another of the field oxides by a high-voltage MOS region. Then, a gate oxide layer is formed above the silicon substrate. Moreover, a polysilicon layer is deposited over the gate oxide layer. A photoresist layer is formed above the polysilicon layer and gate oxide layer, wherein the photoresist layer is defined and etched to form a gate. Then, the photoresist layer is removed. Consequentially, a dielectric layer is deposited and etched above the polysilicon layer by using high-density plasma CVD to result in the inherit triangle shape of high-density plasma CVD film characteristic.

Abstract: The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.

Abstract: In one embodiment, the present invention relates to a method of forming a silicon-on-insulator substrate, involving the steps of providing a first silicon substrate; depositing a metal based layer over the first silicon substrate; forming a first insulation layer over the metal based layer to provide a first structure; providing a second structure comprising a second silicon layer and a second insulation layer; bonding the first structure and the second structure together so that the first insulation layer is adjacent the second insulation layer; removing a portion of the second silicon layer thereby providing the silicon-on-insulator substrate having a combined insulation layer having a thickness of about 100 Å to about 5,000 Å, wherein the metal based layer has a thickness that is one of less than 15% of the thickness of the combined insulation layer and greater than 50% of the thickness of the combined insulation layer.

Abstract: A method for forming an interconnect wiring structure, such as a fuse structure, comprises forming an opening in an insulating layer using a phase shift mask (the opening having vertical sidewalls sloped sidewalls and horizontal surfaces), depositing a conductive material in the opening and removing the conductive material from the sloped sidewalls and horizontal surfaces, wherein the conductive material remains on the vertical sidewalls as fuse links.

Abstract: A semiconductor device includes a first diffusion layer, an insulating film, and an electrode. The first diffusion layer is formed on the surface of a first-conductivity-type semiconductor substrate and has an opposite conductivity type. The insulating film is formed on the first diffusion layer. The electrode is made of a conductor layer formed on the insulating film. The width of the electrode is smaller than a value twice the length by which an impurity doped into the surface of the semiconductor substrate, using the electrode as a mask, laterally diffuses during annealing to a position immediately below the electrode.

Abstract: A bottle-shaped trench capacitor with a buried plate is formed in a controlled etch process. The bottle-shape is fabricated by etching deep trenches from a layered substrate, using the layers as a mask, and covering the side walls of the substrate with protective oxide and nitride layers. With the side walls covered, deep trench etching is then resumed, and a lower trench portion, below the protective layers of the side wall are formed. By diffusing a first dopant in the lower portion of the deep trench region, using the side wall protective layers as a mask, an etch stop is established for a wet etch process at the p/n junction established by the first dopant. The width of the lower trench portion is regulated by the time and temperature of the diffusion. Removing the doped material and applying a second dopant to the lower trench portion establishes a continuous buried plate region between trenches. A capacitor is formed by applying an insulating layer to the trench and filling with a conductor.

Abstract: A method of forming an opening within a surface of a semiconductor substrate while minimizing the effects of lithographic rounding. A semiconductor substrate is patterned using a first hard mask with features aligned in a first direction and a second soft mask with features aligned in a second direction.

Abstract: The present invention provides a new method which increases the surface area of the storage node of the capacitor, the method comprising: (1) Forming a photo resistor layer with a circular hole on the surface of the semiconductor wafer; (2) Using a wet isotropic etching method to form a bowl-like shallow concavity (pit) through the hole with a radius bigger than the hole; (3) Using a dry anisotropic etching process to etch a shallow pit through the hole in the central part of the bottom of the shallow pit down through the substrate of the semiconductor wafer; and (4) Eliminating the photo resistor layer, and then depositing a doped polysilicon layer over the shallow pit and the well resulting in a recess corresponding to the shallow pit and the well, wherein the deposition layer with a recess forms the storage node of a capacitor, the storage node having a recess with a larger surface area.

Abstract: A method for fabricating a capacitor includes the formation of a self-aligned and essentially amorphous passivation edge web. The passivation edge web is formed in the course of a BST vapor phase deposition after prior etching of the lower metal electrode and of the barrier layer, the TEOS layer situated under the barrier layer being attacked by said etching. By means of targeted material redeposition on the side walls of the lower electrode and of the barrier layer, the passivation edge web is subsequently formed from this material deposition.

Abstract: A method and apparatus for enhanced capacitance per unit area electrodes is utilized in semiconductor memory devices. The capacitance is enhanced by roughening the surface of the bottom electrode in such devices. In one embodiment of the invention, surface roughness is achieved on a polysilicon bottom capacitor electrode by depositing doped polysilicon on the outside surfaces of a bottom capacitor electrode and vacuum annealing. In another embodiment of the invention, surface roughness is achieved by depositing a GeO2-embedded GeBPSG layer on a substrate, annealing, selectively etching to remove GeO2, forming a container, and depositing a blanket rough polysilicon layer over the GeBPSG layer to replicate the underlying surface roughness.

Abstract: A method for fabricating a capacitor for a semiconductor device is disclosed. The method includes the steps of forming an insulation film having a contact hole on a substrate, forming a hemispherical grain (HSG) film on an inner surface of the contact hole, forming a lower electrode on a surface of the HSG film, removing the insulation film, forming a dimple on a surface of the lower electrode by removing the HSG film, forming a dielectric film on a surface of the lower electrode, and forming an upper electrode on a surface of the dielectric film, for thereby enhancing a reproducibility of the process and a reliability of a semiconductor device by preventing a lower electrode of a capacitor and a HSG film from being damaged.

Abstract: There is provided a method for forming a capacitor of a semiconductor device capable of preventing a dielectric layer from being damaged in forming a tungsten upper electrode on a dielectic layer, and preventing tungsten siliside from being formed on a tungsten film in the following processes. In the present invention, for protecting a dielectric layer, a polisilicon layer is formed on a dielectric layer as a sacrifical reduction layer. Then, a tungsten seed layer is formed on the dielectric layer by reducing WF6 with the polysilicon layer. After that, a tungsten film to be an upper electrode is formed by subsequently carrying out a deposition process using the reaction of WF6 and H2 or SiH4 Then, for preventing tungsten silicide film from being formed in following thermal process, a thermal process is performed in ammonia(NH3) cointaining ambient, or a plasma process using a nitrogen gas or an ammonia gas is performed to nitrize the surface of the tungsten film.

Abstract: A method of fabricating shallow trench isolation. A silicon oxide layer is formed on a substrate. The silicon oxide layer is patterned and a portion of the substrate is removed to form a trench within the substrate. A liner oxide layer is formed on the sidewall of the trench. An insulating layer is formed on the substrate and filled in the trench. A portion of the insulating layer is removed by CMP to expose the silicon oxide layer. The silicon oxide layer is removed and the STI structure is completed.

Abstract: Structures and methods are disclosed for insulating a polysilicon gate adjacent to an electrically active region with a silicon base layer. A layer of silicon nitride having a thickness in a range from about 100 Å to about 150 Å is conformally deposited over the polysilicon gate. A layer of silicon dioxide is formed over the layer of silicon nitride on the polysilicon gate. The layer of silicon dioxide is subjected to a spacer etch to form spacers upon the layer of silicon nitride and on lateral sidewalls of the polysilicon gate. A portion of the layer of silicon nitride situated between the polysilicon gate and the spacer is removed by an etching process that is selective to silicon dioxide and to polysilicon. The etch forms a recess defined between the polysilicon gate and each respective spacer. A cover layer is formed to close an opening to the recess so as to enclose a void therein.

Abstract: To avoid damage to carrier substrates in a device for mechanically aligning carrier substrates for electronic circuits, the carrier substrates having two main surfaces and a peripheral surface and being supplied to a horizontal fixture of the device, centering elements being forced to engage on the peripheral surface of the carrier substrates to align the carrier substrates in the horizontal fixture, it is proposed that at least two centering elements be mounted rotationally and displaceably in the axial direction on at least two first shafts that are oriented in parallel with one another and in parallel with the horizontal fixture. The centering elements engage on sections of the peripheral surface of the carrier substrate disposed opposite one another in a first direction, and at least two further centering elements engage with stop faces at sections of the peripheral surface of the carrier substrate disposed opposite one another in a second direction running perpendicularly to the first direction.

Abstract: A method for making a thin film of solid material, including bombarding one face of a substrate of the solid material with at least one of rare gas ions and hydrogen gas ions so as to create a layer of microcavities seperating the substrate into two regions at a depth neighboring the average ion penetration depth, and heating the layer of microcavities to a temperature sufficient to bring about a separation between the two regions of the substrate. The solid material includes one of a dielectric material, a conducting material, a semi-insulating material, and an unorganized semiconducting material.

Abstract: A method for fabricating a shallow trench isolation (STI) structure includes a pad oxide layer and a hard masking layer are sequentially formed over a semiconductor substrate. A trench is formed in the substrate by patterning over the substrate. Then, the hard masking layer is removed to expose the pad oxide layer. An insulating layer is formed over the substrate to fill the trench. Using the pad oxide layer as a polishing stop, a CMP process is performed to polish the insulating layer until the pad oxide layer is exposed. The remained pad oxide within the trench is simultaneously planarized to have a planar top surface without dishing and microscratch. After the pad oxide is removed, the STI structure is accomplished.

Abstract: The invention relates to a shallow trench isolation method used in a semiconductor wafer that comprises a plurality of predetermined active regions, a plurality of shallow trenches used for electrically isolating the plurality of active regions, and a wafer alignment region wherein at least one recess having a predetermined pattern is formed on the surface of the wafer. In the method of the present invention, an insulation layer is first formed on the surface of the semiconductor wafer to fill the recesses in the wafer alignment region and the plurality of shallow trenches. An etching process is then implemented to reduce the thickness of the insulation layer on the surface of the working region, the working region having a relatively high density of active regions. Also, the insulation layer is completely removed from the recesses within the wafer alignment region.

Abstract: A method of manufacturing a semiconductor device using shallow trench isolation is provided, wherein a plurality of protrusions are formed in the exposed surface of the mask layer overlying the active area of the device. The protrusions are preferably formed by forming a photo-resist layer on the surface of the mask layer and patterning the photo-resist layer such that the photo-resist layer defines a plurality of protrusion areas and a depression area within the defined active area. A portion of the mask layer is removed in the defined depression area to form a plurality of protrusions in the mask layer. Thereafter, a dielectric layer is deposited on the exposed surface of the mask layer and in the shallow trench and evenly planarized.

Abstract: A method of forming a trench isolation structure is provided, which prevents generation of defects such as voids, cracks, and depressions of an isolation dielectric formed in an isolation trench without problems such as isolation region expansion, isolation capability degradation, and current leakage increase. In a first step, an isolation trench is formed in a semiconductor substrate to expose a top of the trench from a main surface of the substrate. In a second step, the whole main surface of the substrate is covered with a solution of a silazane perhydride polymer by spin coating, thereby forming a film of the solution covering the whole main surface of the substrate. The trench is entirely filled with the film of the solution. The film of the solution may be formed directly on the main surface of the substrate or formed indirectly over the main surface of the substrate via any intervening film or films.

Abstract: A method for planarizing a polycrystalline silicon layer deposited on a trench, which is formed on a semiconductor substrate, comprises the following steps. First, a polycrystalline silicon layer with an enough thickness is deposited on the surface of the semiconductor substrate to overfill the trench. At least one dimple is undesirably developed on the polycrystalline silicon layer during the polycrystalline silicon deposition. Then, an oxide layer with an enough thickness is formed on the polycrystalline silicon layer to overfill the at least one dimple. Next, the polycrystalline silicon layer is partially oxidized so as to transform the upper portion thereof into a polysilicon oxide layer. As a result of a non-uniform distribution of the oxidization rate, the bottom surface of the polysilicon oxide layer, i.e. the interface between the polysilicon oxide layer and the non-oxidized portion of the polycrystalline silicon layer, is substantially planar.

Abstract: A method of fabricating a shallow trench isolation includes formation of a trench in a substrate. A high-density plasma chemical vapor deposition is performed with a plasma which does not contain argon gas. A liner oxide layer is formed on the substrate exposed in the trench. Another high-density plasma chemical vapor deposition is performed. A silicon oxide layer is formed. Then, some follow-up steps are performed to complete the shallow trench isolation.

Abstract: A process for producing a semiconductor device comprises heat-treating an oxygen-containing silicon substrate in an inert atmosphere to change a concentration of oxygen contained in the silicon substrate to within a range of 5×1017/cm3 to 10×1017/cm3, and heat treating the silicon substrate in an oxidative atmosphere to form a silicon oxide film.

Abstract: Prior to a heat treatment for bonding a III-V group compound semiconductor layer on a silicon substrate, a thermal stress relaxation layer is provided between the silicon layer and the III-V group compound semiconductor layer thermal stress relaxation layer, having a thermal expansion coefficient equal or near to the thermal expansion coefficient of the III-V group compound semiconductor layer and having a rigidity coefficient being sufficiently large to suppress generation of any crystal defects in the III-V group compound semiconductor layer due to a thermal stress generated in the heat treatment and subsequent cooling stage by the difference in the thermal expansion coefficient between the III-V group compound semiconductor layer and the silicon layer.

Abstract: Methods for manufacturing semiconductor substrates in which a semiconductor layer for forming semiconductor device therein is formed on a supporting substrate with an insulating film interposed between, with which in forming the semiconductor layer on a substrate on which a buried pattern structure has been formed it is possible to greatly increase the film thickness uniformity of the semiconductor layer and the film thickness controllability, particularly when the semiconductor layer is being formed as an extremely thin film. As a result, it is possible to achieve improved quality and characteristics of the semiconductor substrates and make possible the deployment of such semiconductor substrates to various uses.

Abstract: The present invention provides a method of forming SOI substrate provided with an isolation layer. Since a thinning process is performed at the semiconductor silicon layer after isolation layers are formed on the semiconductor silicon layer, the occurrence of dishing is prevented.

Abstract: In a method for producing a silicon single crystal wafer, a silicon single crystal ingot in which nitrogen is doped is grown by a Czochralski method, sliced to provide a silicon single crystal wafer, and then subjected to heat treatment to out-diffuse nitrogen on the surface of the wafer. According to a further method, a silicon single crystal ingot is grown in which nitrogen is doped by a Czochralski method, with controlling nitrogen concentration, oxygen concentration and cooling rate, and then the silicon single crystal ingot is sliced to provide a wafer. A silicon single crystal wafer is obtained by slicing a silicon single crystal ingot grown by a Czochralski method with doping nitrogen, wherein the depth of a denuded zone after gettering heat treatment or device fabricating heat treatment is 2 to 12 &mgr;m, and the bulk micro-defect density after gettering heat treatment or device fabricating heat treatment is 1×108 to 2×1010 number/cm3.

Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step is disclosed. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The heat-treated wafer is then oxidized by heating in the presence of an oxygen-containing atmosphere in order to establish a vacancy concentration profile within the wafer. The oxidized wafer is then cooled from the temperature of said oxidizing heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a wafer having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the wafer.

Abstract: Systems and methods are described for semiconductor wafer pretreatment. A method of increasing the selectivity of silicon deposition with regard to an underlying oxide layer during deposition of a silicon containing material by broadening a selective temperature of formation window for said silicon containing material by decreasing a lower temperature endpoint includes: providing a semiconductor wafer with the underlying oxide layer in a processing chamber; then pumping water from then processing chamber; and then depositing the silicon containing material on the semiconductor wafer. A step of seeding the semiconductor wafer can be conducted by exposing the semiconducotor wafer to a germanium containing gas. A chlorine containing precursor and/or hydrogen can be introduced into the processing chamber to increase the selectivity of the silicon containing material to the underlying oxide. The selective HSG temperature of formation window is widened.

Abstract: A method for forming a shallow junction in a semiconductor device includes the steps of ion implanting a molecular antimony dimer (Sb2+) into a semiconductor substrate. The antimony dimer implantation process creates a shallow doped junction having a high dopant concentration and a shallow junction depth. The antimony dimer ion is extracted from an antimony source material at an extremely low extraction voltage. The use of a low extraction voltage enables the antimony dimer ion to be analyzed by an analyzer magnetic within the ion implantation device. The process of the invention can be used to form a variety of shallow dope structures in semiconductor devices, such as source/drain extension regions, implanted resistors, and the like.

Abstract: The adhesion of a conductive polymer film to an oxidized porous pellet anode is improved by the incorporation of a silane coupling agent in the polymer impregnating solution. The incorporation of the silane coupling agent also decreases leakage current and dissipation factor. Suitable silanes are those of the general formula (R1—R3)—Si—(OR2)3. Each of R2 and R3 is a C1-C6 alkyl group such as methyl, ethyl, or propyl R1 can be chosen from a wide variety of organic functional groups such as epoxy, glycidoxy, amino, and pyrrole. The most preferred silane is 3-glycidoxypropyltrimethoxysilane.

Abstract: Provided is a manufacturing method of a compound semiconductor having at least one layer of carbon-doped p-type semiconductor epitaxial layer by a MOVPE process, wherein carbon trichloride bromide is used as a carbon source of carbon to be added to the p-type semiconductor epitaxial layer. In the method the etching amount during growth is relatively small, and carbon can be added to a high concentration even with a large MOVPE apparatus.

Abstract: A Schottky diode assembly includes a Schottky contact formed on a semiconductor substrate and having a semiconductor region of a first conduction type, a metal layer disposed adjacently on the semiconductor region, a protective structure constructed on a peripheral region of the Schottky contact and a doped region in the semiconductor substrate having a second conduction type of opposite polarity from the first conduction type. The doped region extends from a main surface of the semiconductor substrate to a predetermined depth into the semiconductor substrate. The doped region of the protective structure has at least two different first and second doped portions located one below the other relative to the main surface of the semiconductor substrate. The first doped portion is at a greater depth and has a comparatively lesser doping, and the second doped portion has a comparatively higher doping and a slight depth adjacent the main surface of the semiconductor substrate.

Abstract: A structure is provided comprising a semiconductor substrate, a gate oxide layer on the substrate, and a polysilicon layer on the gate oxide layer. A masking layer is formed on the polysilicon layer. The masking layer is then patterned into a mask utilizing conventional photolithographic techniques, but without patterning the polysilicon layer. The photoresist layer is then removed, whereafter the mask, which is patterned out of the masking layer, is utilized for patterning the polysilicon layer. The use of a carbon free mask for patterning the polysilicon layer, instead of a conventional photoresist layer containing carbon, results in less breakthrough through the gate oxide layer when the polysilicon layer is patterned. Less breakthrough through the gate oxide layer allows for the use of thinner gate oxide layers, and finally fabricated transistors having lower threshold voltages.

Abstract: A method of forming a multi-layered dual-polysilicon structure that forms a polysilicon gate prior to formation of an ion implantation barrier and that requires fewer steps, is more economical, and permits fabrication of more compact semiconductor circuits and devices than prior art methods.

Abstract: A method for forming a polycide layer wherein the silicide layer is blanket deposited over a polysilicon layer and selectively ion implanted through a mask to form regions of a higher resistivity than the masked regions. The implanted polycide layer is then annealed by RTA and patterned to form the conductors, gate electrodes and interconnects from the low resistivity regions and resistive components of an integrated circuit from the high resistivity regions. The capability of selecting from high and low resistive regions in a single polycide layer permits the design of resistive components with smaller areas than would be permitted if the resistive components were formed of a single low resistivity layer. This extra degree of freedom permits the designer to optimize device density and device performance without compromising either. The procedure utilizes a additional masking step utilizing a block-out mask.

Abstract: A method for preventing void formation in a gate of a transistor formed in a substrate is disclosed. The method comprises: forming a gate oxide layer on the substrate; forming a polysilicon layer on the gate oxide layer; performing an ion implantation on the polysilicon layer, the ion implantation performed with a power approximately 30 KeV and a dosage about more than 1015 atoms/cm2; and forming a silicide layer on the polysilicon layer.

Abstract: A conductive interconnection for an integrate circuit between a protected node and a protecting node and its method are disclosed. The conductive interconnection comprises a stacking connector, a routing connector and a top conductive line. The stacking connector is formed to connect the protected node, which is constructed by at least one inner conductive line and at least one conductive plug, alternately. The inner conductive line has a length lower than a threshold value constrained by antenna effect. Moreover, the routing connector, extending toward the stacking connector, is formed to connect the protecting node. The top conductive line is used to connect the stacking connector and the routing connector. Accordingly, the protected node is disconnected from the protecting node prior to the formation of the top conductive line.

Abstract: Generally, and in one form of the invention, a method is disclosed for forming an ohmic contact on a GaAs surface 20 comprising the steps of depositing a layer of InGaAs 22 over the GaAs surface 20, and depositing a layer of TiW 24 on the layer of InGaAs 22, whereby a reliable and stable electrical contact is established to the GaAs surface 20 and whereby Ti does not generally react with the In.

Abstract: In forming an interconnection between a component and an electronic circuit, a base with precise component pockets is loaded with components. The components are patterned with a thin layer of solder paste. Next, a frame including a stencil, vertical walls and locating or keying features is placed onto the base. The stencil rests a controlled distance above the components. A multitude of solder spheres are dispensed into the frame. Solder balls retained within the frame are passed through the stencil and into contact with solder paste. Most preferably, due to controlled spacing between the stencil and components, only one solder ball is able to pass through each stencil hole. The remaining solder spheres in the frame are collected through various alternative techniques, including a disclosed emptying gate. Then the frame with stencil is removed from the base. The solder paste and solder spheres are heated, resulting in a reflow of the solder paste and a bonding of the solder spheres to the component.

Abstract: This invention relates to a new improved method and structure in the fabricating of aluminum metal pads. The formation special aluminum bond pad metal structures are described which improve adhesion between the tantalum nitride pad barrier layer and the underlying copper pad metallurgy by a special interlocking bond pad structure. It is the object of the present invention to provide a process wherein a special grid of interlocking via structures is placed in between the underlying copper pad metal and the top tantalum nitride pad barrier layer providing improved adhesion to the aluminum pad metal stack structure. This unique contact bond pad structure provides for thermal stress relief, improved wire bond adhesion to the aluminum pad, and prevents peeling during wire bond adhesion tests.