Abstract: In an ion implantation system, an ion beam generator generates and emits an ion beam containing ions of a target impurity element. A mass analyzing system derives desired ions from the ion beam to output an ion beam containing the desired ions. The ion beam emitted from the mass analyzing system becomes incident upon an inner cavity defined by a beam line. An electrostatic lens is being disposed in the inner cavity. The electrostatic lens converges the ion beam entered the inner cavity. The ion beam emitted from the beam line impinges upon a substrate into which impurities are to be implanted. A vacuum pump is being mounted on the beam line to evacuate the inner cavity of the beam line.

Abstract: An arrangement of shutter segments each having longitudinally opposed ends, front and back edges, and top and bottom solid surfaces, wherein each segment is adjacent to at least one other segment. The segments are arranged with the front and back edges of each segment in parallel along a first direction, and with one of the front or back edge of each segment overlapping one of the top or bottom surfaces of an adjacent segment. A drive hub is rigidly connected to each segment, respectively. A drive train engages all of the drive hubs, for simultaneously reciprocating the hubs and connected shutter segments rotatively through an actuation angle of no more than approximately 90 degrees (preferably 45 degrees) around respective axes of rotation which are parallel and coplanar along the first direction.

Abstract: Improvements in a focusing apparatus having an objective optical system for optically manufacturing a workpiece, forming a desired pattern on a surface of a workpiece or inspecting a pattern on a workpiece and used to adjust the state of focusing between the surface of the workpiece and the objective optical system. The focusing apparatus has a first detection system having a detection area at a first position located outside the field of the objective optical system, a second detection system having a detection area at a second position located outside the field of the objective optical system and spaced apart from the first position, and a third detection system having a detection area at a third position located outside the field of the objective optical system and spaced apart from each of the first and second positions.

Abstract: A comparison of the specular and diffused radiation reflected from a coating can be used in ratio to locate the gel point of the coating, and to monitor coating drying characteristics. This same system may be used to monitor the drying process of the coatings in a lab setting to characterize the drying process, optimize coating quality or optimize mill efficiency. A system implementing the Applicant's method uses a radiation source to illuminate a measurement location on the coating, and then provides a first and second radiation detectors to detect reflected radiation from the coating, originating from the radiation source. One of the radiation detectors is arranged to collect specular radiation. The second detector is arranged to collect only diffused radiation. The ratio of these two values represents information about the location of the gel point for the coating, and coating drying characteristics.

Abstract: A device for emitting radiation it a predetermined wavelength is disclosed. The device has a cavity comprising a first bulk region and a second bulk region of opposite conductivity type wherein a barrier is provided for spatially separating the charge carriers of the first and the second region substantially at the antinode of the standing wave pattern of said cavity. The recombination of the charge carriers at the barrier create radiation, the emission wavelength of the radiation being determined by the cavity.

Abstract: A semiconductor device includes a superlattice having a first semiconductor layer having a first band-gap, a second semiconductor layer having a band-gap narrower than the first band-gap, the superlattice having a band structure with an energy level of a conduction band of the second semiconductor layer being lower than an energy level of a conduction band of the first semiconductor layer and an energy level of a valence band of the second semiconductor layer being lower than an energy level of a valence band of the first semiconductor layer, or a band structure with an energy level of a conduction band of the second semiconductor layer being higher than an energy level of a conduction band of the first semiconductor layer and an energy level of a valence band of the second semiconductor layer being lower than an energy level of a valence band of the first semiconductor layer, an exposed face formed on a plane different from a plane orientation on which the superlattice is formed, an end face of the superlatt

Abstract: An OLED display device and a method of fabricating the device utilize a patterned layer of conductive pads formed over a substrate to fabricate a cathode layer without the need to subsequently pattern the cathode layer to create individually addressable cathodes. The design of the OLED display device is such that the cathode layer is positioned below the anode layer. The OLED display device may be configured to emit light through the substrate or through the top layer, i.e., the anode layer. In a first embodiment, the conductive pads have sharp edges that effectively pattern the cathode layer when it is formed over the pads. In a second embodiment, the conductive pads do not include sharp edges. In this embodiment, the cathode layer is made of a composite material, which includes cathode components and non-conducting components.

Abstract: A semiconductor device measuring socket includes a wiring pattern board on which a test circuit is formed; a substantially S-shaped contact for electrically connecting the wiring pattern board to external leads arrayed on a semiconductor device; a supporting member for elastically supporting the contact under tiltable condition; a socket main body for storing thereinto the contact and the supporting member and for mounting the wiring pattern board on a lower portion of the socket main body; and adjusting means for adjusting a tilting amount of the contact with respect to the socket main body. When the wiring pattern board is mounted on the socket main body, a lower end portion of the contact which is projected from the lower surface of the socket main body is depressed by the wiring pattern board to thereby tilt the contact, whereby a contact position between the external lead and the contact is determined.

Abstract: Transistors (43, 44, 45) of an SOI type semiconductor integrated circuit or a liquid crystal display apparatus to which the SOI semiconductor integrated circuit is applied are prevented from leaking a current. A semiconductor region (41) is formed below at least some of a plurality of transistors through an insulating region 42, and changes in threshold value of the transistors (43, 44, 45) caused by a potential applied to the semiconductor region are adjusted. At this time, the transistors (43, 44, 45) have well potentials (45) fixed to a first potential in the circuit, and the semiconductor region is fixed to a second potential.

Abstract: A LED has a thin highly resistive or insulative layer formed below an electrode pad in order to divert current flow from the region below an electrode pad, which region does not contribute to light emission, to another region which does. Consequently, better current efficiency is obtained. Further, diverting current flow from the region below the electrode pad where mechanical damages are expected deters deterioration of the region. Consequently, the LED lasts longer and is a better quality product.

Abstract: An n-type layer (3) and a p-type layer (5) which are made of a gallium nitride based compound semiconductor are provided on a substrate (1) so that a light emitting layer forming portion (10) for forming a light emitting layer is provided. A gallium nitride based compound semiconductor layer containing oxygen is used for at least one layer of the light emitting layer forming portion (10). In the case where a buffer layer (2) made of the gallium nitride based compound semiconductor or aluminum nitride is provided between the substrate (1) and the light emitting layer forming portion (10), the buffer layer (2) and/or at least one layer of the light emitting layer forming portion (10) may contain oxygen. By such a structure, crystal defects of the semiconductor layer of the light emitting layer forming portion (10) can be decreased and a luminance can highly be enhanced. Thus, it is possible to obtain a blue color type semiconductor light emitting device having a high luminance.

Abstract: A light emitting diode array includes a plurality of light emitting elements, provided on a substrate having a first conductivity type, for causing light to pass through a first area thereof. Each of the plurality of light emitting elements includes an active layer; a first cladding layer having the first conductivity type and a second cladding layer having a second conductivity type provided so as to interpose the active layer therebetween; and a current diffusion layer having the second conductivity type. The current diffusion layers respectively included in the plurality of light emitting elements are isolated from one another, and an area including the current diffusion layer is included in the first area.

Abstract: An object of the present invention is to provide a semiconductor light emitting device that an emission efficiency is high and it is possible to emit lights at an ultraviolet wave length. The semiconductor light emitting device according to the present invention is constituted by laminating a buffer layer, an n-GaN contact layer, a clad layer including n-AlGaN, a GaN active layer, a clad layer including p-AlGaN, and a p-GaN contact layer on a sapphire substrate. Each portion of the clad layer including n-AlGaN, the GaN active layer 5, the clad layer including p-AlGaN, and the p-GaN contact layer is eliminated by etching; as a result, the n-GaN contact layer 3 is exposed. Next, An n-side electrode for current injection is formed on the n-GaN contact layer 3. Next, an n-GaN current block layer 9 is formed on a portion of an upper face of the p-GaN contact layer 7. Next, a p-side electrode for current injection is formed on upper faces of the p-GaN contact layer and the n-GaN current block layer.

Abstract: In a charge transfer device, a floating gate is provided in an insulating film which is provided on a charge transfer channel layer. A buffer amplifier is connected with the floating gate, and detects signal charges in the charge transfer channel layer to generate a signal indicative of an output voltage corresponding to the signal charges. A bias gate is provided in the insulating film apart from the floating gate to cover at least a part of the floating gate. A bias applying unit applies a bias voltage to the bias gate in response to the output voltage signal such that an alternate current (AC) component of a voltage of the floating gate is substantially equal to an AC component of a voltage of the bias gate.

Abstract: A ferroelectric memory capable of writing data at a small operation voltage has an insulated-gate field effect transistor, a ferroelectric film, and a pair of capacitor electrodes formed on the ferroelectric film and facing each other, one of the pair of capacitor electrodes being electrically connected to the insulated gate. A ferroelectric memory device with a simple structure has an insulated-gate field effect transistor including a source, a drain, and an insulated gate, and a ferroelectric capacitor connected between the drain and the insulated gate.

Abstract: In order to correspond to high integration with large capacity of a semiconductor device, provided are a structure of the semiconductor device and a method for manufacturing the same in which a horizontal dimension can be reduced in either a memory cell region or a region where a peripheral circuit is to be formed or both the regions. A TFT is superposed on a trench capacitor with an insulation film provided therebetween in a DRAM memory cell region, and a TFT is superposed on a bulk transistor with an insulation film provided therebetween in a region where a peripheral circuit is to be formed. Consequently, elements are arranged three-dimensionally. Thus, a horizontal dimension of a region where each element is to be formed can be reduced.

Abstract: Capacitors and methods of forming capacitors are disclosed. In one implementation, a capacitor comprises a capacitor dielectric layer comprising Ta2O5 formed over a first capacitor electrode. A second capacitor electrode is formed over the Ta2O5 capacitor dielectric layer. Preferably, at least a portion of the second capacitor electrode is formed over and in contact with the Ta2O5 in an oxygen containing environment at a temperature of at least about 175° C. Chemical vapor deposition is one example forming method. The preferred second capacitor electrode comprises a conductive metal oxide. A more preferred second capacitor electrode comprises a conductive silicon comprising layer, over a conductive titanium comprising layer, over a conductive metal oxide layer. A preferred first capacitor electrode comprises a conductively doped Si-Ge alloy. Preferably, a Si3N4 layer is formed over the first capacitor electrode. DRAM cells and methods of forming DRAM cells are disclosed.

Abstract: A method for making reduced-size FLASH EEPROM memory circuits, and to the resulting memory circuit. An FET integrated circuit having two different gate oxide thicknesses deposited at a single step, where a portion of the thickness of the thicker oxide is formed, that oxide is removed from the area of the chip to have the thinner oxide, then the rest of the thicker oxide is grown during the time that the thinner oxide is grown on the area of the chip to have the thinner oxide. Layers for the floating gate stacks are deposited. Trenches are etched in a first, and then a second perpendicular direction, and the perpendicular sides of the stacks are covered with vertical-plane nitride layers in two separate operations. Tungsten word lines and bit contacts are deposited. Aluminum-copper lines are deposited on the bit lines.

Abstract: A memory cell array is constituted with a plurality of memory transistors having tunnel insulating films made relatively thick arranged in the form of a matrix, a non-selected column bias voltage of a value between a source voltage and a gate voltage when reading the selected transistor M11 is supplied to the source and/or drain of a non-selected column memory transistor M21 arranged in the column not containing the selected memory transistor M11 in an reverse bias polarity to for example a channel forming region, and a voltage of a value between the voltage to be supplied to the gate of the related selected memory transistor M11 when reading and a ground voltage supplied to the source of the selected memory transistor M11. Further, a voltage equivalent to or lower than that for the source of the selected memory transistor M11 is supplied to the gate of the non-selected row.

Abstract: A process is provided for forming a transistor in which the channel length is controlled by the depth of a trench etched into a semiconductor substrate. A masking layer extending across the substrate and a portion of the substrate are etched simultaneously to form the trench. A gate dielectric is formed upon the opposed sidewall surfaces of the trench. A pair of gate conductors are then formed upon the exposed lateral surfaces of the gate dielectric and the masking layer. Subsequently, an unmasked region of the substrate underneath the trench is implanted with dopant species and then annealed to form a source junction. The anneal temperature is preferably sufficient to cause the dopant species in the source junction to migrate laterally past the opposed sidewall surfaces of the trench. Drain junctions may subsequently be formed within the substrate a spaced distance above the source region on opposite sides of the trench.

Abstract: Power semiconductor devices having tapered insulating regions include a drift region of first conductivity type therein and first and second trenches in the substrate. The first and second trenches have first and second opposing sidewalls, respectively, that define a mesa therebetween into which the drift region extends. An electrically insulating region having tapered sidewalls is also provided in each of the trenches. The tapered thickness of each of the electrically insulating regions enhances the degree of uniformity of the electric field along the sidewalls of the trenches and in the mesa and allows the power device to support higher blocking voltages despite a high concentration of dopants in the drift region. In particular, an electrically insulating region lines the first sidewall of the first trench and has a nonuniform thickness Tins(y) in a range between about 0.5 and 1.

Abstract: An integrated circuit and fabrication method includes a vertical transistor for a memory cell in a dynamic random access memory (DRAM) or other integrated circuit. Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried gates and body contacts are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in first alternating trenches orthogonal to the bit lines. The buried word lines interconnect ones of the gates. Buried body lines extend in second alternating trenches orthogonal to the bit lines. The buried body lines interconnect body regions of adjacent access transistors. Unitary and split-conductor gate and body lines are provided for shared or independent signals to access transistors on either side of the trenches. In one embodiment, the memory cell has a surface area that is approximately 4 F2, where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.

Abstract: A semiconductor device comprises a semiconductor layer formed on an insulation layer, a pair of source and drain diffusion layer formed on a surface of the semiconductor layer, a first gate electrode disposed on the semiconductor layer region interposed between the pair of source and drain diffusion layer through a gate insulation film, a substrate potential control layer coupled to the semiconductor layer in a region interposed between the pair of the source and drain diffusion layer and formed in such a manner that the first gate electrode does not exist thereon, and a second gate electrode disposed to be in contact with the first gate electrode.

Abstract: An FS upper nitride film (15) is formed on the upper surface of an FS electrode (5). Therefore, the upper surface of the FS electrode (5) is not exposed even when an FS upper oxide film (41) is partially almost removed in the manufacturing process. Thus, a semiconductor device which prevents degradation in operation characteristics and reliability due to existence of an FS insulating layer can be provided.

Abstract: A semiconductor device is disclosed that provides a decoupling capacitance and method for the same. The semiconductor device includes a first circuit region having a first device layer over an isolation layer and a second circuit region adjacent the first circuit region having a second device layer over a well. An implant layer is implanted beneath the isolation layer in the first circuit region, which will connect to the well of the second circuit region.

Abstract: On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms. Furthermore, the film thickness T0 of the stopper is set in the range to fulfill the following expression: T0+T1≦(T2×8000 Å)½ where T1 is the film thickness of the silicon oxide film and T2 is the film thickness of the silicon nitride film.

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a Lateral Insulated Gate Bipolar Transistor (LIGBT) device in an SOI layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first and a body contact region of the second conductivity type in the body region and connected to the source region. A lateral drift region of a first conductivity type is provided adjacent the body region and forms a lightly-doped drain region, and a drain contact region of the first conductivity type is provided laterally spaced apart from the body region by the drift region with an anode region of the second conductivity type in the drain region and connected to the drain contact region.

Abstract: A semiconductor device includes a transistor and a protective resistance element. The transistor has first and second impurity regions of a first conductivity type formed on a surface of a substrate and serving as a source and a drain, respectively, and a gate electrode formed on a channel region sandwiched between the first and second impurity regions through a gate insulating film. The protective resistance element has a third impurity region of the first conductivity type formed on the surface of the substrate to be separated from the second impurity region by a predetermined distance, a control electrode formed on the substrate through an insulating film in a surface region sandwiched between the second and third impurity regions, and a well of the first conductivity type formed on the surface of the substrate in the surface region sandwiched between the second and third impurity regions to come into contact with them.

Abstract: A semiconductor device has electrostatic protection device capable of preventing characteristic fluctuation of MOS transistor caused by electrostatic discharge. PN junction is formed in between N+ cathode region and boron upward diffusion region of P+ substrate, thus being formed low breakdown voltage diode whose breakdown occurs at low reverse voltage. The diode is in use as electrostatic protection device of either input circuit or output circuit so that it is capable of protecting internal device transistor efficiently from applied surge when gate oxide film becomes thin film.

Abstract: A lateral IGBT in an SOI configuration having a top side and an underside is proposed. The lateral IGBT has a drain zone extending to the top side and is of a first conductivity type. The underside of the LIGBT forms a substrate of a second conductivity type. A lateral insulation layer is situated between the substrate and the drain zone. At least one laterally formed region of the second conductivity type is situated in the drain zone, in the vicinity of the lateral insulation layer. These laterally formed regions being spaced apart from one another lying in one plane.

Abstract: A BiCMOS structure and a method for making the same is disclosed, where the dielectric layer between the emitter electrode and the base region is formed of a deposited dielectric. After definition of the bipolar and MOS moat regions, a layer of polysilicon is deposited thereover, and removed from the bipolar region. The base implant is performed either prior to or after the etch of the polysilicon layer. A layer of TEOS oxide is formed thereover and is etched to remain in portions of the bipolar region, with an emitter contact formed therethrough and a portion of the bipolar region exposed at which the extrinsic base is formed. An alternative embodiment of the invention includes scaling the emitter contact by forming sidewall oxide filaments therewithin. A second layer of polysilicon is disposed thereover to form the emitter electrode, and to merge with the first layer to form the gates of the MOS transistors.

Abstract: A depletion mode MOSFET and resistor are fabricated as a silicon carbide (SiC) integrated circuit (IC). The SiC IC includes a first SiC layer doped to a first conductivity type and a second SiC layer overlaid on the first SiC layer and doped to a second conductivity type. The second SiC layer includes at least four more heavily doped regions of the second conductivity type, with two of such regions comprising MOSFET source and drain electrodes and two other of such regions comprising resistor electrodes. The second SiC layer includes an isolation trench between the MOSFET electrodes and the resistor electrodes. At least two electrically conductive contacts are provided as MOSFET electrode contacts, each being positioned over at least a portion of a respective MOSFET electrode and two other electrically conductive contacts are provided as resistor electrode contacts, each being positioned over at least a portion of a respective resistor electrode.

Abstract: An electrically programmable memory cell array is formed of memory cells, which include a vertical MOS transistor. The MOS transistor has a gate dielectric of a material with charge carrier traps. The memory cells are disposed along opposite edges of striplike, parallel insulation trenches. The width and spacing of the insulation trenches are preferably identical. The space required per memory cell of the memory cell array is 2F2, where F is the minimum structural size in the technology employed. The memory cells are programmed by selectively injecting electrons into the gate dielectric.

Abstract: A static random access memory cell is given increased stability and latch-up immunity by using N-type gate NMOS transistors and P-type gate PMOS transistors in the control and sensing circuits, but using the same gate conductivity type for both the NMOS and PMOS memory cell transistors. For example, both NMOS and PMOS memory cell transistors have N-type gates. Weakening the memory cell load transistors by lightly doping the source and/or drain regions further enhances stability.

Abstract: A first transistor having a central impurity region connected to a power supply node and outer-side impurity regions connected to an output node and a second transistor having a central impurity region connected to the output node and outer-side impurity regions connected to the power supply node are so arranged that the impurity regions connected to the power supply node are adjacent to or faced to those connected to the output node. The layout area of an output circuit is reduced without reducing electrostatic damage resistance by parasitic field transistors.

Abstract: A method of fabricating a MOSFET device structure, featuring a double insulator spacer, and improved source and drain engineering, has been developed. A silicon nitride-silicon oxide, double spacer, is used to prevent thinning of the insulator spacer, during a buffered hydrof luoric acid procedure, used prior to a metal deposition and metal silicide formation. A lightly doped source and drain region is formed prior to creation of the silicon oxide spacer, a medium doped source and drain region is formed prior to creation of the silicon nitride spacer, and a heavily doped source and drain region is formed following the creation of the silicon nitride spacer. This source and drain configuration increases device performance and reliability.

Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, and an electrode formed on the first insulating film. The first insulating film contains a halogen element and a combination of silicon and nitrogen or a combination of silicon, oxygen, and nitrogen. The maximum concentration of the halogen element in the first insulating film ranges from 1020 atoms/cm3 to 1021 atoms/cm3 inclusive. With this structure, the dielectric breakdown strength and the like of the insulating film increase, and the reliability of the insulating film improves.

Abstract: The present invention relates to the electrical isolation of components within an integrated opto-electronic device where two or more active regions are optically coupled, for example by a waveguide. The device includes a distributed feed-back laser diode and an electro-absorption modulator fabricated on the same substrate. The laser diode and modulator are: separated by an electrical isolation region; linked optically across the isolation region by a waveguide; and capped by a ternary cap layer through which ohmic contacts are made to operate the components. The cap layer extends to the isolation region from which a grounding contact is made to ground the cap layer in the isolation region and so to electrically isolate the laser diode and modulator from each other.

Abstract: A radiation detection structural principle for improved detection wherein absorbtion members of high density and bandgap semiconductor material and meeting all efficiency limiting requirements are provided with a sweeping field applied across each member. The absorbtion members are assembled in stack structures for particular energy resolution benefits. The detector principle is extendable to long absorbtion paths and to energy resolution in specific areas.

Abstract: A semiconductor device which has few peripheral element malfunctions and superior performance is obtained. The semiconductor device includes a p-type buried layer on a main surface of a semiconductor substrate, an n-type cathode region provided on the p-type buried layer, and a p-type anode region in contact with the side surface of the n-type cathode region, the p-type buried layer being higher than the p-type anode region in acceptor content, and the p-type buried layer being in contact with the bottom surfaces of the anode and cathode regions.

Abstract: A semiconductor device and method of fabricating the same. The semiconductor device includes a first insulating film formed on a substrate and having a plurality of holes therein; a cavity formed under the first insulating film; an impurity region formed in the substrate and around the cavity; a second insulating film formed on portions of the first insulating film to fill the holes and a space between the cavity and the impurity region; a plurality of contact holes formed to expose certain portions of the impurity region; and a plurality of wiring layers formed to be in contact with the impurity region through the contact holes.

Abstract: A spiral inductor fabricated above a semiconductor substrate provides a large inductance while occupying only a small surface area. Including a layer of magnetic material above and below the inductor increases the inductance of the inductor. The magnetic material also acts as barrier that confines electronic noise generated in the spiral inductor to the area occupied by the spiral inductor. Inductance in a pair of stacked spiral inductors is increased by including a layer of magnetic material between the stacked spiral inductors.

Abstract: A discontinuous film structure on a surface which may be a substrate, with an underlying layer on the surface having a first opening formed therein, a separator layer on the underlying layer having a second opening formed therein, and the second opening overlying the first opening such that the separator layer overhangs the underlying layer. A discontinuous-as-deposited film is formed on the separator layer, with the discontinuity substantially in register with the second opening. The structure is made into a stacked capacitor with the discontinuous film being the bottom electrode, by forming a continuous dielectric layer on the bottom electrode and a continuous top electrode layer on the dielectric layer.

Abstract: A memory cell array for a dynamic random access memory (DRAM) includes word and body lines that are buried below the active semiconductor surface in dielectric material in alternating parallel isolation trenches between adjacent ones of the memory cells. Semiconductor-on-insulator (SOI) processing techniques form the access transistor of each memory cell on a silicon island defined by the trenches and isolated from the substrate by an insulating layer. The word and body lines are oriented in the trenches to have a line width that is less than a minimum lithographic feature size F. The memory cells, including portions of the word and body lines, have a surface area of about 8 F2. Also disclosed is a process for fabricating the DRAM cell using SOI processing techniques.

Abstract: A tape carrier package is provided with a first region which includes a plurality of input leads for transmitting an input signal between a liquid crystal driver IC chip and a section external to the tape carrier package, and a second region which includes signal transmitting wires for transmitting an input signal among a plurality of the input leads, on one of the surfaces of a tape substrate. Further, in the tape substrate, a folding slit is formed along a boundary between the first region and the second region. The tape substrate is folded into 180 degrees along the folding slit serving as a fold so as to electrically connect a plurality of the input leads and the signal transmitting wires. This arrangement makes it possible to prevent a voltage drop caused by wire resistance.

Abstract: A semiconductor package substrate includes at least one insulative layer, at least two metal lines next to one another on a first side of the insulative layer, and a first metal layer on a second side of the insulative layer opposing the first side. An opening is formed in the first metal layer in an area between the metal lines. Two lands remain part of the first metal layer. The lands are located adjacent the opening and each land opposes a respective one of the metal lines located next to one another.

Abstract: A connection component for a semiconductor chip includes a support structure having a top surface including a dielectric material and a bottom surface. The support structure includes a central portion, a peripheral portion and one or more gaps extending substantially between the central portion and the peripheral portion. A bus overlies the top surface of the support structure. The each bus has an outer edge which overlies the peripheral portion of the support structure and an inner edge which overlies the one or more gaps. The support structure also includes one or more electrically conductive leads having first ends secured to the central portion and second ends overlying the gaps and being secured to the inner edge of the bus. The second ends of the leads are displaceable relative to the bus in response to bonding forces being applied to the leads for engaging contacts on a semiconductor chip.

Abstract: A support assembly for mounting a semiconductor device vertically relative to a carrier substrate. The support assembly includes an interposer to which the semiconductor device is attached. The support assembly also includes traces carried on the interposer, which electronically connect the semiconductor device to contacts on the interposer. The contacts are disposed along a single edge of the interposer. The invention also includes an alignment device for releaseably mounting the support assembly. The alignment device, which mounts to a carrier substrate, includes one or more receptacles. As a support assembly is inserted into a receptacle, the alignment device establishes an electrical connection between the contacts and corresponding terminals on the carrier substrate. The assembly may also include a cover that attaches to the top of the alignment device and biases the interposer against the carrier substrate.

Abstract: A substrate for reducing electromagnetic emissions is provided. The substrate may include a plurality of ground layers, signal layers and power layers. All of the layers other than the ground layer are provided with a ground ring that may extend around the perimeter of the layer. The ground rings are electrically coupled together by ground stitching or vias that are randomly spaced. The random spacing of the ground stitching is based on the operating frequencies of the integrated circuit devices mounted on the substrate. Additional shielding may be provided by providing a cover assembly made of any conductive material that is coupled to the exposed ground rings on the uppermost and lowermost surfaces of the substrate. The cover assembly is coupled to the exposed ground rings in a randomized pattern. The device provides a virtual electrical ground cage in which the internal signal layers are totally enclosed, thereby reducing electromagnetic emissions.

Abstract: To provide a semiconductor substrate and a light-valve semiconductor substrate capable of preventing the threshold value of a MOS transistor on a single-crystal silicon device forming layer from increasing and forming a MOS integrated circuit with a high reliability even for a long-time operation. A semiconductor substrate and a light-valve semiconductor substrate comprising a single-crystal silicon thin-film device forming layer 5001 formed above an insulating substrate 5004 through an adhesive layer 5003 and an insulating layer 5002 formed on the single-crystal silicon thin-film device forming layer, wherein a heat conductive layers 5201 and 5202 made of a material with a high heat conductivity are arranged between the single-crystal silicon thin-film device forming layer and the adhesive layer and on the insulating layer.