Abstract: A magnetoresistive sensor includes a plurality of multilayered magnetoresistive films arranged in parallel. Each multilayered magnetoresistive film includes at least one pinned ferromagnetic layer and at least one free magnetic layer. Reversion of magnetization of the pinned ferromagnetic layer is pinned, whereas the vector of magnetization of the free ferromagnetic layer freely reverses in response to an external magnetic field. The vectors of magnetization of the pinned ferromagnetic layers in two adjacent multilayered magnetoresistive films are substantially antiparallel to each other.

Abstract: A sensor for measuring linear or angular dimension. The sensor can be moved with respect to a magnetized scale with a period &lgr;. It is equipped with magnetoresistive electrodes provided with barber-pole structures and connected so as to form n measuring bridges, each measuring bridge formed by four sets of magnetoresistive electrodes. The magnetoresistive electrodes making up each set are connected in series, the magnetoresistive electrodes being distributed spatially so as to constitute x groups. Each group being formed by more than eight consecutive magnetoresistive electrodes coming from two sets of a same measuring bridge.

Abstract: A rotary position sensor having redundant sensing including a base (20) upon which a plurality of radially extending magnetic sensing elements (22) are mounted to form two sets (74, 76) of sensors. Interleaved with the sensing elements (22) are a plurality of uniformly spaced magnetic concentrators (30). The sensor assembly (18) is placed in a uniform magnetic field created, for example, by a flat plate magnet (432) mounted adjacent the sensor assembly, and rotatable relative to it. The relative rotary position of the sensor assembly to the magnetic field is determined by comparing the relative values of the sensor elements (22) in the array to each other. Also, failure of the sensor assembly is determined by comparing the rotary position calculated for the first set 74 to the rotary position calculated for the second set 76.

Abstract: An oscillator 12 outputs a constant frequency as a metal object is brought close and this frequency forces oscillation of an oscillating circuit 11 which is sensitive to this metal object, at a level significantly below the critical natural frequency of the oscillating circuit. The oscillating signals S1, S2 are applied to the two inputs of a phase detector 15, such that they can be changed over by means of an inverter device 17, so that the detector can be configured in ferrous mode or in non-ferrous mode.

Abstract: A magnetic field sensor which includes a planar thin-film element made of a crystalline magnetoresistive material exhibiting resistivity anisotropy in a plane, having a first and a second easy axis of magnetization. The planar thin-film element has electrical connections allowing a first electrical measurement current to flow through the planar thin-film element in a first direction, as well as two other electrical connections allowing a voltage to be measured in a second direction transverse to the first direction. The two easy axes of magnetization have comparable magnetization values.

Abstract: A method of compensating for an eddy field according to measurements of the field. The method includes fitting the measurements of the field to a plurality of candidate models of the field. A stability value indicative of the stability of the fitted model to changes, is assigned to each of the fitted candidate models. A model is selected from the candidate models responsive to the stability values of the candidate models and the eddy fields are compensated responsive to the selected model.

Abstract: A toroid cavity detector includes an outer cylindrical housing through which extends a wire along the central axis of the cylindrical housing from a closed bottom portion to the closed top end of the cylindrical housing. In order to analyze a sample placed in the housing, the housing is placed in an externally applied static main homogeneous magnetic field (B0). An RF current pulse is supplied through the wire such that an alternately energized and de-energized magnetic field (B1) is produced in the toroid cavity which B1 field is oriented perpendicular to the B0 field. Following the RF current pulse, the response of the sample to the applied B0 field is detected and analyzed. In order to minimize the detrimental effect of probe ringing, the cylindrically shaped housing is elongated sufficiently in length so that the top and bottom portions are located in weaker, fringe areas of the static main magnetic B0 field.

Abstract: A permanent magnet for nuclear magnetic resonance image detection, includes a magnetic structure having a yoke and magnetic poles, so shaped as to delimit or enclose a cavity, at least a part of a volume of the cavity forms a compartment for receiving at least a part of a body under examination, and at least a part of the volume of the cavity is permeated by a static magnetic field having specific intensity and homogeneity characteristics; the magnetic structure has at least one open side, parallel to the static magnetic field; the magnetic structure has at least two opposite main poles, lying face to face, transverse to the open side, the static magnetic field being generated therebetween; in the vicinity of the open side, the magnet has a device for correcting the static magnetic field generated between the main poles, the correction device including an element for increasing the magnetic potential near the open side, and over a predetermined depth therefrom, transverse to the open side, without reducing th

Abstract: A boring tool is moved through the ground in a region which includes at least one electrically conductive in-ground line and which is subject to static magnetic fields including the magnetic field of the earth.

Abstract: An apparatus and method for implementing azimuthal capabilities on electromagnetic wave resistivity well logging tools. The apparatus comprises a structurally simple antenna shield positioned around either the transmitting or receiving antennas, or both, positioned on the well logging tool on the drill string. The shields partially surround the tool and provide an electromagnetic barrier for either the transmission or reception of electromagnetic waves, as the case may be. Positioned on the shield are appropriately placed and sized windows through which electromagnetic waves may either be transmitted or received, depending upon the function of the antenna that the shield surrounds. Variations in window dimensions allow optimization of the device for use in conjunction with a variety of formations and a variety of drill mud characteristics.

Abstract: A method of data acquisition for geophysical surveys. The method includes the steps of providing a least one magnetic sensor unit for sensing and recording magnetic field fluctuations; providing a plurality of electric sensor units for sensing and recording electric currents induced by the magnetic field fluctuations; receiving a satellite based timing signal and responsively synchronizing and bag a position for each of the plurality of electric sensor units and the at least one magnetic sensor unit; and synchronously recording the positions, the magnetic field fluctuations and the electric currents for downloading for processing.

Abstract: The borehole imaging apparatus of the present invention includes a tool having an array of voltage electrode buttons mounted on a non-conductive pad. A current source and a current return are preferably located on the non-conductive pads at opposite ends thereof. The locations of the current source and return are designed to force a current to flow in the formation parallel to the pad face and non-parallel to the formation boundary layers. According to a method of the invention, the voltage difference between a pair of buttons in the array is proportional to the resistivity of the formation bed adjacent to the buttons. The ratio of voltage differences between two nearby pairs of electrode buttons provides a quantitative measurement of the ratio of shallow resistivity. The resolution of the image produced by the new tool is determined only by the spacing of the buttons. The tool according to the invention produces much better images than the prior art tools when used in OBM wells.

Abstract: A novel toroidal core current sensor for an AFCI/GFCI Circuit Breaker and a test circuit configuration based thereon is disclosed. The current sensor has a plurality of load current conductors extending therethrough. One of the conductors carrying a load current has a portion of the load current shunted outside the core through a shunt conductor which is connected in parallel with one of the load current conductors. The secondary of the transformer outputs a current value proportional to and substantially less than the load current which may be, for example, detected by a control circuit which compares the current value against predetermined stored criteria and operates a circuit breaker accordingly. In the test circuit a power source and a waveform generator are provided for operating an AFCI\GFCI circuit breaker having the shunted current sensor and injecting test signals into a terminal of the circuit breaker.

Abstract: A device and method for determining the state of charge of a battery includes a microprocessor-controlled arithmetic unit connected in parallel to the terminal voltage of the battery. The arithmetic unit is selectively connectable with an ohmic reference resistance placed in parallel with a load resistance which is arranged in series with the battery, and with a capacitor chargeable or dischargeable via the arithmetic unit. The arithmetic unit is further capable of acquiring a value of the voltage drop across the capacitor. The arithmetic unit is operable in a first operating state in which it is disconnected from the reference resistance, and a second operating state in which the arithmetic unit is connected with the resistance. After the capacitor is charged to the terminal voltage of the battery, it is allowed to discharge. With the arithmetic unit in the first operating state, a first point in time marked by the voltage across the capacitor reaching a first threshold value is registered.

Abstract: A cell grading test fixture includes an array of cell sockets electrically interconnected in series so that current through the entire array of cells flows through each of the cells once inserted into the fixture. Associated with each socket is an indicator which indicates to the operator when a cell voltage has fallen to a predetermined level. Each socket of the test fixture includes a spring-loaded switch contact such that upon removal of a cell which has dropped below a threshold voltage, the movable contact engages the contact of an adjacent socket, shorting out the cell location such that the series circuit of cells continues to provide a current path for the remaining cells.

Abstract: An apparatus is provided to facilitate connection inspections for a high tension cord 1. The apparatus includes a contact element that can be brought into contact with a distributor terminal T2. The contact element includes elastic elements 31b to 34b that are constructed to be displaceable between an enclosed state where they enclose the distributor terminal T2 to establish an electrical connection therewith and an open state where a high tension cord 1 can be mounted and detached. Since the distributor terminal T2 can be connected electrically without precisely positioning it, connection inspections for the high tension cord 1 can be made easier and, consequently, automation and labor-saving can be made possible.

Abstract: A capacitance sensor detects the absence/presence of physical matter on a sensing surface of the sensor. The capacitive sensor is a multi-cell sensor wherein each cell has one or more buried, protected, and physically inaccessible capacitor plates. The sensor is physically placed in an environment that is to be monitored for deposition of a particle, vapor, and/or drop of a foreign material on the sensing surface. All cells are initially placed in a startup condition or state. Thereafter, the cells are interrogated or readout, looking for a change in the equivalent feedback capacitance that results from an electrical field shape modification that is caused by the presence of physical matter on the sensing surface. When no such change is detected, the method is repeated for another cell. When a change is detected for a cell, a particle/vapor/drop output is provided.

Abstract: A probe adapter for coupling probe tip contacts of a electrical measurement probe to leads of a surface mounted integrated circuit IC device has an insulating housing from which extend first and second flexible electrically conductive leads having a pitch geometry compatible with the leads of the IC device. First and second electrical contacts, respectively coupled to the first and second flexible electrically conductive leads, are disposed in the housing and have a pitch geometry compatible with the probe tip contacts of the electrical measurement probe.

Abstract: A probe assembly contacts pins of a flat pack or other integrated circuit (IC) package having a body with a flat upper surface and a plurality of pins extending horizontally outward from the IC package body. The probe assembly includes a base that is bonded to the upper surface of the IC package body by a thermal-releasing adhesive when the base is pressed onto the IC package body. A set of probes (spring pins) extending downward from the base contact the IC pins when the base is bonded to the IC package body. The base includes a heating element for supplying heat to warm the adhesive and weaken the adhesive bond when the probe assembly is to be removed from the IC package. The heating element generates the heat in response to a current pulse passing through the heating element or alternatively receives the heat from an external source and conducts it to the adhesive.

Abstract: A method is disclosed for detecting a contact position between an object under measurement and measuring pins. A semiconductor test device issues an instruction to a wafer prober control unit to control raising and down of a stage. When raising the stage in units of a predetermined distance a and detecting that the number of probe pins in contact with a wafer is equal to or greater than a constant value; the semiconductor test device lowers the stage in units of the predetermined distance a. When the number of contacted pins are less than the constant value, the device again raises the stage in units of a predetermined distance b smaller than the predetermined distance a; whereas, when the number of contacted pins is equal to or greater than the constant value, the device treats the position of the stage at that time as a first touch position.

Abstract: Method and apparatus for setting the contact elements (test pins) of a printed circuit board test device, which are accommodated in one or two test adapters, to the contact points, provided on one or both sides, of a printed circuit board (series) to be tested, wherein said printed circuit board (series) comprises various subsets of contact points and suitable alignment means with respect to the adapters, in particular two reference holes or reference edges. The new and inventive feature is considered to consist in the fact that at least one subset of the contact elements (S) of one or both adapters (BF, BA; TF, TA), independently of at least one further subset of the contact elements (H), and the alignment means (T) of one or both adapters are set relative to one another.

Abstract: A method and system for probing with electrical test signals on an integrated circuit specimen using a scanning electron microscope (SEM) positioned for observing a surface of the specimen exposing electrically conductive terminals on the specimen. A carrier is provided for supporting the specimen in relation to the scanning electron microscope while a computer acquires an image identifying conductive path indicia of the surface of the specimen from the scanning electron microscope. A motorized manipulator remotely controlled by the computer manipulates a plurality of probes positionable on the surface of the specimen for conveying electrical test signals inside a vacuum chamber inner enclosure which houses the scanning electron microscope, the carrier, the motorized manipulator and the plurality of probes for analyzing the specimen in a vacuum. A feedthrough on the vacuum chamber couples electrical signals from the computer to the motorized manipulator and the plurality of probes.

Abstract: A temperature control fixture for an integrated circuit under test which provides for heating or cooling of the back side of the integrated circuit while it is being tested by contacts and electrical leads applied to the opposite lead side thereof. A test housing defines a sealed test chamber within which a test mounting is provided for mounting the integrated circuit under test. The test mounting is connected to a plurality of test lines for conducting test signals between the lead side of the integrated circuit and a test instrument external to the test apparatus. The integrated circuit is mounted on the test mounting to expose the back side thereof to a flow of a heat transfer medium in the sealed test chamber to provide for cooling or heating thereof. An observation window in the test housing enables observation of the back side of device during testing.

Abstract: A scan test apparatus for continuity testing of bare printed circuit boards having a first shorting layer and a second shorting layer positioned adjacent a unit under test to electrically short the circuit on the unit under test. At least one of the first or second shorting layers includes a row of wipers for generating test signals as the wiper contacts test sites on the unit under test as the unit under test is moved across the wiper. Measurement electronics are electrically connected to the wiper for receipt of the test signals for comparison to stored data and elimination from further testing if the test signals and stored data match.

Abstract: A test fixture for matched impedance testing of a printed circuit board having a top plate for supporting the printed circuit board having matched impedance circuit traces extending from test site locations on the printed circuit board requiring matched impedance testing. Spring probes extend through holes in the top plate for transmission of test signals from the test sites on the printed circuit board to the matched impedance circuit traces. A TDR meter is wired to the top plate by coaxial connectors attached to the circuit traces to read the test signals.

Abstract: A wafer acceptance testing (WAT) method with a test key is provided. The test key structure includes a testing structure on a substrate. An inter-layer-dielectric layer covers over the substrate to isolate the testing structure. A grounded metal layer is located on the inter-layer dielectric layer. An interconnecting structure is located on the grounded metal layer. A conductive pad layer and a passivation layer are sequentially located on the interconnecting structure. The testing structure is electrically coupled to the interconnecting structure. The interconnecting structure is also electrically coupled to the conductive pad layer. The grounded metal layer is grounded without any further coupling such that the grounded metal layer is not coupled to the testing structure and the interconnecting structure.

Abstract: An integrated circuit having an embedded testing system. The integrated circuit has a plurality of chip input terminals and a plurality of chip output terminals and operates in a test mode and a normal mode. The integrated circuit includes a plurality of core modules and a test data bus. The test data bus has first and second conductors accessible from the chip input and output terminals, respectively. Each core module includes an access register for storing an access word, and a plurality of registers connected together as a first scan-chain having an input terminal for receiving data to be shifted into the registers and an output terminal for reading data shifted out of the registers. Each core module also includes a scan-in enable circuit and a scan-out enable circuit. The scan-in enable circuit connects the input terminal of the first scan-chain to the first conductor of the test data bus.

Abstract: An integrated circuit testing device includes a flexible base of an insulating material, the base having a first surface and a second surface opposite to each other, an integrated circuit to be tested being bonded to the first surface. A conductive wiring layer is provided on the first or second surface of the base, the wiring layer including a plurality of projecting contacts over the first surface at positions which electrodes of the integrated circuit are connected to. An elastic member is provided beneath the second surface of the base opposite to the first surface, the elastic member having a first level of hardness. A flexible film member is provided between the second surface of the base and the elastic member, the film member having a second level of hardness higher than the first level of hardness of the elastic member.

Abstract: A method of measuring total charge of an insulating layer on a semiconductor substrate includes applying corona charges to the insulating layer and measuring a surface photovoltage of the insulating layer after applying each of the corona charges. The charge density of each of the corona charges is measured with a coulombmeter. A total corona charge required to obtain a surface photovoltage of a predetermined fixed value is determined and used to calculate the total charge of the insulating layer. The fixed value corresponds to either a flatband or midband condition.

Abstract: A technique for reducing standby leakage current in a circuit block using input vector activation. A complex circuit includes a plurality of inputs and one or more transistor stacks. At least some of the transistor stacks are coupled to at least one of the inputs. The circuit also includes logic to apply a selected input vector to the plurality of inputs during a standby mode. The input vector is selected based on a configuration of the one or more transistor stacks in the circuit block to turn off a first number of transistors in the transistor stacks. The first number is within a selected percent of a maximum number of transistors in the transistor stacks that can be turned off by any vector applied at the plurality of inputs.

Abstract: A programmable bus hold circuit which may find application in programmable logic devices, memories and other I/O devices may include a first element for receiving a voltage from an I/O pad and programmable circuitry coupled to the first element for controlling whether the voltage at the pad is to be held its current logic level. The first element may be a logic gate (such as a NOR gate) the programmable circuit may include a tristatable buffer (e.g., under the control of a memory cell or other programmable bit capable of enabling or disabling the programmable bus hold circuit) or a switch (e.g., a transistor).

Abstract: Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

Abstract: A programmable logic device includes a global clock structure and a plurality of localized clock structures. Each localized clock structure distributes a respective localized clock signal to a corresponding portion of the programmable logic device. The global clock structure distributes a global clock signal to all portion of the programmable logic device.

Abstract: A method for implementing a large multiplexer with FPGA lookup tables. Logic that defines a multiplexer is detected and implemented according to the number of inputs and the target FPGA architecture. In one situation, a large multiplexer is implemented in two stages. The first stage implements wide AND functions of each of the input signals using lookup tables and carry logic. In a second stage, the resulting decoded input signals are combined in a wide OR gate again formed from lookup tables and a carry chain. In another situation, the multiplexer is implemented as a tree structure using lookup tables that implement 2:1 multiplexers in combination with other 2:1 multiplexers provided by configurable logic blocks of the FPGA.

Abstract: A programmable logic device has logic array blocks (“LABs”) and interconnection resources. For interconnecting signals to, from, and between the LABs, the global interconnection resources may include switch boxes, long lines, double lines, single lines, and half- and partially populated multiplexer regions. The LAB includes two levels of function blocks. In a preferred embodiment, there is one four-input second-level function block for every four-input first-level function blocks. At least one tri-state buffer is provided in each LAB. Each tri-state buffer may receive a data signal either from one or more function blocks in the associated LAB or from one or more interconnection conductors adjacent to the LAB. The tri-state buffer may buffer one of the received data signals and apply the resulting buffered signal to one or more of the interconnection conductors adjacent to the LAB.

Abstract: A Field Programmable Gate Array (FPGA) device includes a plurality of input/output blocks (IOBs) and variable grain blocks (VGBs). An inter-connect network provides efficient and flexible routing of control signals from VGBs to IOBs. Control signals may include individual control signals to a predetermined IOB or common control signals to a plurality of IOBs. The inter-connect network includes vertical and horizontal inter-connect channels. The inter-connect channels are coupled to switch boxes having line segments or stubs. The line segments are coupled to an IOB control multiplexer which output control signals to IOBs. The use of stubs allows for efficient and flexible use of interconnect resources.

Abstract: A programmable logic device (PLD), such as a field-programmable gate array (FPGA), includes an integrated delay-locked loop that produces a lock signal internal to the FPGA. The FPGA also includes a sequencer and related global signals adapted to configure the FPGA using external configuration data. The sequencer disables the FPGA during the configuration process. The sequencer then continues to disable the fully configured FPGA until receipt of the lock signal. The configuration process, including the establishment of a valid internal clock, is controlled entirely within the FPGA. In one embodiment, an FPGA can be fully or partially reconfigured without powering down the device. The delay-locked loop maintains a lock on the clock signal so that the sequencer need not wait for the lock signal after reconfiguration.

Abstract: A cyclic redundancy check (CRC) register is connected to the bi-directional bus and a packet processor in a configuration circuit of an FPGA. The CRC register performs transmission error detection functions based on the command/data transmissions to various registers connected to the bus, and based on the address information transmitted from the packet processor to an address/operand decoder used to enable the various registers to receive subsequent command/data words. The CRC register calculates a check-sum value in accordance with a predetermined equation. At any time during the transmission (e.g., halfway through configuration or at the end of configuration), a pre-calculated check-sum value is transmitted to the CRC register that represents an expected check-sum value at the selected time. The pre-calculated check-sum value is then compared with the check-sum value currently stored in the CRC register.

Abstract: A logic circuit which is driven at low voltage and operates at high speed and low power consumption is provided. Substrate potentials of P and N type transistors MP11 and MN11 constituting an inverter are controlled correspondingly to a stable state of the inverter. In a stable state of the inverter in which the P type transistor MP11 is ON, the substrate potential of the N type transistor MN11 which is OFF is lowered to ground potential or lower and, in a stable state of the inverter in which the N type transistor MN11 is ON, the substrate potential of the P type transistor MP11 which is OFF is raised to a power source potential or higher.

Abstract: A voltage level translator is disclosed which translates a CMOS input signal into a CMOS output signal where the low voltage level of the output signal is equal to the high voltage level of the input signal. The voltage level translator is described in an integrated circuit such as memory circuits, including DRAMs. Specifically, the voltage level translator produces an output signal which can be used as a gate voltage on a pre-charge transistor for a booted circuit where the gate voltage need only drop to the high voltage level of the input signal to shut the transistor off. The voltage level translator described, therefore, reduces the time and power required to translate an input signal by limiting the voltage swing of the output signal.

Abstract: An input buffer is provided that converts a TTL logic signal to a CMOS logic signal and controls an CMOS output level while eliminating static current consumption even when an external bias voltage is changed. The input buffer improves a low-to-high input signal switching speed. Further, the input buffer can be used for low current and high-speed operation. The input buffer includes an inverter unit having pull-up and pull-down transistors with commonly coupled drains coupled between a power supply voltage and a ground voltage. The input buffer further can include a transistor control unit that receives an output signal of the input buffer to completely turn off the pull-up transistor when the TTL input signal is a high level and rapidly turn on the transistor when the TTL input signal is a low level.

Abstract: A domino logic circuit includes a first domino gate that evaluates one or more inputs responsive to a clock signal, a reset gate, and a second domino gate having a first input coupled to the output of the first domino gate. A first input of a reset gate is coupled to the output of the first domino gate, with a second input of the reset gate being coupled to the output of the second domino gate. The reset gate outputs a precharge signal coupled to a second input of the second domino gate when the second domino gate is discharged and the output of the first domino gate changes state such that a high-to-low transition occurs at the first input of the second domino gate.

Abstract: High-speed signal translators are provided to convert differential input signals (e.g., ECL signals) to single-ended output signals (e.g., CMOS signals). An exemplary translator is formed with first and second current mirrors, first and second complimentary differential pairs of transistors, a complimentary transistor output stage and first and second current-diverting transistors. The complimentary output stage initially generates the single-ended output signal in response to currents received from the complimentary differential pairs. When the output signal has been established, the current-diverting transistors respond by carrying at least portions of the currents supplied by the complimentary differential pairs. The current-diverting transistors also drive the current mirrors to divert other portions of these currents away from the complimentary output stage. Stored charges in the output stage are accordingly reduced and its response time enhanced.

Abstract: A comparator circuit (40) includes a comparator network and a comparator enabling device (80) and may be integrated with a sense amplifier circuit (41). The comparator network is adapted to receive a complementary pair of reference data signals (B, B13) and a complementary pair of analog data signals (d1, d1b). An output of the comparator circuit (40) represents a comparison of the data represented by the reference data signals and the data represented by the analog data signals. The comparator output is generated in response to a comparator enable signal (SE) applied to the comparator enabling device (80) while the input data is applied to the comparator network. The comparator enable signal (SE) is applied at a time when the analog data signals (d1, d1b) have developed a minimum differential level.

Abstract: A bipolar peak detector that maintains the charge on its capacitor longer than prior art peak detectors can due to the discharging thereof that occurs during long periods of reception of only a single value in the received signal, e.g. a long string of zeros, by substantially exactly duplicating, i.e., duplicating to within manufacturing tolerances, the current that is leaking out of the capacitor and injecting the duplicate current into the capacitor.

Abstract: A time-multiplexed common mode feedback circuit provides a common mode feedback signal during active phases of a clock signal. The common mode feed back circuit includes capacitors which are charged during the inactive phases of the clock signals. In one embodiment, the common mode feedback signal is provided by two generator circuits each driven by a respective one of two non-overlapping clock signals. In that embodiment, the generator circuits provide the common mode feedback signal during the active phases of their respective clock signals.

Abstract: A multi-input comparator determines a minimum or maximum signal value in a given set of signal values. In an illustrative embodiment, a multi-input comparator includes a number of interconnected inversion circuits, with each of the inversion circuits having an input node associated therewith. The input node of each of the inversion circuits is coupled to an output of at least one of the other inversion circuits. As a result, after activation of the inversion circuits, the voltages at the input nodes are indicative of the relative magnitude of the signal values previously applied thereto. The inversion circuits may be constructed using, for example, single-inverter or multiple-inverter building blocks. Additional inputs can be provided by replicating the corresponding single-inverter or multiple-inverter blocks.

Abstract: In a voltage comparator, a positive feedback circuit having first and second inverters compares the potential of the input terminal of the first inverter with the potential of the input terminal of the second inverter and outputs the comparison result from the output terminal of the second inverter. A first input circuit supplies the first potential corresponding to an input comparison voltage to the input terminal of the second inverter. A second input circuit supplies the second potential corresponding to an input reference voltage to the input terminal of the first inverter. A control circuit supplies a power supply voltage to the positive feedback circuit when an input control signal represents a comparison operation period to execute voltage comparison operation. When the control signal represents an initialization period, the control circuit stops supplying the power supply voltage to set an initial state.

Abstract: A driver circuit having series-connected high-side and low-side MOS switches with MOS transistors for driving a load, a temperature-limiting circuit and a current-limiting circuit, which is assigned to one of the two MOS transistors. In order to balance power losses between the high-side and low-side MOS switches, provision is made for the gate of the MOS transistor without the current-limiting circuit to be connected to ground via a voltage generator, whose voltage corresponds to a maximum drive voltage for this MOS transistor.

Abstract: A method and apparatus for compensating for input threshold variations in input buffers is provided. The method and apparatus compensate for input threshold variations by applying a bias voltage on a known capacitance of an RC calibration circuit using, for example, a pulse width modulator. The bias voltage helps ensure that the time to charge the known capacitance from the bias voltage to the input threshold voltage of the input buffer is independent of the threshold voltage. The bias voltage is chosen using an iterative process in which the time to charge from the bias voltage to the threshold voltage is compared with a reference time. The bias voltage is adjusted based on the comparison.