Abstract: An integrated circuit includes a first adjustable delay unit to which a first clock signal is fed and a second adjustable delay unit to which a second clock signal is fed. A phase detector is connected to the input and to the output of the first delay unit. A control unit serves for correcting a phase difference obtained by the phase detector and controls the delay time of the first delay unit in a corresponding manner. The control unit additionally sets the delay time of the second delay unit to essentially the same value as that of the first delay unit. Furthermore, the output of the second delay unit is connected to the input of a third adjustable delay unit.

Abstract: A circuit for selectively controlling the slew rate of a signal on a data line. A capacitor is connected at one end to a common terminal of a power supply and to a switching circuit. The switching circuit advantageously connects the capacitor to the data line in response to a control pulse, capacitively loading the data line so that slew rate is decreased. When the control pulse assumes a different state, the capacitor is connected by the switching circuit to a terminal of a power supply, and acts as a decoupling capacitor. The dual role of the capacitor provides for efficient circuit layout by utilizing one component in two functions.

Abstract: A D flip-flop circuit operating in master-slave configuration which has low power consumption and is capable of high-speed operation, and a method for lowering power consumption in such a circuit is provided. The circuit embodiment includes two latches, each with a switching and memory section, and two interlaced current sources. In response to the active high clock signal the master latch memory section uses the current from the first current source while the slave latch switching section uses the current from the second current source, and vice versa. The switching section of each latch is biased with a higher current than the memory section, to provide the circuit with low power consumption. The output current provided to the switching section is preferably substantially twice the magnitude of the current provided to the memory section. The ratio of the currents of the current sources for the switching and memory section is preferably in the range of about 30% to 70%, depending on the clock frequency.

Abstract: Disclosed is a delay circuit for delaying at least the timing of a rising edge or the timing of a falling edge of an input signal alternating between first and second levels. The delay circuit includes (1) a charge pump in which first and second field-effect transistors of different channels are serially connected; (2) a capacitor connected in parallel with the first field-effect transistor; (3) a charging current control circuit for passing a charging current into the capacitor via the second field-effect transistor of the charge pump when the input signal is at the first level; (4) a discharge current control circuit for releasing a discharge current from the capacitor via the first field-effect transistor when the input signal is at the second level; and (5) a discrimination circuit for outputting a signal of a prescribed logic level based upon a terminal voltage of the capacitor.

Abstract: In an integrated circuit comprising a so-called “switched” capacitor, the latter is switched by a parallel circuit of two complementary switching transistors having mutually complementary switching pulse trains. Due to parasitic effects during this switching operation, disturbing offset voltages arise at the switched capacitor. In order to avoid such offset voltages, the edges of the one switching pulse train are shifted in time with respect to the corresponding edges of the complementary switching pulse train. To this end, a switching pulse generator contains a delay member fed with a control signal which is formed by means of a constant reference voltage using a dummy or simulation of that circuit that contains the switched capacitor.

Abstract: A clock generation circuit comprises a clock wiring having opposed first and second ends, through which a clock is transmitted from the first end to the second end, and a plurality of clock phase adjustment circuits for generating internal clocks in accordance with the clock supplied from the clock wiring. Each of the clock phase adjustment circuits comprises a first-end side terminal and a second-end side terminal which are connected to a first-end side point and a second-end side point of the circuit, respectively, the points being positioned on both sides of a reference point of the clock wiring; a delay line for delaying a clock supplied from one of the terminals and outputting an internal clock; and a delay control circuit for performing feedback control on a delay of the clock in the delay means in accordance with the phase of the clock supplied from the other terminal so that the phase of the internal clock matches the phase of the clock at the reference point of the cock wiring.

Abstract: A Semiconductor integrated circuit with a protection circuit against electrostatic discharge. A clamping element is connected with MIS transistor to prevent the breakdown under the charged device model. A parasitic bipolar transistor, a MOS transistor or MIS transistor whose gate is composed of an insulating film thicker than that of the transfer gate, can be used as the clamping element.

Abstract: A data communication interface between a high-power device and a low-power device enabling wherein a cable having connectors at its both ends connects the high-power device and the low-power device; and the low-power device has its own incorporated level conversion circuit and drives same with a voltage which is supplied as a source voltage for the low-power device. The circuit receives a data signal at voltage levels compatible with the high-power device. The circuit converts the received signal into a data signal which is acceptable by the low-power device. The circuit receives from the low-power device a data signal at voltage levels compatible with the low-power device, and also converts the received signal into a signal which is acceptable by the high-power device. The level conversion circuit needs no element, such as a zener diode, for lowering (clamping) a voltage because the circuit is powered by the low-power device.

Abstract: The invention relates to an electronic circuit, and in particular embodiments to a level shifting circuit having an output common mode voltage independent of the input common mode voltage, and unity differential signal gain. The circuit receives first and second input voltages, referenced to a first voltage supply rail, and has first and second resistors, each connected to the first input terminal, and third and fourth resistors, each connected to the second input terminal, the second and third resistors having equal resistance values. The first resistor is also connected to a first output terminal, the fourth resistor is also connected to a second output terminal, and the second and third resistors are also connected together at a reference node.

Abstract: A circuit is presented comprising a first device and a second device. The first device may be configured to operate at a first supply voltage and may be configured to generate a pull-up signal in response to an input signal. The second device may be configured to operate at a second supply voltage. The second supply voltage may be lower than the first supply voltage. The second device may be configured to generate an output in response to (i) the input signal and (ii) the pull-up signal.

Abstract: An integrated switched capacitor bias circuit for generating a reference signal which is proportional to absolute temperature, a capacitance and a clock signal frequency. A current mirror circuit generates a primary current and a mirrored current. Under the control of a clock signal, a switched capacitor circuit uses the mirrored current to constantly accumulate charges on primary capacitor while also alternately sharing such charges with and then discharging one of two additional capacitors. The magnitude of the current drawn by the switched capacitor circuit is a factor of the junction area of a diode and absolute temperature. To maintain equality of the primary and mirrored currents, a node voltage within the current mirror circuit is monitored by a bias circuit which provides a bias signal for controlling the current mirror circuit.

Abstract: A mixer circuit includes a first transistor and a second transistor of different conduction types which are connected and the emitter of the first transistor is connected to the collector of the second transistor, and the collector of the first transistor is connected to the emitter of the second transistor, a third transistor, whose collector is connected to the emitter of the first transistor, a power supply terminal connected to the collector of the first transistor, a radio frequency (RF) terminal connected to the collector of the first transistor, a local signal (LO) terminal connected to the base of the first transistor, an intermediate frequency (IF) terminal connected to the base of the second transistor, and a ground terminal connected to the emitter of the third transistor.

Abstract: A gating circuit for largely glitch-free gating of analog signal values obtained in a periodic sequence, capacitively buffer-stored, digitized by means of an A/D converter and subsequently erased before a next signal value is obtained in the capacitive buffer store. A first operational transconductance amplifier (OTA) capable of being activated by a gating pulse has a non-inverting input connected to the reference-earth point of a capacitive store and an output connected to the charging terminal of the capacitive store. Its inverting input is connected through an impedance converter and a resistor, which limits the discharge current, to the charging terminal of the capacitive store. A second OTA serves as a signal driver whose gain is predetermined by the ratio of the value of a resistor connected in parallel with the capacitive store to that of a series resistor that determines the potential at the inverting input of the second OTA.

Abstract: A method for turning a GTO on and off and a corresponding driving circuit are specified. A turn-on current and a holding current are generated from voltage pulses which are converted into currents with the aid of an electric energy store. In terms of circuitry, it is particularly advantageous when the required voltage pulses are drawn from the same energy source, or the same energy store, as the pulse required to generate the turn-off current. The holding current is preferably generated by repeating voltage pulses. The repetition frequency of said voltage pulses can then be increased or reduced as required. The frequency is reduced, in particular, when the gate-cathode voltage becomes negative, and is increased again when the voltage is positive again.

Abstract: A zero static power laser fuse circuit is formed from one laser fuse and three transistors, with the fuse connected in series to a reverse-biased diode and with the common node of the fuse and diode connected to the input of a driving circuit, such as a CMOS inverter. Blowing the fuse allows a small subthreshold conduction current to flow to the common node and pull the node to the opposite logic state. This fuse circuit, which allows the capacitance at the common node to be minimized for zero static power operation, requires less circuit area than previous zero static power fuse circuits.

Abstract: A charge pump circuit is provided which includes a plurality of successively coupled charge pump stages. Each of these successively coupled charge pump stages receives at least one input signals and at least one clock input signals, and in accordance therewith, conveys at least one output signal. Significantly, at least one output signal of a prior charge pump stage is substantially equal to at least one input signal of a next adjacent charge pump stage, so that the prior adjacent charge pump stage will be effectively shut off, so that reverse current flow can be prevented through the charge pump circuit.

Abstract: Higher write speeds in hard disk write preamplifiers require higher supply voltages. The voltage across an inductive write head, VL, is proportional to the value of inductance, L, and to the speed at which the write current is reversed, di/dt. Accordingly, the write current reversal time in inductive write-heads fundamentally depends on how large a voltage can be impressed across the write drive head. The proposed circuitry and method provides a voltage boost circuit for hard disk drive preamplifiers that satisfies the demand for improved rise-time while meeting the conflicting demand for maintaining a same supply voltage.

Abstract: A bandgap reference circuit (10) with improved startup circuitry is disclosed. The bandgap reference circuit (10) includes a startup node (NBIAS) that is connected to the gates of n-channel MOS transistors (38n, 39n) in first and second conduction legs of a current mirror. A series of inverters (51, 53, 55) turn on a transistor (50) that is connected between a precharge node (TO) and the startup node (NBIAS) in response to a signal (RID) indicating recent power-up of a power supply voltage (Vdd). A capacitor (60) is also provided, and which is discharged upon power-down. The capacitor (60) is connected to the gate of a p-channel transistor (70) that has its source/drain path connected between the precharge node (TO) and the startup node (NBIAS), and that is turned on upon power-up, even if the power-up signal (RID) is not generated, thus ensuring initiation of the bandgap reference circuit (10).

Abstract: An electronic circuit having an actuator, which is used for controlling high currents. The actuator includes multiple partial actuators, each of which is regulated according to temperature. The partitioned temperature-dependent regulation of the partial actuators used to homogenize the thermal load on the actuator.

Abstract: A temperature-compensated high precision current source provides a constant current regardless of temperature change, thereby ensuring the stability of electric circuits.

Abstract: A condenser having a huge area is required to reduce a noise on LSI power supply nets (−&Dgr;VDD) of an integrated circuit because a bypass condenser can only utilize a part of accumulated electric charges. A noise of LSI power supply nets is suppressed by generating a noise of a reversed polarity (+&Dgr;VDD) to the noise on the LSI power supply nets (−&Dgr;VDD), based upon a noise reducing circuit discharging a condenser charged with a high voltage. A noise reduction effect equivalent to a bypass condenser having a large capacity is obtained even when a condenser having a small capacity is used.

Abstract: A switched-capacitor cosine filter circuit includes a differential amplifier and a switched-capacitor circuit. A set of control signals cause the switched-capacitor circuit to selectively couple the inputs and output of the differential amplifier thereby producing a switched input signal for the differential amplifier. During alternating states of the control signals, the switched-capacitor cosine filter circuit samples the input signal as a noninverting and inverting integrator circuit.

Abstract: A quadrature demodulator detects a phase angle error determined from the phase angle supplied from constellation symbols of outgoing in-phase and quadrature components of a modulated signal and and the phase angle of a NCO. The quadrature demodulator comprises a receiving circuit for receiving a quadrature modulated signal, and a local oscillator for generating a local carrier. A complex multiplier demodulates the quadrature modulated signal by complex-multiplying the quadrature modulated signal with the local carrier generated in the local oscillator. A symbol error detector detects a symbol error between the carrier of the modulated signal and the local carrier supplied from the signal demodulated at the complex-multiplier. A feedback loop controls the local carrier generated at the local oscillator by feeding back the symbol error detected at the symbol error detector to the local oscillator.

Abstract: The invention concerns a class D amplifier in which a high-frequency reference signal is pulse width modulated by an input signal, such as an audio signal, and in which there are generated a pair of bipolar pulse drive signals, comprising an error generator which forms a signal with an average value which corresponds to the DC component of the pulse drive signals, and which is fed back to the pulse width modulator for the adjustment of the modulator. The high-frequency reference signal is generated from a first clock signal, and the individual pulses of the respective pulse drive signals are controlled via a second clock signal which is derived from the first clock signal.

Abstract: A signal output assembly for an inductive output amplifier comprises a primary output cavity including a drift tube enclosing a modulated electron beam. The density modulated beam passes across a gap separating portions of the drift tube and induces an amplified RF signal into the primary output cavity. A secondary output cavity comprises a coaxial resonator terminated in an inductive coupling loop, and a waveguide having a ridge. The coaxial resonator and the inductive coupling loop have a combined electrical length approximately equivalent to an odd multiple of one-quarter wavelengths of the input signal (n&lgr;/4), where n is an odd integer. The coaxial resonator is electrically connected perpendicularly to a center of the ridge such that first and second portions of the ridge extend in opposite directions from the connection with the coaxial resonator to respective ends of the waveguide.

Abstract: The invention relates to a method and apparatus for reducing the distortion output of an amplifier used with an RF signal. The method and apparatus typically modify the distortion of the amplifier to reduce it, by detecting cross-modulation components modulated onto a continuous wave, low level, pilot signal injected at the input of the amplifier system. The circuitry detects the cross-modulation components and provides correction signals in response thereto.

Abstract: An RF amplifier includes an oscillator developing an RF input signal to be transmitted. A power amplifier receives the RF input signal and amplifies the RF input signal to develop an RF output signal. An amplifier control is operatively associated with the oscillator and the power amplifier. The amplifier control includes means for developing a control signal representing a desired amplitude of the RF output signal. A memory stores correction information correlating actual amplitude of the RF output signal relative to the control signal, and a control varies the power amplifier circuit supply voltage using the control signal modified responsive to the correction information for the desired amplitude.

Abstract: A differential amplifier circuit for amplifying and outputting a differential voltage between a pair of input terminals includes a voltage-to-current converting circuit, a current amplifying circuit, and a current-to-voltage converting circuit. In the voltage-to-current converting circuit, each of the input terminals is connected with one end of each of resistances, a potential on the other end of each of the resistances is kept constant by a feedback circuit, and an electric current corresponding to the differential voltage flows into a first differential circuit. In the current amplifying circuit, the electric current corresponding to the differential voltage and flowing into the first differential circuit is amplified and then flows into a second differential circuit. In the current-to-voltage converting circuit, an electric current outputted from the current amplifying circuit is converted to a voltage to be outputted.

Abstract: Methods and apparatus to tune a transconductance stage include a current source and a six inverting amplifier stage. The current source establishes the biasing points of first and second inverting amplifiers, which in turn, provide a signal to a common mode feedback loop. By establishing the biasing points of the first and second inverting amplifiers, the transconductance of these inverting amplifiers may be controlled. Control of the transconductance permits control of the cut-off frequency of the transconductance stage. Furthermore, the ability to control the transconductance allows for control of the DC gain. In addition, establishing the biasing points of third and fourth inverting amplifiers by a second current source further controls the transconductance of these inverting amplifiers. Thus, further control of the transconductance permits further control of the cut-off frequency and DC gain of the transconductance stage. Therefore, tunability of the transconductance stage is provided.

Abstract: An RF power amplifier has an RF driver stage that also provides a temperature independent reference current to the RF output power amplifier. A diode reference serves as both a DC current reference and as the first RF amplifier stage. Less DC power is consumed since no circuitry is used exclusively for establishing a DC reference.

Abstract: A frequency synthesizer comprises a single phase-locked loop controlled by a reference clock formed by a voltage-controlled oscillator, a programmable divider with variable division rank M, a phase detector, and a loop filter. It also comprises a predetermined number n of fractional division structures, each implementing a frequency step Pi×FreF lower than the reference frequency Fref.

Abstract: An oscillator circuit having a topology that provides for high-speed oscillation in an even number of phases. The topology generally comprises an even number of inverting circuit elements generally including a keeper and an even number of inverters. The circuit elements are connected such that each output of each circuit element is coupled to at least one input of a neighboring circuit element such that a signal traversing a closed path is inverted an odd number of times. One oscillator is implemented using circuit elements containing a keeper having two nodes and two pairs of inverters. The outputs of one pair of inverters are tied to a first node of the keeper and the outputs of the other pair are tied to a second node. In a preferred embodiment, the oscillator circuit contains four such circuit elements arranged in a ring such that the outputs of each circuit element are coupled to the two neighbor circuit elements.

Abstract: An oscillator in an integrated circuit in which the oscillator signal is taken from the output of a comparator, and the decision level of the comparator is determined by the voltage difference between the input of the comparator and the substrate of the integrated circuit. Interference voltages on the substrate, caused by other circuitry on the integrated circuit, are compensated with equal interference voltages at the input of the comparator. To effect this compensation, a capacitor is connected between the input of the comparator and the substrate, in lieu of the conventional capacitor that is connected between the input of the comparator and a ground potential.

Abstract: A circuit including an oscillator circuit, a current generator circuit and a voltage generator circuit. The oscillator circuit may be configured to generate an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal. The current generator may be configured to generate said first control signal in response to a first adjustment signal. The voltage generator circuit may be configured to generate the second control signal in response to a second adjustment signal.

Abstract: There is disclosed an oscillator circuit in which the first capacitor is connected between the input side of a CMOS inverter in a quartz oscillator circuit and a higher potential side, the second load capacitor is connected between the input side of the inverter and a lower potential side, the third load capacitor is connected between the output side of the inverter and the higher potential side, and the fourth load capacitor is connected between the output side of the inverter and the lower potential side, so that variation in amplitudes of the voltage sources synchronized with the oscillation can be reduced with the realization of lower current consumption. There is also disclosed an oscillator circuit of reduced circuit scale. A CMOS inverter for producing oscillations an AC coupling capacitor, and a buffer circuit are formed on one chip. A protective circuit that has been heretofore required at the input terminal portion of the buffer circuit can be dispensed with.

Abstract: A clock circuit includes an oscillator having a biasing node that causes the oscillator to enter a low-power state. The clock circuit also includes a kick-start circuit and a first mechanism. The kick-start circuit operates to provide an excitation to the oscillator, where the excitation enables the oscillator to start its oscillation. The first mechanism is configured to inhibit kick-start based on certain conditions, such as when the oscillator reaches a particular level capable of sustaining oscillation by itself or when the oscillator is already running.

Abstract: Methods of active echo reduction on a multi-drop bus utilizing devices of dynamically-variable impedance, wherein non-signaling intermediate devices are placed in a high-impedance state while all remaining devices are matched to the characteristic impedance of the multi-drop bus. Devices of dynamically-variable impedance capable of implementing methods of active echo reduction on a multi-drop bus are included, as well as systems incorporating such devices.

Abstract: A manifold is constructed with a primary manifold section to which the input wave guides are connected and a tuning section attached to the output of the primary manifold section. The tuning section is constructed of a deformable material which allows the dimpling of the internal wall to alter the impedance of the waveguide system for the purpose of fine tuning the impedance matching of the manifold.

Abstract: A coupling circuit (22) for a radiofrequency (RF) receiver (10) has an attenuator (38) and a resonator (40). Three resistors (42,44,46) of attenuator (38) provide a lossy resistive isolation between a first mixer (20) and a crystal filter (24) of (RF) receiver (10) for undesired signals such as noise and harmonics. Thus, signal reflections between first mixer (20) and crystal filter (24) are absorbed for these undesired signals. However, for desired signals at an intermediate frequency (IF), resonator (40) has an inductor (54) and a capacitor (56) to resonate with such desired signals at the IF. As a result of resonance, resistors (42,46) are isolated to alleviate attenuation of the desired signals.

Abstract: In a stripline configuration, a laminated lowpass filter circuit includes first through fifth dielectric substrates arranged in that order in a stack, first and second groundplane conductor layers disposed on the outer surfaces of the stack, and a shielding conductor layer formed on the third dielectric layer. First and second side electrodes are formed on sides of the stack. A stripline providing an inductive element is formed on the fourth dielectric layer, and first and second conductor plates providing capacitive elements are formed on the first and second dielectric layers. The terminal of the first conductor plate and a first end of the stripline are connected to the first side electrode. A terminal of the second conductor plate and a second end of the stripline are connected to the second side electrode. The first and second side electrodes constitute input and output terminals of the laminated lowpass filter circuit.

Abstract: A laminated body includes a first insulating sheet having first internal conductors disposed thereon, a second insulating sheet having second internal conductors are given, and a protective sheet, wherein the internal conductors define inductors. The first insulating sheet, the second insulating sheet and the protective sheet are stacked on top of each other and laminated to define the laminated body. When a distance between the end surfaces in a length direction of the laminated body and the inductors located adjacent the end surfaces is less than a fixed value, the internal conductors defining the inductors on the side of the end surfaces are arranged in a zig zag pattern which extends toward inner inductors.

Abstract: A coaxial resonator according to the present invention has an outer conductor on an outer peripheral surface of a dielectric block having at least four side surfaces and having a through hole provided in its approximately central part and an inner conductor on an inner peripheral surface of the through hole, and one of two end faces perpendicular to the through hole is opened and the other end face is short-circuited. A pair of an input electrode and an output electrode which are not brought into electrical contact with the outer conductor and are independent of each other is provided in a position in proximity to the opened end face on the outer peripheral surface of the dielectric block, and respective portions of both the electrodes are extended to the side surfaces, which are respectively adjacent to the electrodes, of the dielectric block.

Abstract: A laminated filter comprising a laminated body created by laminating a plurality of dielectric sheets, a resonator electrode disposed on an inner part of the laminated body, and an input-output electrode disposed on the inner part of the laminated body at a position facing the resonator electrode through the dielectric sheet. A stub electrode is connected to the input-output electrode.

Abstract: A duplexer for microwave signals that requires no system of settings by screws. The duplexer includes two tunnels, each having a longitudinal passage and compartments demarcated by transversal partition walls. The compartments, the longitudinal passages and the common part are hollowed out in the plane upper surface of a monolithic block. The tunnels are closed on the top by a lid that adheres uniformly to the plane surface.

Abstract: An apparatus and method for a micromechanical electrostatic relay that includes a base substrate and a carrier layer deposited onto the base substrate. The carrier layer includes an armature and stationary-contact spring tongues that engage each other at their respective free ends. Once engaged, the armature spring tongue moving contacts overlaps the respective stationary-contact spring tongue stationary contacts. During an electrostatic rest state, the armature and stationary-contact spring tongues curve away from the base substrate wherein their respective free ends no longer engage.

Abstract: A plug socket for relays has contact chambers that comprise plug slots open toward an upper base member side for the acceptance of flat plugs and into which plug jacks are inserted proceeding from the underside. These plug jacks have catch tongues branched off at both sides for latching in catch channels of the contact chambers. The contact chambers with the inserted plug jacks are narrower than the plug slots and are offset in alternation toward the ends of the plug slots. The oppositely applied catch channels are thus offset relative to one another in the partitions. In this way, more standard contact jacks can be accommodated in standardized contact chambers in the same space than present aligning arrangement of the contact chambers.

Abstract: A current transformer includes transformer units combined into a bundle, each of the transformer units including an annular iron core surrounding a bus conductor and a secondary winding wound around the iron core for measuring an electric current flowing through the bus conductor, and a shield winding wound around the bundle of the transformer units. The secondary winding may be provided with an air gap in which no secondary winding is present, located at a portion of the current transformer in a direction of a resultant vector, perpendicular to a line connecting bus conductors neighboring the bus conductor to be measured and passing through the bus conductor to be measured. A second air gap may be provided at the position opposite the air gap of the transformer, relative to the bus conductor to be measured, and the shield winding may be divided into two parts at the air gap and opposite the air gap relative to the bus conductor to be measured.

Abstract: An ignition coil that can be easily assembled, that assures co-axial alignment of a primary coil, a secondary coil and a center core part, and that generates desired high voltage. A core body is formed to have an outer diameter larger than that of a permanent magnet so that the permanent magnet will not protrude out of the outer peripheral face of the core body. Accordingly, when the center core part is inserted into a secondary spool, the center core part is not caught by the secondary spool and may be readily inserted and assembled therewith. Also, because no bulge is created at the center core part, it is possible to prevent the center core part from tilting within the secondary spool and to readily assure the co-axial alignment of the primary spool, the secondary spool and the center core part. Thus, voltage generated by the secondary coil is prevented from dropping, and high voltage may be applied to the ignition plug.

Abstract: A small-sized heat resisting high voltage transformer and an ignition transformer using the high voltage transformer are provided and utilize both a heat resistant casting resin and a bobbin, which contain an inorganic filler. The high voltage transformer is capable of producing an output voltage of 10-35 kV and comprises a primary coil, a secondary coil, and a magnetic core, wherein a casting resin is injected into the coil part and subsequently cured. The casting resin and bobbin material used for making the coils have heat distortion temperature of at least 130° C., and contain an inorganic filler. The surface of the bobbin may be pretreated. Thereby, adhesion between a bobbin and a casting resin is enhanced to ensure operating properly under the sever heat cycle condition and provide a small-sized heat resistant high voltage transformer.

Abstract: Methods and apparatus are disclosed for suppressing or eliminating nonlinear current drawing characteristics, while at the same time substantially eliminating high order current harmonics. In accordance with various aspects of the present invention, an energy transfer system, for example a pulse width modulator (PWM) flyback converter (22), comprises an inductor (L) interposed between the AC line voltage and the load (Rload), with a controllable switch (26) provided between the inductor (L) and the negative supply leg of a rectifier circuit (10). The duty cycle of the converter switch (26) is suitably controlled to produce a substantially constant DC output from the converter (22). Proper synchronization of the converter switch (26) ensures that the current through the inductor (L) and the output current through the load (Rload) remains in phase with the AC supply voltage. Thus, a power factor on the order of unity is maintained while substantially eliminating nonlinear current drawing characteristics.