Abstract: A high dielectric constant (HDC) capacitive dielectric film is fabricated in a capacitor structure using relatively high pressure surface treatments. After forming the HDC capacitive dielectric film on a supporting bottom plate electrode structure, a surface treatment comprising oxidation, at a pressure of at least approximately one atmosphere and temperatures of approximately at least 200 degrees Celsius densifies/conditions the HDC capacitive dielectric film. When using a polysilicon, crystalline silicon, hemispherical grain polysilicon, germanium, or silicon-germanium bottom plate electrode, a relatively high pressure surface treatment, comprising rapid thermal nitridation or oxidation, is used after forming the bottom plate electrode, forming a diffusion barrier layer in a controlled manner.

Abstract: After an SAC film is formed to a thickness not to fill the spaces between gate electrodes in a memory cell region, a silicon oxide film is formed to a thickness to fill the spaces. A side wall made of a silicon oxide film is formed on the side surface of only a gate electrode in a peripheral circuit region, and a metal silicide is formed on the exposed substrate surface. A BLC film is formed on the entire surface. A contact hole is formed in self alignment using the SAC film and the BLC film. In this method, silicidation of the source/drain of a transistor in the peripheral circuit region and the self-alignment technique such as BLC or SAC can be simultaneously used to enable an increase in the degree of integration and improvement of performance of a semiconductor device having a metal silicide on the transistor in the logic circuit.

Abstract: A method of fabricating a trench capacitor having high capacitance for ULSI technology below the sub-micrometer scale is provided. The method includes: form a trench on a semiconductor substrate. The trench has a bottom portion and at least one sidewall on the semiconductor substrate. Then, form a diffusion layer in the silicon substrate for circumscribing the bottom portion of the trench and a predetermined region of its sidewall. After that, form a first polysilicon layer on the bottom portion of the trench and in a manner that a portion of the first polysilicon layer does not contact with the sidewall. Then, form a first dielectric layer to completely cover the first polysilicon layer and the diffusion layer. Then, form an upper electrode layer on top of the trench to at least completely cover the first dielectric layer. Eventually, the contact area between the diffusion layer and the dielectric layer has been largely increased so as to maintain sufficient capacitance.

Abstract: In a method for manufacturing a semiconductor memory device, a plurality of openings are perforated in an insulating layer formed on first impurity diffusion regions for bit lines and second impurity diffusion regions for capacitors of a semiconductor substrate surrounded by a field insulating layer, and each of the openings corresponds to one of the first impurity diffusion regions and at least two of the second impurity diffusion regions.

Abstract: A method to remove the silicon nitride capacitor dielectric layer from over the poly-1 layer on portions of the wafer including non-capacitor areas such as the pad contact area, process control monitor (PCM) testsite areas and scribe line areas. By removing the silicon nitride, H2 can penetrate to the polysilicon and thereby increase the uniformity of the VT. In a first embodiment of the invention, the silicon nitride capacitor dielectric layer is etched away from over the poly-1 layer in the pad area. The removal of the SiN layer allows H2 to penetrate into the poly-1 layer and improve the threshold voltage (VT). Uniformity of long channel VT-N was improved when we modify the pad struture of PCM to increase the clear out ratio of capacitor Si3N4 to 1.0584%. In a second embodiment of the invention, the silicon nitride capacitor dielectric is etched away from over the poly-1 layer in the process control monitor (PCM) testsite area between the chips.

Abstract: A semiconductor wafer comprises a substrate, a first conductive layer and a dielectric layer covering the first conductive layer. A thin-film layer is formed over the dielectric layer. The thin-film layer comprises a hole that penetrates down to the surface of the dielectric layer and the hole is located above the first conductive layer. A first barrier layer is formed on the surface of the semiconductor wafer to cover the thin-film layer. Next, a spacer is formed on the internal walls of the hole. Thereafter, a first dry etching process is performed to form a contact hole. A second barrier layer is then formed on the internal walls of the contact hole. A second conductive layer is formed on the surface of the semiconductor wafer that fills the contact hole. A lithographic process is performed to define a pattern and a location of the storage node in a photo resist layer above the contact hole.

Abstract: A method is provided for making capacitors for future high density circuits. The method increases capacitance while reducing the difficulty in etching the high aspect ratio holes for the capacitor node contacts. After FETs are formed in device areas, a first insulator is deposited and first contact openings are etched for the capacitor node contact. First polysilicon (polySi) plugs are formed in the first contact openings. An etch-stop layer and a second insulating layer are deposited. Second contact openings are aligned over and etched in the second insulating layer to the first polySi plugs. Second polySi plugs are formed in the second contact openings. Openings for capacitors, aligned over and wider than the second polySi plug, are etched in the second insulating layer. The capacitors are completed by forming bottom electrodes with a thin dielectric layer in the capacitor openings and forming a top electrode.

Abstract: A process for making self-aligned split-gate non-volatile memory cell is disclosed. It includes the step of using a nitride photomask in conjunction with a photoresist to etch the nitride layer and cause it to become a stepped nitride layer having a high thickness region and a low thickness. Then a poly-1 photomask is used in conjunction with a photoresist to etch through a first portion of the low thickness region to expose an underlying poly-1 layer intended to be floating gate, wherein at the same time, a portion of the high thickness region adjacent to the first portion of the low thickness region is also etched to a reduced thickness. After poly-1 oxidation, a cell drain photomask is used in conjunction with a photoresist to etch through a second portion of the low thickness region using a nitride etch and an underlying poly-1 layer using a poly etch.

Abstract: A manufacturing method having the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining salicided HV gate regions of high voltage transistors; and forming HV source and drain regions not directly overlaid by silicide portions.

Abstract: In a method of manufacturing a semiconductor device comprising a field-effect transistor and a non-volatile memory element at a surface of a semiconductor body, a first and a second active region of a first conductivity type are defined at the surface of the semiconductor body for the transistor and the memory element, respectively. The surface of the semiconductor body is subsequently coated with a first insulating layer providing a sacrificial gate dielectric of the transistor and a floating gate dielectric of the memory element, which first insulating layer is then covered by a silicon-containing layer providing a sacrificial gate of the transistor and a floating gate of the memory element. After formation of the sacrificial gate and the floating gate, the transistor and the memory element are provided with source and drain zones of a second conductivity type.

Abstract: In the manufacture of a semiconductor power device such as a trench-gate power MOSFET, a source region (13) is formed using a sidewall extension (30) of an upstanding insulated-gate structure (11,21,22). The sidewall extension (30) forms a step with an adjacent surface area (10a′) of a body region (15) of a first conductivity type and comprises doped semiconductor material (13a) of opposite, second conductivity type which is separated from the gate (11) by insulating material (22). The body region (15) provides a channel-accommodating portion (15a) adjacent to the gate structure (11,21,22) and also comprises a localised high-doped portion (15b) which extends to a greater depth in the semiconductor body (10) than the shallow p-n junction between the source region (13) and the channel-accommodating portion (15a), and preferably deeper even than the bottom of the trench (20) of a trench-gate device.

Abstract: The present invention proposes a method for fabricating high-density and high-speed NAND-type mask read-only memories. This method constructs the doped sources and drains by dopant diffusion into the silicon substrate to form ultra-shallow junction, and therefore minimizes the punch-through issue. First, a stacked thin oxide, doped silicon and silicon nitride layer is deposited on the semiconductor substrate and then bit line regions is defined. Gate oxide film is formed between the bit line regions and the dopants in the silicon layer are driven into the substrate to form shallow junctions for source and drain regions. A doped polysilicon layer is deposited on the substrate and a chemical mechanical polishing process is carried out with the silicon nitride as the stopping layer. A coding implantation is performed and a conductive layer is defined on the polysilicon layer to be the word lines.

Abstract: Improved methods for forming integrated circuit devices with alignment structures such as a read-only memory (ROM) array in preparation for code programming with a mask is disclosed. In one embodiment, a gate oxide layer is deposited over a substrate and a gate stack layer is formed over the gate oxide layer. The gate stack layer includes a conductive layer and a sacrificial gate layer formed above the conductive layer with a thin layer of etch stop material in between. The gate stack layer is patterned and etched to form a plurality of wordlines having openings therebetween. An ion barrier layer is deposited over the patterned gate stacks, filling the openings. The ion barrier layer is then etched back to form alignment structures in the openings. A code programming mask, is deposited over the resulting structure and patterned to expose portions of the sacrificial gates. The exposed portions of the plurality of sacrificial gates are removed, followed by ion implantation in the designated channel regions.

Abstract: In a CMOS circuit, impurity regions are formed in the channel forming region of each of an n-channel and p-channel transistors along the channel direction. The intervals between the impurity regions in the n-channel transistor is set narrower than those between the impurity regions in the p-channel transistor so as to make the absolute values of the threshold voltages of the n-channel and p-channel transistors approximately equal to each other. Where active layers are formed by utilizing a crystal structural body that is a collection of needle-like or columnar crystals, the same effect can be attained by controlling the width of the needle-like or columnar crystals.

Abstract: A method of manufacturing semiconductor components includes etching two trenches (105, 106, 805, 806, 1205, 1206) into a surface of a substrate (101, 801, 1201), lining the two trenches (105, 106, 805, 806, 1205, 1206) with an electrically insulative layer (107, 807, 1207) that is never completely removed from a first one of the two trenches (105, 106, 805, 806, 1205, 1206), and simultaneously filling the two trenches (105, 106, 805, 806, 1205, 1206) with a material wherein the material is never completely removed from the first one of the two trenches (105, 106, 805, 806, 1205, 1206) and wherein the second one of the two trenches (105, 106, 805, 806, 1205, 1206) becomes electrically coupled to the substrate (101, 801, 1201).

Abstract: A method of forming a shallow trench isolation (STI) structure. A dielectric layer is formed over the interior surface of a shallow trench. Spacers are formed on the sidewalls of the shallow trench such that a portion of the dielectric layer at the bottom of the shallow trench is exposed. When a silicon oxide layer is subsequently deposited into the shallow trench using ozone and tetra-ethyl-ortho-silicate as reactive gases in a chemical vapor deposition, the silicon oxide layer is deposited faster from the dielectric layer than from the spacers.

Abstract: A process for manufacturing a MOS transistor and especially a MOS transistor used for non-volatile memory cells is presented. At the start of the manufacturing, a semiconductor substrate having a first type of conductivity is covered by a gate oxide layer. A gate electrode is formed over the gate oxide layer, which is a stacked gate when the MOS transistor is used in a non-volatile memory. Covering the gate electrode is a covering oxide that is formed over the gate oxide layer, the gate electrode, and around the gate electrode. Next, a dopant of a second type of conductivity is implanted to provide implant regions adjacent to the gate electrode. Subjecting the semiconductor to thermal treatments allows the implanted regions to diffuse into the semiconductor substrate under the gate electrode and form a gradual junction drain and source region of the MOS transistor.

Abstract: A method for increasing gate surface area for depositing silicide material. A silicon substrate having device isolation structures therein is provided. A stack of sacrificial layers comprising a first sacrificial layer at the bottom, a second sacrificial layer in the middle and a third sacrificial layer on top is formed over the silicon substrate. A gate opening that exposes a portion of the substrate is formed in the stack of sacrificial layers. A portion of the second sacrificial layer exposed by the gate opening is next removed to form a side opening on each side of the gate opening. The gate opening together with the horizontal side opening form a cross-shaped hollow space. A gate oxide layer is formed at the bottom of the gate opening. Polysilicon material is deposited to fill the gate opening and the side openings, thereby forming a cross-shaped gate polysilicon layer. The third, the second and the first sacrificial layers are removed. A metal silicide layer is formed over the gate polysilicon layer.

Abstract: A process for forming a silicon-germanium base of a heterojunction bipolar transistor. First, a silicon substrate having a mesa surrounded by a trench is formed. Next, a silicon-germanium layer is deposited on the substrate and the portion of the silicon-geranium layer adjacent the mesa is removed to form the silicon-germanium base. In a second embodiment, the process comprises the steps of forming a silicon substrate having a mesa surrounded by a trench, forming a dielectric layer in the trench adjacent the mesa, and growing a silicon-germanium layer on the mesa top surface using selective epitaxial growth to form the silicon-germanium base.

Abstract: The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or made amorphous and at least partially doped (139) by means of ion implantation from an upper silicon surface comprised in a semiconductor structure (144) down to a depth lower than the depth of the surrounding field oxide (120), and that the semiconductor structure (144) is then heat treated.

Abstract: A vertical plate capacitor is formed in interlayer dielectric material which separates conductors of upper and lower interconnect layers by a method which avoids the accumulation of residual materials from chemical mechanical polishing (CMP). The method comprises the steps of forming a capacitor via into the interlayer dielectric material, forming a first conductive layer having a U-shaped portion into the capacitor via, forming U-shaped capacitor dielectric material in the U-shaped portion of the first conductive layer, forming a second conductive layer having a U-shaped portion in the U-shaped capacitor dielectric material, filling an interior of the U-shaped portion of the second conductive layer with a plug material, and polishing after the capacitor via is entirely occupied by these elements.

Abstract: There is described the manufacture of a semiconductor device having a storage node or high-yield manufacture of a compact memory IC.

Abstract: A dielectric layer is deposited over an etching stop layer. Then, a photoresist pattern is patterned on the dielectric layer. An anisotropical etching is performed to etch the dielectric layer by using the photoresist pattern as an etching mask to generate a slot in the dielectric layer. An isotropical etching is subsequently performed using the photoresist pattern as an etching mask. A further anisotropical etching is used to create contact holes to the substrate. Then, the photoresist pattern is stripped. A conductive layer is deposited along the surface of the etched dielectric layer and on the side walls of the contact holes. A filling material is refilled into the cup-shape cavities. The upper portion of the conductive layer is left exposed by the filling material. A selective etching step is performed to remove the upper portions of the conductive layer by using the filling material as a mask. The filling material and the etched dielectric layer are removed.

Abstract: Microstructures, including a plurality of spaced structural members which are bendable under an external force, undergo a treating method using a first treating liquid, to prevent permanent deformation, by removing the microstructure from the first treating liquid to an environment having a pressure less than atmospheric pressure; or moving the microstructure from the first treating liquid to a second treating liquid having a smaller surface tension than the first treating liquid, and then removing the microstructure from the second liquid; or drying the microstructure removed from the first treating liquid by exposing same to a liquid vapor having a smaller surface tension than the first treating liquid; or removing the microstructure from the first treating liquid to the atmosphere, and drying the microstructure using an energy beam of high intensity or an ultrasonic wave.

Abstract: A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is created in the high voltage device region. A layer of sacrificial oxide is deposited on the surface of the semiconductor substrate. A low voltage cluster n-well implant is performed in the high voltage PMOS region of the semiconductor substrate followed, for the high voltage NMOS region, by a low voltage cluster p-well implant which is followed by a buried p-well cluster implant.

Abstract: A novel two-dimensional scaling method is used to determine overlay errors on a pilot wafer for more accurate alignment when a photoresist is exposed in a step-and-repeat tool on product wafers. The method is useful for accurately aligning interconnections over contact holes in field (circuit) areas. A first photoresist layer is deposited on a pilot wafer having a planar insulating layer, and exposed through a first reticle that is stepped across the wafer to form contact holes in the array of field areas and first registration patterns adjacent to the field areas. Contact holes are etched and filled with metal. A conducting layer is deposited. A second photoresist layer is deposited and exposed through a second reticle to form an etch mask for interconnections and second registration patterns. During exposure, the interfield expansion parameter in the algorithm for the step-and-repeat tool is used to gradually shift the image from wafer center to wafer edge in both x and y directions.

Abstract: Methods of forming trench isolation regions include the steps of forming a trench masking layer comprising a first material (e.g., polysilicon) on a semiconductor substrate and then etching a trench in the semiconductor substrate, using the trench masking layer as etching mask. A trench nitride layer comprising a second material different from the first material is then formed on a sidewall of the trench and on a sidewall of the trench masking layer. The trench is then filled with a trench insulating material (e.g., USG). The trench masking layer is then removed by selectively etching the trench masking layer with an etchant that selectively etches the first material at a higher rate than the second material. This step of removing the trench masking layer results in exposure of a protruding portion of the trench nitride layer but does not cause the trench nitride layer to become recessed. The trench insulating material and the trench nitride layer are then etched back to define the trench isolation region.

Abstract: A method of forming a semiconductor device minimizes oxide recessing in a trench of a semiconductor device. In one embodiment, forming a nitride spacer surrounding the top trench corner oxide in a shallow trench isolation region protects the corner oxide from being etched during processing. Oxide recessing in the trench is undesirable since it results in high electric fields around the sharp top corners of the trenches and Vt roll-off of the transistors. According to one example embodiment, STI regions filled with an HDP oxide and having undergone planarization, are masked. The masking substantially covers the HDP oxide and overlaps at least portions of nitride regions. Unmasked areas of the nitride regions are etched away forming nitride spacers on both sides of the HDP oxide fill.

Abstract: A method of manufacturing shallow trench isolation structure comprising the steps of forming a polysilicon mask layer over a substrate, and then patterning the polysilicon mask layer and the substrate to form a trench. Thereafter, a silicon nitride layer is formed covering the sidewalls of the trench. Next, a high-density chemical vapor deposition method is used to deposit oxide material into the trench. Finally, the surface is polished to remove a portion of the oxide layer and the silicon nitride layer until the polysilicon mask layer is exposed. The shallow trench isolation structure can avoid subthreshold kink effect and reduce subthreshold leakage current.

Abstract: An isolation structure which protrudes above the semiconductor surface and sidewall spacers which smooth the topography over said isolation structure.

Abstract: A method of manufacturing a shallow trench isolation in a substrate. The substrate has a pad oxide layer and a mask layer formed thereon in sequence and a trench penetrating through the mask layer and the pad oxide layer and into the substrate. A thermal oxidation process is performed to form a liner oxide layer on a portion of the substrate exposed by the trench. A spacer is formed on the sidewall of the mask layer, the pad oxide layer and the trench. An oxidation process is performed to oxidize a portion of the substrate under a portion of the liner oxide layer located on the bottom of the trench. An insulating layer is formed over the substrate and filling the trench. A planarization process is performed to remove a portion of the insulating layer until the mask layer is exposed. The mask layer and the pad oxide layer are removed.

Abstract: A method for forming buried oxide regions below a single crystal semiconductor layer incorporating the steps of forming epitaxial layers having different rates of oxidation with the lower layer having a faster rate of oxidation and oxidizing the layers through an opening in a mask. A plurality of oxide isolated FET's may be formed. The invention reduces the problem of source/drain parasitic capacitance and short channel effects while isolating FET's and eliminating floating body effects of an FET by selectively oxidizing semiconductor layers.

Abstract: A method of forming an isolated structure of sufficient size to permit the fabrication of an active device thereon is comprised of the steps of depositing a gate oxide layer on a substrate. Material, such as a polysilicon layer and a nitride layer, is deposited on the gate oxide layer to protect the gate oxide layer. An active area is defined, typically by patterning a layer of photoresist. The protective material, the layer of oxide, and finally the substrate are etched to form a trench around the active area. Spacers are formed on the sides of the active area. The substrate is etched to deepen the trench around the active area to a point below the spacers. The substrate is oxidized at the bottom of the trench and horizontally under the active area to at least partially isolate the active area from the substrate. Oxide spacers are formed on the sides of the active area to fill exposed curved oxide regions and the remainder of the trench may be filled with an oxide.

Abstract: A low dielectric constant (k) material, such as methylsilsesquioxane (MSQ), used as an interlevel dielectric is expected to reduce the parasitic capacitance in integrated circuit. However, MSQ film can be easily degraded during resist ashing after the film is etched with the damascene trenches being created. The present invention discloses an innovative sidewall capping technology to solve the degradation issue. Prior to resist ashing, a high-quality, low-k oxide film is selectively deposited onto the sidewalls of MSQ trenches using selective liquid-phase deposition. Experimental results demonstrate that the capping oxide can effectively protect the sidewalls of MSQ trenches from ashing-induced degradation.

Abstract: The invention provides a number of semiconductor substrate manufacturing methods with which, in manufacturing a semiconductor substrate having a semiconductor layer in an insulated state on a supporting substrate, it is possible to obtain a thick semiconductor layer with a simple process and cheaply while reducing impurity contamination of the semiconductor layer to a minimum.

Abstract: The present invention employs a scanned atomic force probe to physical incorporate impurity atoms (dopant or bandgap) into a semiconductor substrate so that the impurity atoms have high resolution and improved placement. Specifically, the method of the present invention comprising a step of physically contacting a semiconductor surface having a layer of a dopant/bandgap source material thereon such that upon said physical contact impurity atoms from the dopant/bandgap source material are driven into the semiconductor substrate.

Abstract: An open apparatus is described for the processing of planar thin semiconductor substrates, particularly for the processing of solar cells. The apparatus includes a first zone for the drying and burn-out of organic components from solid or liquid based dopant sources pre-applied to the substrates. The zone is isolated from the remaining zones of the apparatus by an isolating section to prevent cross-contamination between burn-out zone and the remaining processing zones. All the zones of the apparatus may be formed from a quartz tube around which heaters are placed for raising the temperature inside the quartz tube. Each zone may be purged with a suitable mixture of gases, e.g. inert gases such as argon, as well as oxygen and nitrogen. The zones may also be provided with gaseous dopants such as POCl3 and the present invention includes the sequential diffusion of more than one dopant into the substrates. Some of the zones may be used for driving-in the dopants alternatively, for other processes, e.g. oxidation.

Abstract: In a method for fabricating a highly activated shallow abrupt doped junction in a semiconductor substrate, a first dopant is implanted into a predetermined surface of the semiconductor substrate to form a preamorphization junction having a first predetermined depth from the predetermined surface of the semiconductor substrate. Furthermore, a second dopant is implanted into the preamorphization junction with a dopant profile along a depth of the semiconductor substrate from the predetermined surface of the semiconductor substrate. A peak of the dopant profile is located at a fraction of the first predetermined depth of the preamorphization junction. A silicidation RTA (Rapid Thermal Anneal) is performed to form silicide on the semiconductor substrate. The silicidation RTA (Rapid Thermal Anneal) recrystallizes the preamorphization junction from the first predetermined depth of the preamorphization junction up to an unrecrystallized depth of the preamorphization junction.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: An improvement in the deposition of materials in a multiple chamber semiconductor processing cluster tool comprising a first cluster of first chambers, a second cluster of second chambers and a transition chamber located between the first cluster and the second cluster, where the transition chamber is adapted to deposit a material upon a wafer. Specifically, the transition chamber provides a flash coating of PVD copper on the wafer which significantly improves the adhesion of subsequently CVD deposited bulk copper without sacrifice in the throughput of the cluster tool.

Abstract: A semiconductor device and a wiring therefor and a fabrication method thereof are disclosed, which are capable of providing a good current driving capability without degrading the characteristic of the semiconductor device by overcoming the problems encountered in the known semiconductor device, and a wiring is implemented by using e semiconductor device fabricated in accordance with the present invention.

Abstract: A gate stack (104) including a gate dielectric with reduced effective electrical thickness. A high-k dielectric (108) is formed over the silicon substrate (102). Remote plasma nitridation of the high-k dielectric is performed to create a nitride layer (107) over the high-k dielectric (107). A conductive layer (110) is formed over the nitride layer (107) forming the gate electrode.

Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;M. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.

Abstract: A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a position of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.

Abstract: A new method of forming silicon nitride sidewall spacers has been achieved. This method is used to fabricate tapered, L-shaped spacer profiles using a two-step etching process that can be performed insitu. In accordance with the objects of this invention, a new method of forming silicon nitride sidewall spacers has been achieved. An isolation region is provided overlying a semiconductor substrate. Conductive traces are provided overlying the insulator layer. A liner oxide layer is deposited overlying the conductive traces and the insulator layer. A silicon nitride layer is deposited overlying the liner oxide layer. The silicon nitride layer is anisotropically etched down to reduce the vertical thickness of the silicon nitride layer while not exposing the underlying liner oxide layer. The silicon nitride layer is etched through to form silicon nitride sidewall spacers adjacent to the conductive traces.

Abstract: A system and method for forming solder bumps on a surface of a semiconductor device, such as a spherical-shaped semiconductor integrated circuit, is disclosed. Multiple devices are first aligned so that a vacuum chuck can hold all of the devices with an appropriate orientation. The vacuum chuck can then dip the devices into different molten metal compounds to form a plurality of solder bumps. Metal solder materials of different melting points are chosen so that the thickness of the solder bumps are partially controlled by the number of layers of solder metal sequentially grow on the metal pads. Once the solder bumps are grown on the devices, the vacuum chuck can immediately transfer the devices to a tape and reel assembly for further transportation thereof. It can also be easily fed into a tube assembly which protects the spherical shaped semiconductor device with the solder bumps during the shipping process.

Abstract: An adhesion pad for adhering a semiconductor chip or a ball grid array module to a supporting substrate includes a stepped or tapered structure. The structure is composed of at least one solder wettable metal or alloy layer having solder deposited thereon. The stepped or tapered structure prevents a fatigue crack from propagating in the X-Y plane above the adhesion pad.

Abstract: A method of making a ball grid assembly and the assembly wherein a mask (1) is provided which is not wettable by solder and through which a pattern of parallel holes (3) is provided extending to at least one of a pair of opposing surfaces. A magnet (5), preferably an electromagnet, is disposed at the other one of the opposing surfaces. Solderable magnetic pins (7) are caused to enter the holes by magnetic attraction by positioning the one surface of the mask over the pins with a portion of each of the pins extending out of the hole into which it has entered. A layer of solder (11) is formed on the portion of each of the pins extending out of a hole in the mask and this layer of solder is reflowed over the pins and over a grid of solder adherable elements (13) on the package (15) and then allowed to set. The mask is removed from the pins when the solder is again set.

Abstract: A method of arranging staggered bond pads layers for effectively reducing the size of a die. The sizes of different bond pad layers are reduced gradually from the upper layer to the lower layer, while the sizes of traces in different layers are increased from the upper layer to the lower layers. The size of the first layer is specified and determined by the specification of a wire bonder. The reduction of different bond pad layers may be linear or nonlinear.

Abstract: A method of manufacturing a contact pad. A substrate having a source/drain region formed therein is provided. A dielectric layer is formed over the substrate. An opening is formed in the dielectric layer and exposes the source/drain region. A selective epitaxial process is performed to form a contact pad in the opening, wherein a top of the contact pad extends onto a surface of the dielectric layer.