Abstract: The present invention relates to an in vitro cell culture device which includes a vessel comprising an inner surface, a layer of cartilage disposed on at least a portion of said inner surface, the layer of cartilage including a plurality of chondrocytes in an extracellular matrix, and a growth medium in the vessel, the layer of cartilage being bathed in the growth medium. Also disclosed is a composite cell culture prepared from the in vitro cell culture device, the composite cell culture includes a first layer including chondrocytes in an extracellular matrix, a second layer disposed on the first layer and including type I collagen, and a third layer disposed on the second layer and including cells at least partially covering the second layer.

Abstract: Chemically modified oligonucleotides (ODNS) are complementary, either in the sense of the classic “four letter code” recognition motif, or in the sense required for triple strand formation based on the more limited “two letter code recognition motif”, to a target sequence of double stranded DNA of an invading cell, organism or pathogen, such as a virus, fungus, parasite, bacterium, malignant cell, or any duplex DNA which is desired to be broken into segments for the purpose of “mapping”. The ODNs have cross-linking agents covalently attached at least to two different sites of the ODN. Alternatively, the cross-linking agent which is attached to one site on the ODN has two cross-linking functionalities, and therefore in effect comprises two cross-linking agents.

Abstract: This invention relates to an isolated nucleic acid fragment encoding a geranylgeranyl transferase subunit. The invention also relates to the construction of a chimeric gene encoding all or a portion of the geranylgeranyl transferase subunit, in sense or antisense orientation, wherein expression of the chimeric gene results in production of altered levels of the geranylgeranyl transferase subunit in a transformed host cell.

Abstract: The present invention features gram-positive bacteria resistant to 5-fluorodeoxyuridine (FUdR). Such bacteria will preferably be commensal, and will not be resistant to antibiotics. Bacteria according to the present invention may also be transformed with DNA encoding an antigenic protein. Such transformed bacteria may be used to formulate a vaccine, in order to stimulate an immune response to the antigenic protein in a patient. The present invention further provides a method for isolating gram-positive bacteria resistant to FUdR.

Abstract: A composition comprising a nuclear localization sequence and a peptide nucleic acid oligomer (NLS-PNA) is described. Uses of the composition include, but are not limited to: regulation of gene expression, gene therapy, and the production of pharmaceutical nucleic acids and proteins. In addition, the NLS-PNA is useful for scientific and therapeutic transfection and expression of nucleic acids in cells types that previously were resistant to transfection and therapy including quiescent cells, differentiated cells, embryonic stem cells, and eukaryotic cells with intact nuclear membranes. The NLS-PNA can be combined with a membrane transport sequence (MTS) forming a novel compound referred to as an MTS-NLS-PNA wherein the MTS provides transport through the cytoplasmic membrane of a cell.

Abstract: Genetic modification of pluripotent hemopoietic stem cells of primates (P-PHSC) by transduction of P-PHSC with a recombinant adeno-associated virus (AAV). Tile genomc of the recombinant AAV comprises a DNA sequence flanked by the inverted terminal repeats (ITR) of AAV. The DNA sequence will normally comprise regulatory sequences which are functional in hemopoictic cells and, controlled by these regulatory sequences, a sequence coding for a protein or RNA with a therapeutic property when introduced into hemopoietic cells. Preferred examples of DNA sequences are the human lysosomal glococerebrosidase gene, a globin gene from the human &bgr;-globin gene cluster, a DNA sequence encoding an RNA or protein with anti-viral activity, the &agr;1-antitrypsin gene and the human multidrug resistance gene I (MDRI). The invention provides for effective gene therapy with PHSC of primates, in particular humans.

Abstract: The present invention relates to a method of marking liquids using at least two markers, wherein said markers absorb in the 600-1200 nm region of the spectrum and reemit fluorescent light and the absorption range of at least one marker overlaps with the absorption range of at least one other marker. The present invention further relates to a method for detecting markers in liquids marked by the method of the invention, which comprises using light sources which emit radiation in the absorption ranges of said markers and detecting the fluorescent light reemitted by said markers, at least one of said light sources emitting radiation in the overlapping absorption range of at least one marker with that of at least one other marker and the number of light sources being less than or equal to the number of markers. The present invention further relates to liquids marked by the method of the invention.

Abstract: A method for measuring chemical analytes and physical forces by measuring changes in the deflection of a microelectromechanical cantilever structure while it is being irradiated by a light having an energy above the band gap of the structure.

Abstract: The invention provides methods for preparing a reaction substrate for use as assay devices comprising parallel printing of arrays of biosites on reaction substrates, wherein each biosite comprises a single type of capture probe bound to the reaction substrate and the array of biosites is deposited on the reaction substrate by a capillary bundle printer device.

Abstract: A biosensor comprises a waveguide into which light is coupled by a diffraction grating. The sample to be analyzed is placed on a reaction region in which a component of the immunological reaction is provided, for example antibodies or antigens. Fluorescence is excited on the surface of the waveguide because of the presence of a marker for example, a labelled antigen or antibody. Fluorescence is decoupled from the waveguide by the coupling diffraction grating or another diffraction grating. The waveguide is made of a material emitting light when it is excited by the marker excitation beam. This latter emission has a peak wavelength different from that of the emission radiation due to the marker used in the immunological reaction. Waveguide material fluorescence emission provides a reference during measurement.

Abstract: A method for COB mounting of electronic chips on a circuit board includes contact connection of connecting wires and substantially whole-area adhesive bonding of a housing. A chip is partially adhesively bonded on a circuit board in such a way that the chip can be contact-connected and can be removed again without damage to the circuit board. Electronic tests or a burn-in process is performed on the chip. The chip, with a given functionality in a manner that is required for application of the circuit board, is fully adhesively bonding.

Abstract: A method provides estimations of physical interconnect process parameter values in a process for manufacturing integrated circuits. The method includes fabricating test structures each providing a value of a measurable quantity corresponding to a value within a range of values of the physical interconnect process parameters. In some embodiments, the measured value is used to derive the values of the physical interconnect process parameters, either by a numerical method using a field solver, or by a closed-form solution. The values of physical interconnect process parameters involving physical dimensions are also obtained by measuring photomicrographs obtained using a scanning electron microscope from cross sections of test structures. In some embodiments, a family of test structures corresponding to a range of conductor widths and a range of spacings between conductors are measured.

Abstract: A method of testing an integrated circuit having a layout structure which includes a plurality of branch structures, the method comprising the steps of: (A) generating a control current in response to an input reference; (B) establishing a respective branch current through each of the plurality of branch structures when a process bias supports fabrication of a respective predetermined dimension associated with the branch structures; and (C) generating, in response to the branch currents, an output indicative of the process bias obtained during fabrication of the layout structure.

Abstract: An improved method for sharpening emitter sites for cold cathode field emission displays (FEDS) includes the steps of: forming a projection on a baseplate; growing an oxide layer on the projection using a low temperature oxidation process; and then stripping the oxide layer. Preferred low temperature oxidation processes include: wet bath anodic oxidation, plasma assisted oxidation and high pressure oxidation. These low temperature oxidation processes grow an oxide film using a consumptive process in which oxygen reacts with a material of the projection. This permits emitter sites to be fabricated with less distortion and grain boundary formation than emitter sites formed with thermal oxidation. As an example, emitter sites can be formed of amorphous silicon. In addition, low temperature materials such as glass can be used in fabricating baseplates without the introduction of high temperature softening and stress.

Abstract: The present invention comprises forming a first conductive layer over the substrate to have a gap. A dielectric layer is then formed on the first conductive layer. A portion of the dielectric layer is removed to leave a residual dielectric layer in the gap. Next, isotropical etching is performed to etch the first conductive layer using the residual dielectric as an etching mask, thereby forming a conductive tip. A polishing stopper composed of oxide is formed over the conductive tip. A nitride layer is formed over the conductive tip and on the polishing stopper. The nitride is polished to the surface of the polishing stopper. A portion of the nitride layer is etched to form a step over the conductive tip. A second conductive layer is formed over the etched nitride layer. A portion of the second conductive layer is removed to expose an upper surface of the step. The nitride layer and the polishing stopper are respectively removed to expose the conductive tip.

Abstract: A semiconductor device such as a light emitting semiconductor device comprising a mask layer having opening areas and a selective growing layer comprising a semiconductor grown selectively by way of the mask layer, with each of the mask layer and the selective growing layer being disposed by two or more layers alternately. The semiconductor device is manufactured by a step of laminating on a substrate a mask layer having opening areas and a selective growing layer comprising a semiconductor grown selectively way of a mask layer, each by two or more layers alternately and a subsequent step of laminating semiconductor layers thereon. Threading dislocations in the underlying layer are interrupted by the first mask layer and the second mask layer and do not propagate to the semiconductor layer. The density of the threading dislocations is lowered over the entire surface and the layer thickness can be reduced.

Abstract: A method for fabricating a monolithically integrated liquid crystal array display and control circuitry on a silicon-on-sapphire structure comprises the steps of: a) forming an epitaxial silicon layer on a sapphire substrate to create a silicon-on-sapphire structure; b) ion implanting the epitaxial silicon layer; c) annealing the silicon-on sapphire structure; d) oxidizing the epitaxial silicon layer to form a silicon dioxide layer from portion of the epitaxial silicon layer so that a thinned epitaxial silicon layer remains; e) removing the silicon dioxide layer to expose the thinned epitaxial silicon layer; f) fabricating an array of pixels from the thinned epitaxial silicon layer; and g) fabricating integrated circuitry from the thinned epitaxial silicon layer which is operably coupled to modulate the pixels. The thinned epitaxial silicon supports the fabrication of device quality circuitry which is used to control the operation of the pixels.

Abstract: A solid-state imaging sensor, a method for manufacturing the solid-state imaging sensor and an imaging device of which said solid state image sensor is designed to reduce unwanted light reflections, improve light focusing of light reflections from the substrate and oblique light constituents onto the sensor in order to allow further reduction in pixel size. Transfer electrodes in a line shape are arrayed at spaced intervals on a substrate, discrete sensors for photo-electric conversion are formed between the transfer electrode lines, a light-impervious film consisting of a first and second light-impervious films with an aperture positioned directly above a sensor is formed on the substrate and covers the transfer electrode to block any incident light other than the beam of light R from entering the sensor, and an on-chip lens for focusing the light R onto a sensor is formed above the light-impervious film.

Abstract: In a CCD type solid state image pickup device including a semiconductor substrate having photo/electro conversion portions and a first insulating layer formed on the semiconductor substrate, a plurality of charge transfer electrodes are formed on the first insulating layer and are a double structure formed by a first conductive layer and a second conductive layer having a lower resistance value than the first conductive layer. A second insulating layer is interposed between two adjacent ones of the charge transfer electrodes.

Abstract: A process for forming a relatively high quality, lower cost organic semiconductor film is provided. A substrate is formed by depositing an organic semiconductor film via a lower cost method such as printing or spin coating on a support substrate. A portion of a solvent is vaporized to bring the vapor into contact with the film. The chemical potential of the vapor molecules is controlled to provide an interaction with the organic semiconductor film to alter the molecular arrangement of the film. The process further entails placing the substrate on a first temperature controlled stage and placing the solvent on a second temperature controlled stage. The chemical potential of the vapor is adjusted by controlling the temperature of the solvent. Appropriate annealing conditions are obtained by adjusting the temperature of the solvent, the substrate, and the anneal time. The process can assist manufacturing of lower cost displays that utilize arrays of organic thin-film transistors.

Abstract: A method of packaging an integrated circuit chip wherein the chip is encapsulated prior to mechanical bonding to a packaging substrate.

Abstract: A semiconductor device assembly according to the present invention may comprise a semiconductor die having at least one contact pad thereon and a package substrate having at least one lead pad thereon. The package substrate is sized to receive the semiconductor die so that the contact pad on the semiconductor die is substantially aligned with the lead pad on the package substrate when the semiconductor die is positioned on the package substrate. A coil spring is positioned between the contact pad on the semiconductor die and the lead pad on the package substrate so that the axis of the coil spring is substantially parallel to the contact pad contained on the semiconductor die and the lead pad contained on the package substrate.

Abstract: A method for simultaneous bumping/bonding an IC chip to a semiconductor substrate and a semiconductor package fabricated by the method are described. In the method, a plurality of edge-type conductive pads formed of under-bump-metallurgy layers are first fabricated on an IC chip by dicing through conductive pads formed on a silicon wafer. The edge-type conductive pads, or UBM layer, are then positioned in close proximity to conductive elements formed on a top surface of a semiconductor substrate. A volume of solder is then applied to the interface between the conductive pads and the conductive elements to form electrical bonds between the two. A suitable method for applying the volume of solder may be a solder jetting technique, a solder printing technique or a method utilizing pre-applied solder paste on the surfaces to be bonded together.

Abstract: A semiconductor package having an encapsulation that encapsulates an integrated circuit chip and an external lead frame for the chip. Multiple connection leads project from the periphery of the encapsulation. At least one external face of the encapsulation is covered with a layer of electrically conductive material, and the conducting material layer has at least one lateral extension that electrically contacts at least one of the projecting connection leads. A method of manufacturing such a semiconductor package is also provided.

Abstract: A method of manufacturing a leadless semiconductor chip package comprises the steps of: attaching a semiconductor die onto a die pad of a lead frame, wherein the lead frame comprises a plurality of leads arranged about the periphery of the die pad and each lead has a notch formed at the to-be-punched position thereof; wire bonding the inner ends of the leads to bonding pads on the semiconductor die; sucking a film against a lower part of a molding die; closing and clamping the molding die in a manner that the semiconductor die is positioned in a cavity of the molding die and the lead frame is disposed against the film; transferring a hardenable molding compound into the cavity; hardening the molding compound; opening the molding die to take out the molded product; and punching the molded product along the notches of the leads thereby making the singulation process more convenient and correct.

Abstract: The present invention is directed to a method of attaching a leadframe to a singulated good die using a wet film adhesive applied in a predetermined pattern on the active surface of the good die, the lead finger of a leadframe, or both. By applying the adhesive only to identified good dice, time and material are saved over a process that applies adhesive to the entire wafer. By attaching the leadframe to the good die with a wet film, it is possible to remove the leadframe from the good die for rework if the good die subsequently tests unacceptable.

Abstract: In accordance with the invention, a semiconductor die having an input/output contact surface is interconnected with a substrate. A metal plate having a surface cavity is provided for receiving the die. The plate has peripheral surface regions surrounding the cavity. The die is mounted in the cavity with its contact surface co-planar with the peripheral regions, and a sealable contact region forming closed figure around the die is provided on the peripheral surface regions of the plate. A substrate surface is provided with a corresponding contact regions for receiving the die and the plate. The plate/die structure is mounted and solder bonded on the substrate. The resulting structure has reduced thermal impedance from the die/board surface through the plate and a continuous peripheral hermetic seal around the die.

Abstract: The present invention relates to a method of crystallizing an amorphous silicon layer which is carried out by depositing a crystallization-inducing substance on an amorphous silicon layer on crystallizing the amorphous silicon layer by metal-induced crystallization whereby speed of crystallizing silicon is increased and metal contamination by MIC is reduced. The present invention includes the steps of depositing a crystallizing-induced layer of an induced substance for crystallizing silicon on an amorphous silicon layer wherein the crystallizing induced layer is formed to the thickness under 0.03 angstroms, and treating thermally the amorphous silicon layer on which the crystallizing-induced layer is deposited.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: A method for producing a semiconductor device includes the steps of: forming an impurity diffusion layer for controlling a threshold voltage by ion implantation; and conducting a high-temperature rapid heat treatment for recovering crystal defects generated by the ion implantation. More specifically, treatment conditions for the high-temperature rapid heat treatment are set in such a manner that interstitial atoms causing the crystal defects are diffused, and impurities in the impurity diffusion layer are not diffused. For example, the high-temperature rapid heat treatment is conducted in a temperature range of about 900° C. to about 1100° C.

Abstract: This invention provides a semiconductor device by which a high-speed DRAM cell and logic circuit can be obtained without increasing the number of fabrication steps, and a method of fabricating the same. A memory cell is constructed of capacitors formed in two end portions of an element formation region of a silicon substrate and a MOS transistor formed between these capacitors. The interval between gate electrodes of MOS transistors in adjacent memory cells is made larger than the intervals between these gate electrodes and gate electrodes formed outside the former gate electrodes. A portion above an n-type diffusion layer connected to a capacitor node is filled with a spacer insulating film, and an n-type diffusion layer connected to a bit line is covered with the spacer insulating film. A titanium silicide film is formed on one of these n-type diffusion layers and the gate electrodes.

Abstract: A method for forming a bit line of a DRAM memory array is disclosed. The method comprises the steps of: forming an interlayer dielectric over the DRAM memory array; etching the interlayer dielectric to form trenches in the interlayer dielectric, the trenches collectively forming a bit line pattern and having tapered side walls; and depositing a conductive material into the trenches to form the bit line.

Abstract: A semiconductor processing method of forming a contact pedestal includes, a) providing a node location to which electrical connection is to be made; b) providing insulating dielectric material over the node location; c) etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base; d) providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; e) anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; f) after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location; g) filling the contact opening to the node location with electrically conductive material; h) rendering the sidewall spacer electrically conductive; and i) etching the electrically conductive material to form an electrically conducti

Abstract: A method of fabricating a bottom electrode is described. A first dielectric layer having a first opening is formed over a substrate. The first opening exposes a portion of a conductive layer in the substrate. A first liner layer is formed on a sidewall of the first opening. A conductive plug is formed in the opening. A plurality of bit lines are formed next to the first opening. A second liner layer is formed over the substrate to cover the bit lines, the first liner layer, and the conductive plug. A node contact opening is formed in the second liner layer to expose a portion of the conductive plug. A second dielectric layer is formed over the substrate. A second opening is formed in the second dielectric layer to expose the node contact opening and a portion of the second liner layer. A conformal conductive layer is formed in the opening.

Abstract: A container capacitor and method having an internal concentric fin. In one embodiment, the finned capacitor is a stacked container capacitor in a dynamic random access memory circuit. The finned container capacitor provides a high storage capacitance without increasing the size of the cell. The capacitor fabrication requires only two depositions, a spacer etch and a wet etch step in addition to conventional container capacitor fabrication steps.

Abstract: A method for forming a hemispherical grain polysilicon layer on an amorphous silicon film increases the surface area of the layer by first forming silicon crystal nuclei on the film, and then enlarging the nuclei before annealing. The nuclei are formed on the amorphous silicon film loading a substrate having the amorphous silicon film into a chamber and injecting a silicon source gas into the chamber at a first, low flow rate which allows the pressure of the chamber to be reduced, thereby increasing the density of the crystal nuclei. A silicon source gas is then injected into the chamber at a second, higher flow rate, thereby enlarging the silicon crystal nuclei on the amorphous layer. The resulting structure is then annealed to form a hemispherical grain polysilicon layer having a large surface area due to the irregular surface of the polysilicon layer.

Abstract: Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material. In another embodiment, a capacitor storage node is formed having an uppermost surface and a side surface joined therewith. A protective cap is formed over the uppe-most surface and a capacitor dielectric layer is formed over the side surface and protective cap. A cell electrode layer is formed over the side surface of the capacitor storage node.

Abstract: A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide. The vertical wall of the protruding structure over the source is used to form vertical floating gate and spacer control gate with an intervening inter-gate oxide. Because the coupling between the source and the floating gate is now provided through the vertical wall, the coupling area is much larger than with conventional flat source. Furthermore, there is no longer the problem of voltage punch-through between the source and the drain. The vertical floating gate is also made thin so that the resulting thin and sharp poly-tip enhances further the erasing and programming speed of the flash memory cell.

Abstract: A nonvolatile semiconductor memory cell array is shown which is composed of a plurality of unit cell-arrays arranged in a repeating pattern. Each of the unit cell-arrays includes a first plurality of cell transistors having control gates coupled in common to a first word line and a second plurality of cell transistors having control gates coupled in common to a second word line. The two word lines are arranged in parallel to one another and perpendicular to a bit line. The bit line is connected in common with drains of both the first and second plurality of cell transistors through a bit line contact. A pair of source lines is arranged along each side of the bit line and parallel to the bit line. Each source line is coupled to one transistor from each of the first and second pluralities of cell transistors through a source line contact.

Abstract: A method (200) of forming a NAND type flash memory device includes the steps of forming an oxide layer (202) over a substrate (102) and forming a first conductive layer (106) over the oxide layer. The first conductive layer (106) is etched to form a gate structure (107) in a select gate transistor region (105) and a floating gate structure (106a, 106b) in a memory cell region (111). A first insulating layer (110) is then formed over the memory cell region (111) and a second conductive layer (112, 118) is formed over the first insulating layer (110). A word line (122) is patterned in the memory cell region (111) to form a control gate region and source and drain regions (130, 132) are formed in the in the substrate (102) in a region adjacent the word line (122) and in a region adjacent the gate structure (107).

Abstract: Thin film transistor and method for fabricating the same, is disclosed, in which a channel width of the thin film transistor is made greater in a narrow area for improving an on/off performance of the thin film transistor, the thin film transistor including a source electrode formed on a substrate, a columnar conductive layer connected to the source electrode, a drain electrode formed on the conductive layer, a gate insulating film formed to cover the conductive layer and the drain electrode, a gate electrode formed on the gate insulating film surrounding the conductive layer, and an insulting film formed between the source electrode and the gate electrode.

Abstract: A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high frequency applications.

Abstract: A method for fabricating a semiconductor device comprises the step of forming an interconnection 18 having the upper surface covered with an insulation film 20 on a base substrate 10, the step of sequentially depositing an insulation film 24 and an insulation film 26 on the base substrate 10 with the interconnection 18 formed on, the step of etching the insulation film 26 with the insulation film 24 as a stopper to form openings in a region containing a region where the interconnection 18 is formed, and the step of etching the insulation film 24 in the opening to form sidewall insulation films 30 of the insulation film 24 on the side walls of the interconnection 18 and form contact holes 34, 36 to be connected to the base substrate 10 in alignment with the interconnection 18.

Abstract: A MOS transistor and a method of fabricating the same for Ultra Large Scale Integration applications includes a composite gate structure. The composite gate structure is comprised of a main gate electrode and two assisted-gate electrodes disposed adjacent to and on opposite sides of the main gate electrode via an oxide layer. Areas underneath the two assisted-gate electrodes form ultra-shallow “pseudo” source/drain extensions. As a result, these extensions have a more shallow depth so as to enhance immunity to short channel effects.

Abstract: There is provided a method for fabricating a semiconductor device comprising a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed within the semiconductor layer, a drain region of the second conductivity type formed within the semiconductor layer, a channel region provided between the source and drain regions, a gate electrode formed over the channel region, and a buried region of the first conductivity type having at least a part included in the drain region. The method for fabricating the semiconductor device comprises the steps of doping the semiconductor layer with a dopant of the second conductivity type for the drain region and doping the semiconductor layer with a dopant of the first conductivity type for the buried region.

Abstract: A method for adjusting Vt while minimizing parasitic capacitance for low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant between vertical structures to provide a graded implant. The implant angle is greater than or equal to arc tangent of S/H where S is the horizontal distance between, and H is the height of, such vertical structures.

Abstract: For fabricating a field effect transistor, a gate structure is formed on a gate dielectric on an active device area of a semiconductor substrate. A liner layer of a non-dielectric material is formed on sidewalls of the gate dielectric, and on a drain extension area and a source extension area of the active device area of the semiconductor substrate. First spacers of dielectric material are formed on the liner layer at sidewalls of the gate structure and over the drain and source extension areas. A contact junction dopant is implanted into exposed regions of the active device area of the semiconductor substrate to form a drain contact junction and a source contact junction. The first spacers of dielectric material are etched using a first type of etching reactant that etches the first spacers but not the liner layer such that the gate dielectric is not exposed to the first type of etching reactant.

Abstract: A method for forming a MOSFET having an LDD structure with minimal lateral dopant diffusion is described. A gate electrode is provided overlying a gate dielectric layer on a semiconductor substrate. Dielectric spacers are formed on sidewalls of the gate electrode. Source and drain regions are formed associated with the gate electrode. The gate electrode and source and drain regions are silicided. Thereafter, the spacers are removed to expose the semiconductor substrate. LDD regions are formed using plasma doping in the exposed semiconductor substrate between the source and drain regions and the gate electrode to complete formation of an LDD structure in the fabrication of an integrated circuit device.

Abstract: A vertically-isolated bipolar transistor occupying reduced surface area is fabricated by circumscribing an expected active device region within a first narrow trench. The first trench is filled with sacrificial material impermeable to diffusion of conductivity-altering dopant, and then isolation dopant of a conductivity type opposite to that of the substrate is introduced into the trench-circumscribed silicon region. The introduced isolation dopant is then thermally driven into the substrate, with lateral diffusion of isolation dopant physically constrained by the existing first narrow trench. Epitaxial silicon is then formed over the substrate, with polysilicon formed in regions overlying the filled narrow trench. A second, wider trench encompassing the first trench is etched to consume epitaxial silicon, polysilicon, and the sacrificial material. The second trench is then filled with dielectric material.

Abstract: The present invention relates to a method for semiconductor manufacturing of one semiconductor circuit, having a multiple of transistors NMOS1, NMOS2, NPN1, NPN2 of one type. The method comprises the steps of arranging a first region 4, 16 on a semiconductor substrate 1, and implementing two transistors of said type, having different sets of characteristics, in said first region 4, 16. The step of implementing said active devices comprises a step of creating a first 6′, 10′ and a second 6″, 10″ subregion within said first region 4, 16, and said step further comprising a step of introducing dopants having different sets of dose parameters, into a first and a second area, respectively, of said first region, said dopants being of a similar type, and a step of annealing said substrate 1 to create said first 6′, 10′ and second 6″, 10″ subregion, respectively, whereby two subregions, having different doping profiles, can be manufactured on a single integrated circuit.