Abstract: The present invention relates to a method of manufacturing a thin film transistor for use in a liquid crystal display apparatus or the like. In the method, impurity ions are implanted into a semiconductor by intermittently generating a plasma which generates impurity ions, for a predetermined period at a predetermined interval. By changing the duty rate at which the plasma is generated, the effective value of a beam current can be controlled over a wide range with excellent accuracy without changing rates of ions. As a result, it is possible to form a channel portion and a lightly doped drain layer of a field effect transistor which contains silicon as a main component, so that a field effect transistor and a liquid crystal display device can be manufactured with high quality and excellent productivity.

Abstract: A new method is provided for the creation of openings in a layer of dielectric while at the same time forming a dielectric that forms the dielectric of MIM capacitors. Under the first embodiment of the invention a layer of insulation, such as SixNy or SiON or TaN and TiN, is deposited over the surface of a semiconductor substrate, points of electrical contact have been provided in this semiconductor surface. A layer of IMD is deposited over the layer of insulation, an opening is created in the layer of IMD that aligns with and overlays a contact point over which a MIM capacitor is to be created. Under the second embodiment of the invention, a stack of three layers of a first layer of TaN followed by SiOx or SixNy followed by a second layer of TaN is used as the dielectric layer for the capacitor whereby the first layer of TaN is used as an etch stop for an opening that is etched for the creation of the upper plate of the capacitor.

Abstract: After HSG-Si 15a is formed on the surface of a polycrystal silicon film 15, heat treatment is conducted on it using a phosphorus diffusion apparatus in an atmosphere of a mixture gas containing POCl3, O2, and N2 gases in such a situation that the O2/POCl3 mole ratio is adjusted into 0.2 through 1.5, thus diffusing phosphorus into the HSG-Si 15a. With this, it is possible to suppress the corrosion of silicon by the chlorine radicals and inhibit the accelerated oxidation of silicon, thus preventing the reduction of the HSG-Si 15a.

Abstract: Provided is a method of manufacturing a semiconductor device having a capacitor above a semiconductor substrate, with which it is possible to reduce the number of steps and the cost of manufacture. Specifically, a polysilicon layer (12) in which impurity is diffused is deposited on the entire surface including the inside of a hole (8A). An etching process of the polysilicon layer (12) is performed to form a storage node electrode composed of the polysilicon layer (12) remaining on the bottom and side of a groove for metallization (15) and in the hole (8A). The storage node electrode is broadly divided into a storage node electrode body disposed on the bottom and side of the groove for metallization (15), and a plug part disposed in the hole (8A). The storage node electrode is electrically connected via the plug part to a diffused region (19) of a semiconductor substrate (1).

Abstract: A method of field implantation. Using a photo-resist layer as a mask, a substrate is implanted with ions to forming a selectively distributed ion field.

Abstract: A trench isolation structure is fabricated using high pressure and low temperature. A substrate is provided within which a trench is formed. The trench walls are annealed in nitrogen at a pressure above atmospheric pressure to remove silicon damage caused by plasma etching. The exposed side walls of the trench are oxidized at a pressure above atmospheric pressure to form an oxidized layer. The trench is filled with an oxide. Optionally, re-oxidation densification may be performed at a pressure above atmospheric pressure and a temperature in the range of about 600° C. to about 800° C.

Abstract: The invention describes three embodiments of methods for forming a balloon shaped STI trench. The first embodiment begins by forming a barrier layer over a substrate. An isolation opening is formed in the barrier layer. Next, ions are implanted into said substrate through said isolation opening to form a Si damaged or doped first region. The first region is selectively etching to form a hole. The hole is filled with an insulating material to form a balloon shaped shallow trench isolation (STI) region. The substrate has active areas between said balloon shaped shallow trench isolation (STI) regions. The second embodiment differs from the first embodiment by forming a trench in the substrate before the implant. The third embodiment forms a liner in the trench before an isotropic etch of the substrate through the trench.

Abstract: A semiconductor device and a fabrication method thereof which are capable of achieving a lightly doped drain (LDD) construction and reducing a parasitic capacitance generated between an impurity area and a word line by forming a trench in a portion of a semiconductor substrate and forming impurity areas around the trenches, include a semiconductor substrate, a plurality of trenches formed in the semiconductor substrate, first impurity areas formed along the outer surfaces of the plurality of trenches, second impurity areas formed on the bottom surfaces of the first impurity areas along the outer surfaces of the trenches, an insulating film filled in the trenches, a gate insulating film formed at a regular interval on the substrate having the insulating film filled in the trenches, and a gate electrode formed on the gate insulating film.

Abstract: A trench isolation structure including high density plasma enchanced silicon dioxide trench filling (122) with chemical mechanical polishing removal of non-trench oxide.

Abstract: In an example embodiment, a method for manufacturing a semiconductor device having shallow trench isolation comprises forming a trench region in a substrate having a substantially planar bottom, a first and second sidewall. In the trench region, the method forms a dielectric liner on the bottom and the first and second sidewalls. The dielectric liner is a silicon nitride compound. The dielectric liner minimizes the anomalous increases in threshold voltage with width (Vt versus W) owing to transient enhanced up-diffusion of the channel profile induced by source/drain implant damage. In addition, the anomalous increase in Vt versus W associated with the formation of an interstitial gradient in sub-micron devices is reduced. By using a nitrided liner, Vt roll off due to boron segregation is also minimized.

Abstract: Disclosed is an multi-layered SOI substrate, which includes a supporting substrate, and a first insulator, a semiconductor film, a second insulator and a single crystalline semiconductor film (SOI film) which are layered on the main surface of the supporting substrate. The SOI substrate is formed by a direct bonding technique, and a bipolar transistor and an MOS transistor are formed using the single crystalline semiconductor film (SOI layer). The extremely shallow junction can be formed without epitaxial growth, thereby significantly increasing the operation speed of the semiconductor device at a low cost.

Abstract: There are a device and method for protecting semiconductor material, wherein semiconductor material is processed on a surface of stabilized ice made from ultrapure water and particles of semiconductor material.

Abstract: A single-crystal silicon substrate having a surface layer which has been heat-treated in a reducing atmosphere containing hydrogen is prepared. An ion-implantation layer is formed by implanting oxygen ions. Subsequently, a buried oxide film (BOX) layer is formed by a desired heat-treatment utilizing the ion-implantation layer. An SOI substrate having a single-crystal silicon layer (SOI layer) which is formed on the BOX layer and has a remarkably reduced number of defects such as COPs is obtained.

Abstract: Silicon nanowires and silicon nanoparticle chains are formed by the activation of silicon monoxide in the vapor phase. The silicon monoxide source may be solid or gaseous, and the activation may be by thermal excitation, laser ablation, plasma or magnetron sputtering. The present invention produces large amounts of silicon nanowires without requiring the use of any catalysts that may cause contamination.

Abstract: A method for producing relaxed epitaxy layers on a semiconductor substrate by an epitaxy process, particularly molecular beam epitaxy, with a hydrogen source, wherein the following steps occur during an in situ process sequence: a hydrogen-containing intermediate layer is deposited on the substrate surface or diffused into the substrate near the surface; a strained epitaxy layer is grown on this intermediate layer; and the epitaxial layer subsequently is relaxed by a temperature treatment. A preferred layer sequence formed according to the above method includes a substrate of silicon with a hydrogen-containing intermediate layer that is deposited thereon or diffused into the substrate surface; a relaxed Si1−xGex epitaxial layer with a germanium concentration of x=0.1 to 0.3 as a first buffer layer; a hydrogen-containing intermediate layer deposited on or diffused into an outer surface of the first buffer layer; a Si1−xGex relaxed epitaxy layer with a germanium concentration of x=0.

Abstract: A process of epitaxially growing a Group IV semiconductor film on a surface (WS) of a substrate (W) made of a material comprising one of Si or Ge in a reaction chamber (14) under vacuum. The process includes the steps of heating the substrate to a temperature between 300° C. and 650° C., then introducing into the reaction chamber a first reactant gas containing one of Si and Ge corresponding to the material comprising the substrate while bombarding the surface with energetic ions having a flux ratio of about between 0.5 and 5 eV/adatom. The first reactant gas may be silane and the substrate made of Si, in which case the semiconductor film grown is Si. Alternatively, the first reactant gas may be germane and the substrate made of Ge, in which case the semiconductor film grown is Ge. Likewise, compounds of Si, Ge and C may be formed by introducing reactant gases comprising Si, Ge and C, for example silane, germane and methane, in the appropriate ratios.

Abstract: A microelectronic device such as a Metal-Oxide-Semiconductor (MOS) transistor is formed on a semiconductor substrate. A tungsten damascene interconnect for the device is formed using an etch stop layer of silicon nitride, silicon oxynitride or silicon oxime having a high silicon content of approximately 40% to 50% by weight. The etch stop layer has high etch selectivity relative to overlying insulator materials such as silicon dioxide, tetraethylorthosilicate (TEOS) glass and borophosphosilicate glass (BPSG). The etch stop layer also has a high index of refraction and is anti-reflective, thereby improving critical dimension control during photolithographic imaging.

Abstract: A method for fabricating a Y-gate structure is provided. The method comprises the steps of providing a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer, a first sacrificial layer over the protection layer and a second sacrificial layer over the first sacrificial layer. An inwardly sloping opening is formed in the second sacrificial layer and the opening is extended vertically in the first sacrificial layer. A contact material is deposited over the second sacrificial layer filling the opening with the contact material and forming a contact layer and portions of the contact material outside a gate region are removed. The first sacrificial layer and the second sacrificial layer are then removed.

Abstract: The present invention provides a semiconductor device and a method for fabricating the same. In the present invention, an electron depletion preventing layer is formed in a bottom portion of a polysilicon gate of MOSFET devices. In addition, the ion-implanted layer of boron ions is formed in an upper portion of the polysilicon gate to increase conductivity thereof. Because the electron depletion preventing layer is formed in the bottom portion of the polysilicon gate, electron depletion and boron penetration into the transistor channel region can be reduced and thus operational properties of the semiconductor device can be stabilized.

Abstract: The present invention provides a process for forming a sub-micron p-type metal oxide semiconductor (PMOS) structure on a semiconductor substrate. The process includes forming a gate oxide on the semiconductor substrate, forming a gate layer on the gate oxide by depositing a first gate layer on the gate oxide at a first deposition rate and depositing a second gate layer on the first layer at a second deposition rate to provide an improved stress accommodation within the gate structure. The process further includes forming a silicide dopant barrier on the gate. Due to the presence of the improved stress accommodation in the gate, the integrity of the silicide dopant barrier is substantially enhanced. This increased silicide integrity prevents significant damage to the silicide dopant barrier layer during subsequent fabrication processes.

Abstract: A container capacitor having a recessed conductive layer. The recessed conductive layer is typically made of polysilicon. The recessed structure reduces the chances of polysilicon “floaters,” which are traces of polysilicon that remain on the surface of the substrate, coupling adjacent capacitors together to create short circuits. The disclosed method of creating such a recessed structure uses successive etches. One of these etches selectively isolates a rim of the polysilicon within the container to recess the rim, while the remainder of the polysilicon in the container is protected by photoresist.

Abstract: A method of fabricating a deflection aperture array used in an electron beam exposure apparatus and a wet etching method and apparatus for fabricating the deflection aperture array are disclosed. In wet etching an aperture array substrate, a jig is used for holding the substrate in such a manner that only a portion of the reverse side to be etched is exposed to an etching solution so that the surface protective film can be removed before wet etching. According to the wet etching method, a gas is introduced into or discharged from an enclosed spacing facing a non-etched surface thereby to adjust the internal pressure of the enclosed spacing. The internal pressure of the enclosed spacing is thus detected and held at a predetermined value in accordance with the detected pressure.

Abstract: In one embodiment of the invention, conductive support structures (112) are formed within an interlevel dielectric layer. The conductive support structures (112) lie within the bond pad region (111) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (112) are formed using the same processes that are used to form metal interconnects in the device region (109) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (109). Conductive support structures (114) are also formed within the scribe line region (104) to provide support to the interlevel dielectric layer in this region of the integrated circuit.

Abstract: A process for forming a dual damascene structure. The process includes forming a stack including insulating layers and a stop layer where two masks are formed above the stack. One of the masks is used to form via or contact openings in the insulating layers and the second mask is used to form grooves for interconnections in the insulating layers. In an alternative embodiment, the grooves are formed before the via or contact openings.

Abstract: A method for producing reliable contacts in microelectronic devices and contacts produced thereby are provided. In one embodiment of the invention, a first conductive layer is formed over a first dielectric layer. The first conductive layer contains a pattern etched therein. A second dielectric layer is deposited over the first conductive layer and a via is etched therein over the pattern, thus exposing a portion of the pattern and the first conductive layer. The structure is then further etched to remove a portion of the first dielectric layer using the exposed portions of the first conductive layer as a mask. The structure is then subject to an isotropic etch to create undercuts in the first dielectric layer underneath the exposed portions of the first conductive layer. A conductive material can then be deposited into the via to fill the undercut, thus contacting the first conductive material on the exposed top, sides, and underside of the layer to produce a highly reliable contact.

Abstract: The present invention pertains to a carrier layer and a contact enabled by the carrier layer which enables the fabrication of aluminum (including aluminum alloys and other conductive materials having a similar melting point) electrical contacts in multilayer integrated circuit vias, through holes, or trenches having an aspect ratio greater than one. In fact, the structure has been shown to enable such contact fabrication in vias, through holes, and trenches having aspect ratios as high as at least 5:1, and should be capable of filing apertures having aspect ratios up to about 12:1. The carrier layer, in addition to permitting the formation of a conductive contact at high aspect ratio, provides a diffusion barrier which prevents the aluminum from migrating into surrounding substrate material which operates in conjunction with the electrical contact.

Abstract: A method of fabricating a dual damascene is provided. A dielectric layer is formed on a substrate. A diffusion barrier layer is formed on the dielectric layer. A portion of the diffusion barrier layer and the dielectric layer is removed to form a trench and a via hole. A barrier layer is formed on the diffusion barrier layer and in the trench and the via hole. The barrier layer on the diffusion barrier layer is removed by chemical-mechanical polishing. A conductive layer is formed in the trench and the via hole by selective deposition. A planarization step is performed with the diffusion barrier layer serving as a stop layer.

Abstract: Disclosed is a method for forming multi-layer interconnection of semiconductor device, which allows a contact hole to be formed at a size smaller than a resolution limit of the exposing system.

Abstract: The present invention provides a base layer structure formed in a hole having an upper portion which has a larger diameter than other portions thereof. The hole is formed in an insulation layer in a semiconductor device. The base layer structure comprises a base layer which extends on at least a part of the upper portion of the hole and over at least a part of the insulation layer in the vicinity of a top of the hole, wherein the base layer extending on the upper portion has an effective thickness in an elevational direction, which is thicker than a thickness of the base layer over the insulation film and also thicker than a critical thickness which allows that at least a part of the base layer on the upper portion of the hole remains after an anisotropic etching process, whilst the base layer having extended over the insulation layer is etched by the anisotropic etching process.

Abstract: This invention is a process for forming an effective titanium nitride barrier layer between the upper surface of a polysilicon plug formed in a thick dielectric layer and a platinum lower capacitor plate in a dynamic random access memory which is being fabricated on a silicon wafer.

Abstract: A method for manufacturing a salicide transistor, a semiconductor storage, and a semiconductor device that can solve both an increase in narrow-line resistance and an increase in P-N-junction leakage, and can give an optimized process as the total LSI device manufacturing process flow. After adding an impurity in the high-concentration source/drain region on a semiconductor substrate, a heat treatment is performed at a first temperature, then a heat treatment is performed for forming salicide at a second temperature higher than a predetermined temperature and lower than the first temperature for a first period of time, an interlayer insulating film is formed, and heat treatment is performed at a third temperature higher than the second temperature and lower than the first temperature. Since the crystallinity of the implanted layer 109 has been recovered before forming the silicide protecting film, salicide can be formed under the conditions where the crystallinity of the diffusion layer is good.

Abstract: The invention provides a method for forming a microelectronic device comprising: forming a first electrode; depositing an adhesion layer over the first electrode utilizing high density plasma physical vapor deposition, wherein the adhesion layer comprises a material selected from Ta, TaNx, W, WNx, Ta/TaNx, W/WNx, and combinations thereof, depositing a dielectric layer over the adhesion layer; and forming a second electrode over the dielectric layer. The invention also provides a microelectronic device comprising: a first electrode; a second electrode; a dielectric layer disposed between the first and second electrodes; and an adhesion layer disposed between the first electrode and the dielectric layer, wherein the adhesion layer comprises a material selected from Ta, TaNx, W, WNx, Ta/TaNx, W/WNx, and combinations thereof.

Abstract: A method for forming integrated circuit device structures upon active semiconductor regions of a semiconductor substrate. The active semiconductor regions are defined by Field OXide (FOX) isolation regions which are formed through a Polysilicon Buffered LOCal Oxidation of Silicon (PBLOCOS) oxidation mask structure. The PBLOCOS oxidation mask structure includes a blanket pad oxide layer which resides upon the semiconductor substrate, a blanket polysilicon buffer layer which resides upon the blanket pad oxide layer and a patterned silicon nitride layer which resides upon the blanket polysilicon buffer layer. Portions of the blanket polysilicon buffer layer and the blanket pad oxide layer exposed through the patterned silicon nitride layer are completely consumed to leave remaining the patterned silicon nitride layer, a patterned polysilicon buffer layer and a patterned pad oxide layer upon the active regions of the semiconductor substrate which are separated by the FOX isolation regions.

Abstract: A multi-component layer is deposited on a semiconductor substrate in a semiconductor process. The multi-component layer may be a dielectric layer formed from a gaseous titanium organometallic precursor, reactive silane-based gas and a gaseous oxidant. The multi-component layer may be deposited in a cold wall or hot wall chemical vapor deposition (CVD) reactor, and in the presence or absence of plasma. The multi-component layer may also be deposited using other processes, such as radiant energy or rapid thermal CVD.

Abstract: The method of producing semiconductor device comprises ion implanting a first p-type impurity to form a p-type source-drain region 7 and a heat-treatment to activate followed by ion implantation of a second p-type impurity, ion-implanting a third impurity to convert the surface of at least a diffusion layer of a source-drain portion into amorphous to form titanium silicide 9. This reduces contact resistance between the titanium silicide layer and the p-type impurity layer to improve the current driving performance of the p-type MOS transistor.

Abstract: A semiconductor comprising a semiconductor device formed on a semiconductor substrate, an interlevel insulating film having holes and a ring-shaped groove in a circuit area formed on the semiconductor substrate and having the semiconductor element formed therein, the ring-shaped groove seamlessly surrounding an outer periphery of the circuit area, via plugs formed in the holes in the interlevel insulating film, a wiring connected to the plug electrodes and mainly comprising copper, and a via ring having a layer formed in the ring-shaped groove and mainly comprising aluminum, wherein no layer mainly comprising copper is formed in the via ring layer.

Abstract: A method and apparatus for planarizing a microelectronic substrate. In one embodiment, the microelectronic substrate is engaged with a planarizing medium that includes a planarizing pad and a planarizing liquid, at least one of which includes a chemical agent that removes a corrosion-inhibiting agent from discrete elements (such as abrasive particles) of the planarizing medium and/or impedes the corrosion-inhibiting agent from coupling to the discrete elements. The chemical agent can act directly on the corrosion-inhibiting agent or can first react with a constituent of the planarizing liquid to form an altered chemical agent, which then interacts with the corrosion-inhibiting agent. Alternatively, the altered chemical agent can control other aspects of the manner by which material is removed from the microelectronic substrate, for example, the material removal rate.

Abstract: A composition for chemical mechanical polishing that includes a slurry is described. A sufficient amount of a selectively oxidizing and reducing compound is provided to produce a differential removal of a metal and a dielectric material. A pH adjusting compound adjusts the pH of the composition to provide a pH that makes the selectively oxidizing and reducing compound provide the differential removal of a metal and a dielectric material. A composition may include an effective amount of an hydroxylamine compound, ammonium persulfate, a compound which is an indirect source of hydrogen peroxide, and a peracetic acid or periodic acid. A method for chemical mechanical polishing is described which includes applying a slurry that includes the composition to a surface to produce mechanical removal of the metal and dielectric material.

Abstract: A process for etching a dielectric layer, including the steps of forming, over the dielectric layer, a layer of polysilicon, forming over the layer of polysilicon a photoresist mask layer, etching the layer of polysilicon using the photoresist mask layer as an etching mask for selectively removing the layer of polysilicon, removing the photoresist mask layer from over the layer of polysilicon, etching the dielectric layer using the layer of polysilicon as a mask. Subsequently, the layer of polysilicon is converted into a layer of a transition metal silicide, and the layer of transition metal silicide is etched for selectively removing the latter from over the dielectric layer.

Abstract: Presented is a method of enhancing the rate of removal of a photoresist layer from wafers of semiconductor material after the latter have gone through various process steps to define the patterns of integrated circuits. The method includes heating the wafer and treating it with low-pressure steam in a vacuum environment before starting to remove the photoresist by plasma or wet solutions. This pre-treatment of the photoresists allows the time for removing the photoresist to be reduced substantially and eliminates problems from residue.

Abstract: A method of cleaning a contact area of a semiconductor or metal region on a substrate of an electronic device. First, the contact area is cleaned by exposing the substrate to a plasma that includes fluorine-containing species. Second, the substrate is exposed to a second atmosphere that scavenges fluorine, preferably formed by plasma decomposition of a hydrogen-containing gas. The second atmosphere removes any fluorine residue remaining on the contact area and overcomes any need to include argon sputtering in the cleaning process. Another aspect of the invention is a method of depositing a refractory metal over a contact area of a semiconductor region on a substrate. The contact area is cleaned according to the two-step process of the preceding paragraph. Then a refractory metal is deposited over the contact area. The two-step cleaning process can reduce the electrical resistance between the refractory metal and the semiconductor region.

Abstract: A method of manufacturing a field emission element including the steps of: depositing an emitter electrode film on the surface of an emitter portion forming recess formed on a substrate; forming an emitter portion of an emitter electrode by removing the emitter electrode film deposited on the bottom of the emitter portion forming recess; depositing a sacrificial film on the surface of the emitter electrode and on the bottom of the emitter portion forming recess, and thereafter depositing a second gate electrode film on the surface of the sacrificial film. With this manufacture method, field emission elements having small unevenness in vertical positions of emitter and gate electrodes can be formed.

Abstract: There is provided a method for forming a SOG layer, which can enhance flatness. In the method, the SOG layer is spin-coated on a wafer and the SOG solvent is spread in a closed receptacle containing the wafer to make a saturated vapor pressure in the receptacle. Thus, the SOG layer can be more flattened and be obtained with larger thickness than that of the prior art to enhance the productivity. The present invention can also maximally suppress the production of edge beads generated by spin coating and inhibit the bowing generated during etching of the SOG layer for forming a contact hole, with enhancing the flatness.

Abstract: Nanoporous silicone resins and silicone resin films having low dielectric constants and a method for preparing such nanoporous silicone resins.

Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components.

Abstract: Disclosed is an MOCVD method of forming a tantalum oxide film. First, water vapor used as an oxidizing agent is supplied into a process container to cause moisture to be adsorbed on a surface of each semiconductor wafer. Then, PET gas used as a raw material gas is supplied into the process container and is caused to react with the moisture on the wafer at a process temperature of 200° C., thereby forming an interface layer of tantalum oxide. Then, PET gas and oxygen gas are supplied into the process container at the same time, and are caused to react with each other at a process temperature of 410° C., thereby forming a main layer of tantalum oxide on the interface layer.

Abstract: A cleaning method in a semiconductor fabrication process includes providing a dilute composition consisting essentially of phosphoric acid and acetic acid and exposing a surface, e.g., aluminum, to the dilute composition. For example, the dilute composition includes phosphoric acid at a concentration of about 5% or less by volume and acetic acid at a concentration of about 30% or less by volume. Further, the cleaning method may use a composition comprising phosphoric acid and acetic acid, wherein the composition includes phosphoric acid at a concentration of X%, wherein X is about 5% by volume or less, and acetic acid at a concentration of about (100-X%) by volume or less. The cleaning method may be used, for example, in fabricating interconnect structures, aluminum containing structures, and multilevel interconnect structures. Cleaning compositions for use in the cleaning methods are also provided.

Abstract: Food industry disposable wet sanitizer wipe(s) (10) for food preparation surfaces, utensils, cooking instruments, containers and the like; using U.S. food industry approved legal sanitizer(s) and their respective legal solution parts per million of quaternary ammonium; chlorine/bleach and/or iodine which is saturated/impreganted into at least one absorbent fabric sheet(s) (11) and/or sponge(s) (12) which optionally may have at least one foldable line (13); such absorbent fabric and/or sponge is enclosed by at least one over-wrap (19) layer and sealed (26) on at least one border margin and/or side edge (21) thereof. A release-opening (22) permitting a food-related instrument and the like, to enter the sanitizer packet (20) from at least one exterior face (25) surface(s) of the packet (20) or blister pack (30). The packets and blister-packs may be non-articulated and/or articulated to each other by release lines of separation (24) which permit easy individual packet separation as desired.

Abstract: The subject of the invention is a mineral wool capable of being dissolved in a physiological medium and comprising the constituents below in the following percentages by weight: SiO2 38-52% Al2O3 16-23% RO (CaO + MgO) 4-15% R2O (Na2O + K2O) 16-25% B2O3 0-10% Fe2O3 (total iron) 0-3%, preferably 0-1.5% P2O5 0-3%, preferably 0-1.5% TiO2 0-2%.

Abstract: The present invention provides a method for the manufacture of ceramic composite fibers, and the present invention relates to a method for the manufacture of a composite fiber in which a second phase is dispersed within a matrix fiber, wherein the matrix consists of a substance selected from alumina, zirconia, mullite, YAG, silica, magnesia, nitrides, carbides, metals, alloys, and polymers; the second phase consists of a substance selected from zirconia, mullite, YAG, and other oxides, or from metals; and the composite fiber is produced by synthesizing a fiber from a precursor solution containing the substance of the matrix, and the starting solution which serves as the second phase, dispersed through the matrix solution, and then heating the fiber.