Abstract: A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which includes a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume an ASSERTED state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of ASSERTED inputs exceeds the threshold value. In the preferred embodiment, the gate exhibits hysteresis such that the output remains ASSERTED while the number of ASSERTED inputs remains greater than zero, less than the threshold value. In an alternate embodiment, an array of simplified threshold elements is used to form more complex threshold gates.

Abstract: An input/output (I/O) buffer having an output node tolerant of an externally applied high voltage signal is powered by a lower voltage supply potential and comprises a n-well region and a bias generation circuit that generates a reference voltage at an internal node. A PMOS pull-up transistor is coupled between the lower voltage supply potential and the output node, and NMOS pull-down transistor is coupled between the output node and a ground reference potential. First and second PMOS charging transistors each of their gates coupled to the internal node, with the first PMOS charging transistor being coupled between the output node and the gate of the PMOS pull-up transistor. The second PMOS charging transistor is coupled between the output node and the n-well region.

Abstract: A driver circuit for transmitting a signal by switching the direction of a signal current which flows on a pair of transmission lines. The drains of field effect transistors having the opposite polarities are connected to each other so as to constitute first and second switches. One of differential driving signals is input to the gate terminal of each of the field effect transistors constituting the first switch, while the drain terminal is connected to one of the transmission line pair. The other of the differential driving signals is input to the gate terminal of each of the field effect transistors constituting the second switch, while the drain terminal is connected to the other of the transmission line pair.

Abstract: A bidirectional full swing voltage repeater implemented on a signal line of an integrated circuit, which includes a first enable node for providing a first enable signal and a second enable node for providing a second enable signal. There is included a first full-swing unidirectional repeater circuit coupled between a first portion of the signal line and a second portion of the signal line. The first full-swing unidirectional repeater is configured to pass a first full swing signal from the first portion of the signal line to the second portion of the signal line when the first enable signal is enabled. The second full-swing unidirectional repeater circuit is coupled between the first portion of the signal line and the second portion of the signal line.

Abstract: A primary driver is activated to drive an output signal in response to an input signal. A reference signal is generated in response to the input signal. The output signal is compared to the reference signal. When the output signal lags the reference signal by a predefined amount an auxiliary driver is activated.

Abstract: The I/O terminal positions of a pass transistor logic circuit cell are distributed in the cell, an output amplifier is provided on the end part of the cell, the pass transistor circuit is arranged in the direction in which a potential supply line extends, a signal polarity inverting circuit is laid out in the cell and the arrangement of wells is different from the arrangement of a conventional CMOS logic circuit.

Abstract: In order to produce a logic circuit excellent in circuit characteristics which are area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function, and respective nodes of the diagram are mapped into 2-inut, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. In the pass transistor logic circuit, a pass transistor selector operating as a NAND or NOR logic with any one of its two inputs excluding the control input being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass tansistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value (if the resulting logic circuit is smaller in area, delay time or power consumption than the original pass transistor logic circuit).

Abstract: The invention includes a differential input stage that is coupled to a turn around stage with a differential output. The input common mode voltage range is independent of the output common mode voltage range and the electronic circuitry is suited for use with other circuits such as an amplifier. The circuitry provides Class AB operation with quiescent and bias currents that are significantly less than the maximum output signal current so that overall power consumption is significantly reduced. The biasing of the output transistors in the turn around stage is floated and the invention is well suited for use with other circuits that require an input stage that can operate between the rails of a voltage supply. Also, the amount of noise is reduced and the offset performance of the circuit is improved by cross coupling the emitters of separate transistors employed to bias the output transistors in the turn around stage.

Abstract: A sample and hold in a switched capacitor circuit with frequency shaping. The sample and hold does not require a pair of large area, power-consuming operational amplifiers and, as such, consumes less power and less area. Preferably, the sample and hold is operable in four different states wherein a different set of switches are closed in each of the four states. The switches are controlled by two clock signals and a plurality of signals derived from the two clock signals, such as four signals derived from the two clock signals. Desirably, the sample and hold with frequency shaping is configured to sample a voltage across a first capacitor while a second capacitor is disconnected from said first capacitor, and is configured to thereafter connect the second capacitor to the first capacitor and possibly discharge at least a portion of a charge held in the first capacitor into the second capacitor.

Abstract: There is provided buffer circuitry that can include a data output circuit for connecting a first power supply to its output terminal when a data applied thereto is at a HIGH level, or connecting a ground to the output terminal when the data is at a LOW level, a comparator for comparing the frequency of a clock signal applied thereto with a reference frequency, and a driving capability changing circuit for, only if the comparator outputs a comparison result indicating that the frequency of the clock signal is greater than the reference frequency, connecting a second power supply to the output terminal when the data is at a HIGH level, or connecting a ground to the output terminal when the data is at a LOW level.

Abstract: A current control circuit capable of minimizing changes in an output high voltage VOH and an output low voltage VOL and quickly and accurately bringing a divided voltage to a steady state, and a packet-type semiconductor memory device including the current control circuit. The current control circuit includes a first differential amplification type buffer for transmitting the voltage of a first pad, that is, the output high voltage VOH, without change in response to a current control enable signal, a second differential amplification type buffer for transmitting the voltage of a second pad, that is, the output low voltage VOL, without change in response to the current control enable signal, and a voltage divider for dividing a voltage ranging between the voltage outputs of the first and second differential amplification buffers, and outputting the divided voltage.

Abstract: The present invention provides a buffer circuit that consumes little power. Specifically, the buffer circuit can operate at lower voltages (e.g., 3.3 V) and interface with other circuits that operate at higher voltages (e.g., 5 V) at an interface node. In a preferred embodiment, the buffer circuit has a driver PMOS transistor, and a pre-driver circuit having a pull-up circuit coupled to the interface node via a PMOS switch transistor and a first PMOS pass transistor. The pre-driver biasing circuit is configured to decouple the pull-up circuit from the interface node when an input voltage at the interface node exceeds the VDD voltage by a PMOS threshold voltage.

Abstract: The present invention provides a buffer circuit that can tolerate over-voltage, and a method for protecting buffer circuits from over-voltage. Specifically, the buffer circuit can operate at lower voltages (e.g., 3.3 V) and interface with other circuits that operate at higher voltages (e.g., 5 V). In a preferred embodiment, the buffer circuit has a pre-driver circuit having a pull-up circuit coupled to an interface node via a PMOS switch transistor. The pre-driver biasing circuit is configured to decouple the pull-up circuit from the input voltage source when an input voltage at the interface node exceeds the VDD voltage by a threshold voltage. The buffer circuit has a first biasing transistor that ties an N-well of the integrated circuit to the VDD voltage source when a control node of a PMOS driver transistor is in a first logic state, and a second biasing transistor that ties the N-well to the VDD voltage source when the control node of the PMOS driver transistor is in a second logic state.

Abstract: A signal obtained through logical operation of an output signal from a K·T delay circuit delaying a supplied signal by K cycles of an input signal and a feedback signal of an M·T delay circuit delaying a supplied signal by M cycles of the input signal through a feedback part is supplied to the M·T delay circuit. Among signals generated by the M·T delay circuit, signals out of phase by K/2 cycles of the input signal is Ored or ANDed by a duty control circuit for controlling a duty ratio. Alternatively, cascaded latch circuits operating in synchronization with a clock signal have a final output coupled to a first stage input through an inverter. The final output provides a frequency-divided signal. The number of components is reduced, layout efficiency is improved and a frequency-divided signal having a duty ratio of 50% is provided.

Abstract: A variable delay line outputs a clock signal advanced in phase by a time corresponding to a sum tH+tL of a time tH required to output high level data from an OCD circuit and a time tL required to output low level data from the OCD circuit. A replica circuit for outputting low level data has the same configuration as a circuit portion of the OCD circuit through which low level data passes. The replica circuit outputs a start signal SSH for outputting high level data from the OCD circuit. Another replica circuit for outputting high level data has the same configuration as a circuit portion of the OCD circuit through which high level data passes. The replica circuit outputs a start signal SSL for outputting low level data from the OCD circuit.

Abstract: The present invention provides an improved, efficient DLL design. In one embodiment, it includes a voltage controlled delay line, a phase comparator, and a dynamic bias source. The delay line has an associated delay that is controllably adjusted by a received control signal. The delay line also has an input for receiving a reference signal and one or more outputs for providing one or more delayed versions of the reference signal. The phase comparator is operably connected to the delay line in a closed loop fashion for controlling the control signal based on the phase difference between the reference signal and one of the one or more delayed reference signal versions to cause the delay line to generate an output delayed reference signal that is in synch. with the reference signal but delayed from it by a predetermined quantity. The dynamic bias source provides power to the delay line as it is needed so that the control signal is not adversely affected by changes in the delay lines power demands.

Abstract: A semiconductor integrated circuit has an internal clock signal generator circuit and a data input/output circuit. The internal clock signal generator circuit includes a clock receiver, a synchronous delay control circuit, a clock driver, an output control circuit, a delay monitor, and a control signal generator circuit. Accordingly, in a delay measuring mode, a delay in the input signal is set in the delay monitor based on a measurement start signal and a measurement stop signal. After completion of the delay measuring mode, the delay monitor causes the signal CLK, outputted from the clock receiver, to lag behind by a delay set in the delay measuring mode. Further, the delay monitor outputs the delayed signal to the synchronous delay control circuit.

Abstract: A signal transmission circuit, a CMOS semiconductor device, and a circuit board improve the signal transmission characteristic of a signal line having a large capacitance that is generated on the long signal line inside a large-scale integrated circuit when the signal line is long or when many driven circuits are connected to the signal line. The midpoint voltage of the power source voltage of the drive circuit and driven circuit is output. An assist-circuit having low output impedance is then connected to the signal line. The voltage of the signal line is thus held at the midpoint voltage of the power source voltage. At the same time, a drive signal that is output from the driver circuit is excited centered at the midpoint voltage (threshold voltage of the driven circuit) with a small amplitude. The driven circuit is then driven by this drive signal that is restricted to the small amplitude.

Abstract: The edge rate controller circuit includes: a first transistor coupled to an output control node; a second transistor coupled to the output control node; an edge rate control driver; a third transistor coupled to the first transistor; a fourth transistor coupled in parallel with the third transistor, the fourth transistor having a control node coupled to the edge rate control driver; a fifth transistor coupled to the second transistor; and a sixth transistor coupled in parallel with the fifth transistor, the sixth transistor having a control node coupled to the edge rate control driver.

Abstract: A timing circuit which is used to synchronize different circuit to each other. The timing circuit includes adjustable delay apparatus which delay an input signal with a predetermined value. The timing circuit uses counting devices to count the input signal and the delayed output signal and thereby provides a simple and more cost effective timing circuit.

Abstract: This invention provides a phase splitter device that generates in-phase and quadrature outputs that have a phase difference of substantially a phase set value (e.g., 90°) and an amplitude difference of substantially an amplitude set value (e.g., zero). A first feedback loop controls the phase difference between the in-phase and the quadrature outputs while a second feedback loop controls the amplitude difference between the in-phase and quadrature outputs. The phase splitter device controls the amplitude difference and the phase difference between the in-phase and the quadrature outputs by a common mode of control signals and a differential between the control signals, respectively. In this way, the phase splitter device generates in-phasing and quadrature outputs that have a phase difference and an amplitude difference that is substantially equal to the amplitude and phase set values (e.g., zero and 90°) using a single set of control signals.

Abstract: A variable delay circuit has a positive logic variable delay circuit which delays an edge of a signal which is input through an input terminal and a negative logic variable delay circuit which delays an edge of the signal input through an input terminal. Only an edge delayed in accordance with the set time is extracted from all the edges of a signal supplied from the positive logic variable delay circuit and all the edges of a signal supplied from the negative logic variable delay circuit in an extracting circuit of the variable delay circuit.

Abstract: A shaped pulse generation circuit for applications such as automatic test equipment pin drivers employs an active feedback circuit that adds a pre-emphasis to the output pulses, thereby compensating for the effect of the transmission system between the pin driver and the device under test. Current pulses are applied to the pin driver output transistors in conjunction with the production of rising and falling output pulse edges to produce edge overshoots that are mitigated during pulse transit to the device under test. The driver circuit together with the pre-emphasis active feedback circuit can be integrated onto a single chip, with an additional programming circuit employed to control the amount of pre-emphasis.

Abstract: An ASIC device and method provide clock signals to load circuits having a balanced clock tree including a master clock line, for example a clock trunk or H-tree, and branched clock lines feeding the clock signals to load circuits and being balanced with respect to the delays and loads in domains of the ASIC device to which the branched clock lines supply the clock signals. The ASIC device and method generate derived clock signals by gating the master clock signal, in which the derived clock signals have a frequency reduced by a factor n>1 (n=2, . . . , N), which is adapted to the need of the load circuits in a particular domain, and route the master clock signal and/or the derived clock signal for a particular domain to the load circuit of said domain.

Abstract: A current pulse generator with process-independent and temperature-independent symmetric switching times, includes a differential stage which is adapted to generate a transmission current and a circuit for driving the differential stage which is adapted to generate a control voltage for the differential stage. The generator also includes a circuit for compensating the variations in the values of degeneration resistors of the differential stage, to generate, with the differential stage driving circuit, a current for controlling the differential stage, to keep the switching times of the current pulses of the generator substantially unchanged and symmetrical despite variations in the manufacturing process of the generator and the temperature.

Abstract: An offset integrator and method are provided to induce integrator leakage while simultaneously latching and canceling its own offset. The method includes combining a first and second input signals with a part of the output signal of a different polarity to produce a charge signal. An accumulation of the charge signal on a plurality of storage components is used to reduce the offset component of the output signal and simultaneously inducing an integrator leak. A positive and negative components of the input signals are combined with a negative and positive offset components of the part of the output signal, respectively. The method liner includes modifying a positive and negative components of an in-phase and a quadrature signal. A reset signal may be provided to erase a plurality of memory locations. A gating scheme may be used to provide a predetermined signal to produce a two-phase, non-overlapping signal.

Abstract: When PMOS transistors are successively turned off, the resistance between a PMOS transistor and a power supply VDD is changed, and the amplitude of a waveform at the junction between the last-mentioned PMOS transistor and an NMOS transistor is controlled based on the changed resistance. Thereafter, a waveform output unit outputs a waveform whose harmonic components are made smaller from the junction between the PMOS transistor and the NMOS transistor.

Abstract: A variable impedance circuit for use with a load, such as an IC-based active filter circuit, formed on a semiconductor substrate. The variable impedance circuit includes at least one non-linear element, such as a MOSFET. The variable impedance circuit also includes a means for suppressing at least a second order harmonic distortion term from the non-linear element.

Abstract: A mixer structure and method for using same in accordance with the present invention includes a multi-phase mixer. A VCO includes a plurality of differential delay cells to output a plurality of multi-phase clock signals. The multi-phase mixer can include a load circuit, switch circuit, noise reduction circuit and an input circuit. The switch circuit is coupled to receive the plurality of multi-phase clock signals and includes a first switch array and a second switch array coupled to the load circuit, respectively. The noise reduction circuit coupled to the switch circuit can include a transistor responsive to a bias voltage. The input circuit includes a transistor receiving the input signal. The first switch array includes a first plurality of switches coupled between a first output terminal and a second node, and the second switch array includes a second plurality of switches coupled between a second output terminal and the second node.

Abstract: A power switching circuit with reduced interference radiation includes at least one pair of low-side and high-side MOS power transistors, between which a load resistor is connected. One or at least one of the low-side MOS power transistors is connected to a drive circuit having a divider for dividing a difference between a maximum output voltage of the MOS power transistor and an instantaneous output voltage at the load resistor as a dividend, by a maximum output voltage of the MOS power transistor as a divisor, and a level converter for generating a drive voltage for the MOS power transistor. The drive voltage is proportional to the quotient.

Abstract: First main electrodes of second and third semiconductor elements are connected to the first main electrode of the first semiconductor element, control electrodes of the second and third semiconductor elements are connected to the control electrode of the first semiconductor element, a second main electrode of the second semiconductor element is connected to a first resistor, and a second main electrode of the third semiconductor element is connected to a second resistor. Second main-electrode voltages of the first and second semiconductor elements are compared with each other by a first comparator, a control voltage is supplied a control voltage to the control electrodes of the first and second semiconductor elements according to an output of the first comparator by control means. Second main-electrode voltages of the first and third semiconductor elements are compared with each other by a second comparator.

Abstract: An apparatus for adjusting static thresholds of CMOS circuits. The apparatus includes a low reference circuit including at least one channel n-channel MOS device having a back gate and a high reference circuit including at least one p-channel MOS device having a back gate. A feedback loop is provided for providing a control voltage to the back gate of the n-channel NMOS device while a second feedback loop is provided for providing a second control voltage to the back gate of the p-channel MOS device. A control voltage is applied to the first feedback loop while a control voltage is applied to the second feedback loop. The output of the low reference circuit is coupled to the first feedback loop and the output of the high reference circuit is coupled to the second feedback loop.

Abstract: A current source for providing matched currents at low and variable bias voltages. The current source includes a first circuit, a second circuit, and a biasing circuit. The first circuit provides a first current. The first circuit includes a first transistor with a control terminal, a first terminal, and second terminal. A second circuit provides an output current to an output node. The second circuit includes a second transistor with a control terminal, a first terminal, and second terminal. The biasing circuit includes a third transistor with a control terminal, a first terminal, and second terminal. The biasing circuit also includes a fourth transistor with a control terminal, a first terminal, and second terminal. The biasing circuit provides a voltage at the first terminal of the third transistor and a voltage at the control terminal of the second transistor so that a voltage at the first terminal of the second transistor and a voltage at the second terminal of the first transistor match.

Abstract: An electronics module (FIG. 1, 30) requires two distinct voltage inputs (V1, V2) and can be damaged when the difference between the two voltages exceeds a maximum value during power up. Additionally the electronics module (30) can be damaged during a power down transition when the difference between the two voltages exceeds a maximum negative value. A voltage ratio control circuit (FIG. 8) which includes at least one diode (D1), a capacitor (C1) whose value is proportional to the product of the value of the second voltage source (V2) and the value of the sum of any decoupling capacitances (C2) divided by the difference between the two input voltages is used to reduce the difference between the two voltages. This prevents damage to the electronic module (FIG. 1, 30) during power up and power down transitions caused by excessive voltage differences in the two voltage inputs (V1 and V2).

Abstract: An internal power voltage generating circuit for a semiconductor device reduces current consumption during stand-by mode and allows a fast transition to active mode by using a single output driver for both standby mode and active mode. The output driver is coupled to both an active mode comparison circuit, which is disabled during stand-by-mode, and a stand-by mode comparison circuit which is enabled during stand-by-mode. The active mode comparison circuit is fabricated from large transistors and generates a first output signal having a high current capacity to turn the output driver completely on. The stand-by mode comparison circuit is fabricated from small transistors and generators a second output signal having a low current capacity which only turns the output driver partially on. The output driver can switch quickly from stand-by-mode to active mode because it is not turned completely off during stand-by-mode. This also eliminates the need for an additional circuit for turning the driver completely off.

Abstract: Resistance elements are inserted into a main power supply line and a main ground line so that offset differential amplifiers receive voltages developed across the same. The differential amplifiers control transistors connected to a sub power supply line and a sub ground line. Thus, a leakage current flowing from the sub power supply line to the main ground line and that flowing from the main power supply line to the sub ground line are regularly kept constant. Consequently, it is possible to prevent an operation delay in an initial stage of a standby state while keeping an effect of reducing a subthreshold leakage current in a semiconductor circuit device having a hierarchical power supply structure.

Abstract: Clock circuitry on an integrated circuit chip includes a differential buffer with common-mode rejection circuitry. The differential buffer includes first and second DC paths, each including semiconductor devices connected in cascode circuits. A tap of the first path supplies bias voltage to control electrodes of devices of the first and second paths. Control electrodes of devices in the cascode circuits of the first and second paths are connected to be biased by opposite power supply voltages of the buffer.

Abstract: The device for amplifying input signals (10) comprises a control stage (12) and a switching bridge amplifier (14), which is coupled to said control stage via at least first and second control signals (16, 18). The bridge amplifier (14) can be switched in at least two states, in dependence upon the control signals (16, 18). The control stage (12) is embodied so as to control only a single substantially passive state of the bridge amplifier (14), as a result of which relatively small switching losses occur.

Abstract: A method and apparatus for RF amplification of a transmit signal within a wireless phone. The amplifier chain is composed of three parts, a pre-driver, a bypassable driver amp, and a power amp. The configuration of the amplifier chain is adjusted in real time to optimize power consumption for a given output power requirement. At low output power levels the driver amp is bypassed and the power amp is provided a low bias current. At medium output power levels the driver amp is bypassed and the power amp is biased at a moderate current. When high output power is required the driver amp is utilized and the power amp is provided a high bias current. The driver amp is shut down when in the bypassed state. The result of implementing this amplifier configuration is an increase in the efficiency of the transmit amplifier. The increase in amplifier efficiency results in increased talk times for battery powered wireless phones.

Abstract: A power amplifier including: a first amplifier PA2 having an input terminal and an output terminal; a passive circuit PC3 having an input terminal and an output terminal; and a first switch SW2 having a single-pole terminal and two multi-throw terminals, one of the multi-throw terminals of the first switch SW2 being connected to the input terminal of the first amplifier PA2 and the other of the multi-throw terminals of the first switch SW2 being connected to the input terminal of the passive circuit PC3. This makes it possible to provide a power amplifier and a communication unit which can be operated with different frequencies, output powers or modulation types.

Abstract: A power amplifier including: a first amplifier PA2 having an input terminal and an output terminal; a passive circuit PC3 having an input terminal and an output terminal; and a first switch SW2 having a single-pole terminal and two multi-throw terminals, one of the multi-throw terminals of the first switch SW2 being connected to the input terminal of the first amplifier PA2 and the other of the multi-throw terminals of the first switch SW2 being connected to the input terminal of the passive circuit PC3. This makes it possible to provide a power amplifier and a communication unit which can be operated with different frequencies, output powers or modulation types.

Abstract: The present invention relates to a method and to a signal predistorter circuit for eliminiating the nonlinearities in the input/output characteristics of nonlinear stages, in particular for eliminating the third-order nonlinearities. More particularly, it relates to a method and to a predistorter circuit for external optical modulators of television signals. The method for predistortion of a signal of variable amplitude comprises the phases of: delivering the said signal to at least one first distorter circuit; biasing the said at least one first distorter circuit; distorting the said signal in the said at least one first distorter circuit; characterized in that the said phase of biasing the said at least one first distorter circuit comprises the phase of maintaining a substantially constant preset voltage value on varying the amplitude of the said signal at the said at least one first distorter circuit.

Abstract: A phase correction amplifier according to the present invention includes; a GaAs field effect transistor; and a Si field effect transistor or a Si bipolar transistor; wherein the GaAs field effect transistor and the Si field effect transistor or the Si bipolar transistor are cascade-connected each other through a variable attenuator.

Abstract: A LINC amplifier of a radio frequency transmitter provides substantially linear amplification from two nonlinear amplifiers by decomposing the original signal into two constant amplitude envelope, phase varying signals, which, when combined, constructively and destructively interfere to re-form the original signal. The output of the LINC amplifier, which is to be transmitted via an antenna, is an amplified form of the original signal. The LINC amplifier uses a digital control mechanism to control and adapt a digital compensation network that directly compensates for the imperfections of the analog RF environment, including the amplifiers. The mechanism monitors the combined amplifier output and adjusts the signal components in order to precisely compensate for any differences in the characteristics of the separate signal paths which would cause the combination not to accurately represent the original signal.

Abstract: In cases where a direct-current offset occurs in a differential signal output from a differential signal amplifier when a differential input signal is differentially amplified in a series of differential signal amplifiers, a direct-current offset component amplified is included in a differential signal output from a particular differential signal amplifier. To suppress the direct-current offset component, the differential signal is, at first, differentially amplified in a pair of transistors of a detecting amplifier, the direct-current offset component is extracted in a low-pass filter from the differential signal amplified, and compensating currents produced according to the direct-current offset component are input to a differential signal amplifier preceding to the particular differential signal amplifier to adjust the direct-current offset component of the differential signal to zero.

Abstract: A bias network uses resistive biasing, active biasing and current mirror biasing in combination to enhance RF power amplifier linearity and efficiency by forming a bias network that provides temperature compensation, minimizes current drain requirements for the Vbias source and reduces the level of RF linear amplifier quiescent current.

Abstract: Realizing a stabilized gain slope without increasing circuit scale or entailing extra time or care for correcting impedance. A resonant circuit that is made up of a capacitor and an inductor is provided in an output stage outside a feedback loop for realizing peaking at a particular frequency and for realizing a gain slope having a desired slope of, for example, 1 dB or more.

Abstract: A digital phase locked loop includes a digital phase detector which provides a magnitude control signal to adjust the step size of up and down adjustments in the phase/frequency of a digitally controlled oscillator, resulting in shorter lock-in or acquisition time and smaller jitter as compared to conventional digital phase locked loop devices. In the disclosed embodiments, the digital phase detector includes multiple bit shift registers in both the up and down directions to count or measure a number of up or down minimum width pulses and provide a pulse magnitude control based on the value of the shift registers to the digitally controlled oscillator. The digitally controlled oscillator includes a charge pump and voltage controlled oscillator. In one embodiment, the charge pump provides programmable control over its output current pulses to a capacitor which controls the output frequency of the voltage controlled oscillator.

Abstract: A phase locked loop (PLL) circuit is provided having: (1) a phase detector coupled to a reference clock signal and a feedback signal for generating positive and negative phase detection signals corresponding to the phase difference between the reference clock signal and the feedback signal; (2) an integrator coupled to the positive and negative phase detection signals for generating an output voltage proportional to the pulse width of either the positive or negative phase detection signals, the integrator including an operational amplifier having positive and negative inputs; (3) a voltage controlled oscillator coupled to the output voltage of the integrator for generating a local oscillator signal with an oscillation frequency proportional to the output voltage of the integrator; (4) a feedback circuit coupled to the local oscillator signal for generating the feedback signal; and (5) an analog holdover circuit for generating an input to the integrator when the phase detector stops receiving the reference clo

Abstract: The present invention is concerned with a PLL comprising the phase comparator 20, loop filter 21, VCO 14 and loop counter 22, wherein there are further provided a prediction window circuit 23 for outputting HWIN (prediction window signal) for predicting the point at which the REF (reference signal) is generated, an omission compensation circuit 24 for detecting the omission of the REF at the time when HWIN is outputted and outputting d.VARX (the second correction signal) to offset the phase difference between d.REFX (the first correction signal) and the VAR (comparison signal) so that the phase comparator 20 outputs the signals Ph1 and Ph2 corresponding to the phase difference between the VAR and the d.REFX and the signals Ph1 and Ph2 corresponding to the phase difference between d.REFC and d.VARX when the omission of the REF has occurred, thereby enabling proper compensation for omission to be made and stable CLK (clock) to be generated even when VCO 14 having a very wide frequency variation range is used.