Patents Issued in November 6, 2001
  • Patent number: 6313458
    Abstract: A photoreceiver circuit includes (a) a photoelectric conversion element for converting incident light to a current, (b) an analog voltage amplifier circuit for amplifying a voltage corresponding to the current of the photoelectric conversion element and for producing an amplified voltage as an output of the photoreceiver circuit, and (c) an analog multiplier circuit for multiplying the amplified voltage produced by the voltage amplifier circuit by an adjusting voltage and for producing an output current with a component proportional to a product of the amplified voltage and the adjusting voltage. The output current of the analog multiplier circuit is supplied to the photoelectric converter element, thereby forming a feedback path of the voltage amplifier circuit. A voltage-lowering part and a current-leaking part may be additionally provided.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: November 6, 2001
    Assignee: NEC Corporation
    Inventor: Fuyuki Okamoto
  • Patent number: 6313459
    Abstract: The present invention comprises an operational algorithm, and calibration process, for an avalanche photodiode (ADP) receiver which takes into account an APD behavioral model. In-situ optical and electrical measurements (calibration) of the APD are performed to determine key constants for use in the model. Knowledge of these constants allows for optimum operation of the APD over a wide range of input optical power. The operational algorithm also gives an estimate of input optical power over a wide range of ambient temperatures.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: November 6, 2001
    Assignee: Nortel Networks Limited
    Inventors: Ronald D. Hoffe, Collin G. Kelly, Marc A. Nadeau, Ping W. Wan, Ashley A. Truscott
  • Patent number: 6313460
    Abstract: An optical device for quantitative detection of linear or rotary movements, in which light beams from two light emitters pass through a grid disk which images the movement and has translucent areas and opaque areas. A single photo receiver is also provided in which the transmitted light strikes the photo receiver. The light emitters are actuated in a pulsed mode. The pulses are separated from one another in an evaluation circuit that is coupled to the photo receiver.
    Type: Grant
    Filed: September 21, 1999
    Date of Patent: November 6, 2001
    Assignee: Siemens Aktiengesellschaft
    Inventors: Heinz Haas, Martin Haushalter, Frank Möllmer
  • Patent number: 6313461
    Abstract: A scanning-aperture electron microscope system and method in which a radiation source generates a radiation beam that is incident upon a surface of a sample material causing electrons to be ejected from the surface. When magnetic imaging is being performed, a polarization rotator polarization-modulates the radiation beam. A scanning-aperture probe having an aperture is positioned in proxiity to the surface of the sample material so that photoelectrons ejected from the surface of the sample material pass through the aperture. A detector detects the electrons passing through the aperture. The electron detector outputs a signal in response to the detected electrons that is used for imaging magnetic and/or spectroscopic features of the surface of the sample material. The resolution of the imaged features is about equal to a size of the aperture.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: November 6, 2001
    Assignee: International Business Machines Corp.
    Inventors: Gary Miles McClelland, Charles Thomas Rettner, Mahesh Govind Samant, Dieter Klaus Weller
  • Patent number: 6313462
    Abstract: In an infrared-rays detector, a pyroelectric element detects existence or movement of a human body, and the output signal of the pyroelectric element is converted to a voltage signal. Then, the voltage signal is subjected to waveform analysis. Then, a detection signal is outputted only when a waveform generated by a human body is detected by the waveform analysis. For example, the voltage signal is amplified at two different frequency ranges, and the amplified signals are used for discriminating a signal due to a human body. Then, a noise such as a popcorn noise of the pyroelectric element is prevented to be detected erroneously as generated by a human body.
    Type: Grant
    Filed: February 25, 1999
    Date of Patent: November 6, 2001
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Hiroshi Matsuda, Yuji Takada, Teruki Hatatani
  • Patent number: 6313463
    Abstract: A high performance microbolometer in which a pixel contains the material VOx wherein x of VOx is set at a value to adjust a thermal coefficient of resistance to a selected value between 0.005 and 0.05.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: November 6, 2001
    Assignee: Honeywell International Inc.
    Inventors: Barrett E. Cole, Christopher J. Zins
  • Patent number: 6313464
    Abstract: A portable, infrared, multiple gas analyzer for measuring the concentration of a plurality of infrared absorbent gases with a simple optical arrangement for transmitting an infrared beam along an optical path along with gas mixtures to be analyzed. Light transmitting tubes arranged in a U-like configuration transmit infrared energy and the gases applied thereto over a small path to an infrared detector from an infrared source and provide electrical analog output signals representative of the detected gases. The detector output signals are processed by D.C. processing circuits including an analog to digital converter and microprocessing circuits for providing digital, binary coded, output signals representative of the detected gas concentration of the infrared absorbent gases. The analyzer can be readily calibrated by applying a non-infrared absorbent gas to the gas analyzer to provide a maximum output signal level with the infrared beam on and the background level or dark level signal with the beam off.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: November 6, 2001
    Inventor: Robert J. Schrader
  • Patent number: 6313465
    Abstract: A radiation discriminative measurement is performed by using a radiation discriminative measuring apparatus which comprises a radiation source for radiating radiations, first, second and third scintillators disposed in a region which is irradiated with the radiations radiated from the radiation source, and an image pickup means to deal with the light beams emitted from the first, second and third scintillators and the discrimination measurement includes the steps of arranging the first, second and third scintillators in a region which is irradiated with the radiations radiated from the radiation source, causing the first scintillator to respond to type A, type B and type C radiations radiated from the radiation source and to emit alight beam in a first wavelength region, causing the second scintillator to respond to type B and type C radiations which pass through the first scintillator so as to to emit a light beam in a second wavelength region, and causing the third scintillator to respond to a type C radiat
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: November 6, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Nittoh, Takeshi Takahara, Yukihiro Fukuta, Chikara Konagai
  • Patent number: 6313466
    Abstract: In a method for determining the nitrogen concentration in a film of nitrided oxide material formed over a semiconductor wafer during fabrication of a semiconductor device an optical property of the film of nitrided oxide material is determined. The determined optical property is used to determine the nitrogen concentration in the film of nitrided oxide material. In one embodiment the optical property, e.g., extinction coefficient, k, is correlated to the nitrogen concentration measured by secondary ion mass spectroscopy. In a method of making a semiconductor device a film of nitrided oxide material is formed over a plurality of semiconductor wafers in a fab. The nitrogen concentration in the film of nitrided oxide material is monitored by periodically subjecting one of the wafers to an in-line test in the fab.
    Type: Grant
    Filed: May 12, 1999
    Date of Patent: November 6, 2001
    Assignee: Philips Electronics North America Corp.
    Inventors: Christopher S. Olsen, Subhas Bothra
  • Patent number: 6313467
    Abstract: An ultraviolet (UV) catadioptric imaging system, with broad spectrum correction of primary and residual, longitudinal and lateral, chromatic aberrations for wavelengths extending into the deep UV (as short as about 0.16 &mgr;m), comprises a focusing lens group with multiple lens elements that provide high levels of correction of both image aberrations and chromatic variation of aberrations over a selected wavelength band, a field lens group formed from lens elements with at least two different refractive materials, such as silica and a fluoride glass, and a catadioptric group including a concave reflective surface providing most of the focusing power of the system and a thick lens providing primary color correction in combination with the focusing lens group. The field lens group is located near the intermediate image provided by the focusing lens group and functions to correct the residual chromatic aberrations. The system is characterized by a high numerical aperture (typ. greater than 0.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: November 6, 2001
    Assignee: KLA-Tencor, Inc.
    Inventors: David R. Shafer, Yung-Ho Chuang, Bin-Ming B. Tsai
  • Patent number: 6313468
    Abstract: A device for determining the level of UV-transmission through a flowing media This UV-transmission is determined by measuring and evaluating the radiation intensity of a UV-radiation source radiating through a zone of the medium. The emitting surface of the UV-radiation source partly extends into the flowing medium and partly into a reference space, or borders on the medium and the space. Two UV-sensors are directed at zones of equal irradiation intensity of the radiation source emitting surface. In this case, the one UV-sensor is arranged in the flowing medium and the other UV-sensor in the reference space. Both UV-sensors are connected to a measuring and evaluating circuit, which compares and evaluates the signals of the UV-sensors.
    Type: Grant
    Filed: March 4, 1999
    Date of Patent: November 6, 2001
    Assignee: Wedeco AG Water Technology
    Inventor: Horst Wedekamp
  • Patent number: 6313469
    Abstract: An ion implantation apparatus has a vacuum chamber, a beam exposure region defined in an end of the vacuum chamber, and a pair of substrate holding robots disposed one on each side of the beam exposure region, each for holding a semiconductor wafer to allow the semiconductor wafer to be exposed to a beam in the beam exposure region. A pair of load-lock chambers is disposed in an opposite end of the vacuum chamber in confrontation with the substrate holding robots, respectively. A pair of feed robots is disposed between the load-lock chambers and the substrate holding robots, respectively. The vacuum chamber houses a relay table disposed between the feed robots, for relaying a semiconductor wafer.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: November 6, 2001
    Assignee: Ebara Corporation
    Inventor: Tadamoto Tamai
  • Patent number: 6313470
    Abstract: There are described apparatus and methods wherein ultraviolet light kills and/or degrades and vaporizes microorganisms and organic material which naturally form over time on a heat exchanger. As this matter is eliminated, the pressure drop is decreased (i.e., airflow is increased) and the heat exchange efficiency (capacity) is increased. Less energy per Btu removed is used by the cooling system, and less energy is used by the HVAC system to move air.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: November 6, 2001
    Assignee: Steril-Aire, U.S.A. Inc.
    Inventors: Forrest B. Fencl, Robert Scheir
  • Patent number: 6313471
    Abstract: A method and apparatus for determining the fluorescence, luminescence, or absorption of a sample is provided. The sample may either be contained within a cuvette or within one or more sample wells within a multi-assay plate. A combination of a broadband source, a monochromator, and a series of optical filters are used to tune the excitation wavelength to a predetermined value within a relatively wide wavelength band. A similar optical configuration is used to tune the detection wavelength. In one aspect, multiple optical fibers are coupled to the excitation source subassembly, thus allowing the system to be quickly converted from one optical configuration to another. In another aspect, the excitation light and the detected sample emissions pass to and from an optical head assembly via a pair of optical fibers. The optical head assembly is scanned across one axis of the sample multi-assy plate.
    Type: Grant
    Filed: March 23, 1999
    Date of Patent: November 6, 2001
    Assignee: Molecular Devices Corporation
    Inventors: Robert Giebeler, David G. Ogle, Roger Kaye
  • Patent number: 6313472
    Abstract: A radiation image information reading apparatus has a main assembly which incorporates an exposure unit, an image information reading unit, an erasing unit, and a circulatory feed system. The image information reading unit has an auxiliary scanning feed mechanism for feeding a stimulable phosphor sheet vertically in an auxiliary scanning direction, and a laser beam applying mechanism for applying a laser beam substantially horizontally to the stimulable phosphor sheet which is being fed in the auxiliary scanning direction and scanning the stimulable phosphor sheet with the laser beam in a main scanning direction. The radiation image information reading apparatus is relatively simple in structure and small in size.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: November 6, 2001
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Masakazu Nakajo
  • Patent number: 6313473
    Abstract: A device for producing apodized gratings on a stationary optical fiber. The device includes a slit-generating means, a stationary phase mask and a stationary writing-beam-generating means. A slit is generated by the slit-generating means. A writing beam is generated by the stationary writing-beam-generating means to pass through the slit and the stationary phase mask and then focus on the stationary optical fiber for a plurality of exposure time periods. The slit is adjustable in width so that the slit has a plurality of widths during the plurality of exposure time periods, respectively.
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: November 6, 2001
    Assignee: :Uconn Technology Inc.
    Inventors: Samuel I-En Lin, Win-Yann Jang, Iying Wu
  • Patent number: 6313474
    Abstract: Current density distributions of the ion beam in the scanning direction (the direction of X) at two points Zf and Zb on Z-coordinate are respectively measured by Faraday arrays. Using the thus measured current density distributions, a current density distribution in the scanning direction of the ion beam at an arbitrary position on Z-coordinate located in a workpiece is found by the method of interpolation. Using the thus found current density distribution, a waveform of scanning voltage V(t) of the ion beam is reformed so that a scanning speed of the ion beam can be relatively decreased at a position where the current density must be raised in the current density distribution and a scanning speed of the ion beam can be relatively increased at a position where the current density must be lowered. Due to the foregoing, a current density distribution in the scanning direction of the ion beam at an arbitrary position on Z-coordinate located in the workpiece is adjusted to a desired distribution.
    Type: Grant
    Filed: July 21, 1999
    Date of Patent: November 6, 2001
    Assignee: Nissin Electric Co., LTD
    Inventors: Koji Iwasawa, Nobuo Nagai
  • Patent number: 6313475
    Abstract: An ion beam generator includes an ion beam source for generating an ion beam, an acceleration/deceleration column for selectably accelerating or decelerating ions in the ion beam to desired energies, a source filter positioned between the ion beam source and the acceleration/deceleration column for removing first undesired species from the ion beam, and a mass analyzer positioned downstream of the acceleration/deceleration column for removing second undesired species from the ion beam. The ion beam generator supplies an energetic ion beam having a low level of energy and mass contaminants. The ion beam generator may be utilized in an ion implanter.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: November 6, 2001
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Anthony Renau, Charles McKenna
  • Patent number: 6313476
    Abstract: A charged beam lithography system includes a charged particle gun for generating charged beams, a main deflecting system and a sub-deflecting system for deflecting the charged beams generated by the charged particle gun, and a control computer. The charged beam lithography system is designed to cause the surface of a substrate to be irradiated with the charged beams from the charged particle gun while continuously moving a stage, to write a desired pattern for each of stripes defined by the maximum deflection widths of the main deflecting system and the sub-deflecting system. The charged beam lithography system further comprises: a real time proximity effect correcting circuit for calculating an optimum dosage for each of the stripes by correcting the dosage of the electron beams in view of the influence of the proximity effect; and a cash memory for storing the optimum dosage data for at least two of the stripes.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: November 6, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuko Shimizu, Takayuki Abe, Hirohito Anze, Susumu Oogi, Takashi Kamikubo, Eiji Murakami, Yoshiaki Hattori, Tomohiro Iijima, Hitoshi Higurashi, Kazuto Matsuki
  • Patent number: 6313477
    Abstract: In a two-side radiation image reading method wherein a stimulable phosphor sheet storing a radiation image is scanned by stimulating rays and light emitted from the front and back sides of the sheet is photoelectrically detected by photoelectric reading means separately located on the front and back sides of the sheet to obtain two image signals representing the radiation image to be subjected to addition processing or the like for obtaining a final image, shading correction data and/or fading correction data are obtained in advance and shading correction and/or fading correction is carried out on the image signals by using the correction data having been obtained. While an area equivalent to one side of the stimulable phosphor sheet (whose number of main scan lines is 4320) is being scanned, reading of the sheet is switched between the front and back sides and sensitivity of photoelectric reading means is also changed (to standard, semi-high, and high).
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: November 6, 2001
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Hiroaki Yasuda, Naoto Iwakiri
  • Patent number: 6313478
    Abstract: There is provided a single electron device. The device has weak links with bottle-neck figure in place of the tunnel junction of the prior device. The weak links are easily formed on the same substrate by simple processes and thus the integration of the single electron device can be easily achieved.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: November 6, 2001
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seongjae Lee, Kyoungwan Park, Mincheol Shin
  • Patent number: 6313479
    Abstract: Systems and methods are described for fabricating arrays of quantum dots. A method for making a quantum dot device, includes: forming clusters of atoms on a substrate; and charging the clusters of atoms such that the clusters of atoms repel one another. The systems and methods provide advantages because the quantum dots can be ordered with regard to spacing and/or size.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: November 6, 2001
    Inventors: Zhenyu Zhang, John F. Wendelken, Ming-Che Chang, Woei Wu Pai
  • Patent number: 6313480
    Abstract: The structure allows checking an integrated electronic device comprising an oxide layer to be measured located above a doped pocket of a wafer of doped semiconductor material and arranged adjacent to a gate region of polycrystalline semiconductor material. The structure is formed at a suitable point of the wafer and comprises an oxide test region of the same material, having the same thickness and the same electrical characteristics as the oxide layer to be measured and a polycrystalline region of the same material, having the same thickness and the same electrical characteristics as the gate region. The polycrystalline region extends preferably along the perimeter of a square and delimits laterally the oxide test region, the area of which is greater than the area of the oxide layer to be measured so as to allow non-destructive testing, on-line, of the oxide layer to be measured during an early stage of the manufacturing process.
    Type: Grant
    Filed: December 9, 1998
    Date of Patent: November 6, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Nicola Zatelli, Carlo Cremonesi
  • Patent number: 6313481
    Abstract: In a liquid crystal display device, an improved storage capacitance that uses a pair of transparent conductive films for electrodes is provided. On a flattening film made of a resin, a first transparent conductive film and an insulating film for capacitance are formed into a lamination to form in this laminated film an opening portion. An insulating film covering near the opening portion is formed. A transparent conductive film is formed and patterned to form a pixel electrode. Thus is formed a storage capacitance having the structure where the insulating film for capacitance is sandwiched between the first transparent conductive film and the pixel electrode.
    Type: Grant
    Filed: July 19, 1999
    Date of Patent: November 6, 2001
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Hisashi Ohtani, Misako Nakazawa
  • Patent number: 6313482
    Abstract: Silicon carbide power devices having trench-based charge coupling regions include a silicon carbide substrate having a silicon carbide drift region of first conductivity type (e.g., N-type) and a trench therein at a first face thereof. A uniformly doped silicon carbide charge coupling region of second conductivity type (e.g., an in-situ doped epitaxial P-type region) is also provided in the trench. This charge coupling region forms a P-N rectifying junction with the drift region that extends along a sidewall of the trench. The drift region and charge coupling region are both uniformly doped at equivalent and relatively high net majority carrier doping concentrations (e.g., 1×1017 cm−3) so that both the drift region and charge coupling region can be depleted substantially uniformly when blocking reverse voltages.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: November 6, 2001
    Assignee: North Carolina State University
    Inventor: Bantval Jayant Baliga
  • Patent number: 6313483
    Abstract: A light-emitting semiconductor device has a semi-insulating semiconductor surface layer overlying a conductive semiconductor layer of a first conductive type. A diffusion region of a second conductive type extends through the semi-insulating semiconductor surface layer and ends in the conductive semiconductor layer. Positive and negative electrode contacts are provided on the upper surface of the device. Nonradiative recombination near the surface of the device is reduced because there is no pn junction in the semi-insulating semiconductor surface layer, and the device structure is suitable for matrix driving.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: November 6, 2001
    Assignee: Oki Data Communication
    Inventors: Mitsuhiko Ogihara, Hiroshi Hamano, Masumi Taninaka
  • Patent number: 6313484
    Abstract: A circuit-integrated light-receiving device of the present invention includes: a semiconductor substrate of a first conductivity type; a first semiconductor crystal growth layer of the first conductivity type provided on a surface of the semiconductor substrate, wherein the first semiconductor crystal growth layer includes a first portion whose impurity concentration gradually decreases in a direction away from the surface of the semiconductor substrate and a second portion located in a first region above the first portion whose impurity concentration distribution is uniform in a depth direction; a buried diffusion layer of the first conductivity type located in a second region which is above the first portion of the first semiconductor crystal growth layer and does not overlap the first region; a second semiconductor crystal growth layer of a second conductivity type which is provided across a surface of the first semiconductor crystal growth layer and a surface of the buried diffusion layer; and a separatio
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: November 6, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Isamu Ohkubo, Masaru Kubo, Naoki Fukunaga, Takahiro Takimoto, Mutsumi Oka, Toshimitsu Kasamatsu
  • Patent number: 6313485
    Abstract: A gate-controlled thyristor in which an IGBT in a first cell and a thyristor in a main cell are connected together in ouch a way that the first cell and the main cell form a lateral FET with a channel of a first conducting type. In an emitter zone of the thyristor, there is a layer embedded that increases the charge carrier recombination in order to reduce the start-up resistance of the gate-controlled thyristor. Trenches, filled with insulated gate electrodes, can be introduced into the lateral FET, so that the FET is a side wall FET.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: November 6, 2001
    Assignee: Infineon Technologies AG
    Inventor: Jenoe Tihanyi
  • Patent number: 6313486
    Abstract: A field effect transistor such as a flash EEPROM device has channel region between a source region and a drain region with the channel region including a silicon germanium alloy layer epitaxially grown on a silicon substrate and a silicon cap layer epitaxially grown on the alloy layer. A floating gate is provided over and insulated from the channel region, and a control gate is provided over and insulated from the floating gate. The silicon germanium alloy layer and cap silicon layer provide for enhanced secondary impact ionization when injecting electrons from the channel region into the floating gate in programming the device. In a preferred embodiment the SiGe alloy layer is graded with the germanium mole fraction increasing from zero to some maximum value in the growth direction and with the germanium layer thickness being below a critical thickness for maintaining pseudomorphic strain.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: November 6, 2001
    Assignee: Board of Regents, The University of Texas System
    Inventors: David L. Kencke, Sanjay K. Banerjee
  • Patent number: 6313487
    Abstract: A vertical channel flash memory cell with a silicon germanium layer in the channel region provides enhanced secondary electron injection when programming the device. The device includes a silicon substrate, a silicon germanium alloy layer epitaxially grown on the substrate, and a silicon layer epitaxially grown on the silicon germanium layer. A sidewall through the stacked structure is formed by etching thereby exposing edges of the silicon layer and the silicon germanium layer and a portion of the substrate. A floating gate is formed overlying the sidewall and insulated therefrom with a control gate overlying the floating gate and insulated therefrom. A source region is formed in the silicon layer and a drain region is formed in the substrate with a channel therebetween along the sidewall and including the silicon germanium layer. The silicon germanium layer is preferably compressively strained and can have a uniform mole fraction or a graded mole fraction.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: November 6, 2001
    Assignee: Board of Regents, The University of Texas System
    Inventors: David L. Kencke, Sanjay K. Banerjee
  • Patent number: 6313488
    Abstract: A bipolar transistor having at least a low doped drift layer (14) of crystalline SiC comprises at least one first layer (13) of a semi-conductor material having a wider energy gap between the conduction band and the valence band than an adjacent layer (14) of SiC.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: November 6, 2001
    Assignee: ABB Research Limited
    Inventors: Mietek Bakowski, Bo Breitholtz, Ulf Gustafsson, Lennart Zdansky
  • Patent number: 6313489
    Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral transistor device in an SOI layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region and forms a lightly-doped drain region, and a drain contact region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being at least substantially insulated from the body region and drift region by a surface insulation region.
    Type: Grant
    Filed: November 16, 1999
    Date of Patent: November 6, 2001
    Assignee: Philips Electronics North America Corporation
    Inventors: Theodore Letavic, Mark Simpson, Richard Egloff, Andrew Mark Warwick
  • Patent number: 6313490
    Abstract: A SRAM memory cell including an access device formed on a storage device is described. The storage device has at least two stable states that may be used to store information. In operation, the access device is switched ON to allow a signal representing data to be coupled to the storage device. The storage device switches to a state representative of the signal and maintains this state after the access device is switched OFF. When the access device is switched ON, the state of the storage device may be sensed to read the data stored in the storage device. The memory cell may be formed to be unusually compact and has a reduced power supply requirements compared to conventional SRAM memory cells. As a result, a compact and robust SRAM having reduced standby power requirements is realized.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: November 6, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Wendell P. Noble
  • Patent number: 6313491
    Abstract: An upper electrode of an FRAM capacitor is connected to a diffusion layer on the surface of a semiconductor substrate via a contact hole, second interconnecting layer, contact hole, first interconnecting layer, and contact hole. The first interconnecting layer is formed at substantially the same level as the FRAM capacitor. This decreases the depth of the contact hole connecting the first interconnecting layer to the surface of the semiconductor substrate and thereby decreases the aspect ratio of this contact hole. This facilitates processing and filling this contact hole and allows micropatterning.
    Type: Grant
    Filed: July 15, 1999
    Date of Patent: November 6, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Susumu Shuto
  • Patent number: 6313492
    Abstract: A photoresist composition is disclosed having both negative tone and positive tone responses, giving rise to spaces being formed in the areas of diffraction which are exposed to intermediate amounts of radiation energy. This resist material may be used to print doughnut shapes or may be subjected to a second masking step, to print lines. Additionally, larger and smaller features may be obtained using a gray-scale filter in the reticle, to create larger areas of intermediate exposure areas.
    Type: Grant
    Filed: July 6, 1998
    Date of Patent: November 6, 2001
    Assignee: International Business Machines Corporation
    Inventors: Mark C. Hakey, Steven J. Holmes, David V. Horak, Ahmad D. Katnani, Niranjan M. Patel, Paul A. Rabidoux
  • Patent number: 6313493
    Abstract: The semiconductor device of the invention includes a plurality of circuit blocks including a first circuit block and a second circuit block, a block parameter of the first circuit block being different from a block parameter of the second circuit block. In the semiconductor device, the first circuit block is formed on a first semiconductor chip, and the second circuit block is formed on a second semiconductor chip and is electrically connected with the first circuit block.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: November 6, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiki Mori, Ichiro Nakao, Tsutomu Fujita, Reiji Segawa
  • Patent number: 6313494
    Abstract: A semiconductor device, having a contact pad grown by an anisotropical silicon selective growth technique, includes a first word line crossing a diffusion layer formed on a substrate and surrounded by an element separating region at a right angle, a second word line parallel with the first word line formed over a rounded corner of the diffusion layer, and an area of the diffusion layer rectangularly partitioned by the first and second word lines. So that anisotropical silicon selective epitaxial growth from this area of the diffusion layer is achieved, avoiding isotropical growth deteriorated by the rounded corner.
    Type: Grant
    Filed: December 2, 1998
    Date of Patent: November 6, 2001
    Assignee: NEC Corporation
    Inventor: Hiroki Koga
  • Patent number: 6313495
    Abstract: The present invention includes a method of improving conductivity between an electrode and a plug in a stacked capacitor where an oxide has formed therebetween. The method includes the steps of bombarding the oxide with ions and mixing the oxide with materials of the electrode and the plug to increase a conductivity between the electrode and the plug. A method of forming a diffusion barrier within an electrode in a stacked capacitor includes the steps of providing a stacked capacitor having a plug coupled to an electrode and bombarding the electrode with ions to form the diffusion barrier within the electrode such that the diffusion barrier is electrically conductive. A stacked capacitor in accordance with the present invention includes an electrode, a plug for electrically accessing a storage node, the plug being coupled to the electrode and a barrier layer disposed within the electrode for preventing diffusion of materials which reduce conductivity between the electrode and the plug.
    Type: Grant
    Filed: January 6, 2000
    Date of Patent: November 6, 2001
    Assignee: Siemens Aktiengesellschaft
    Inventors: Hua Shen, Joachim Hoepfner
  • Patent number: 6313496
    Abstract: The invention comprises capacitors and methods of forming capacitors. In one implementation, a method of forming a capacitor includes forming a first capacitor electrode. An Si3N4 comprising capacitor dielectric layer is formed over the first capacitor electrode. The Si3N4 comprising layer is oxidized in the presence of a chlorine containing atmosphere under conditions which form a silicon oxynitride layer comprising chlorine atop the Si3N4 layer. In one aspect, the oxidizing sequentially comprises a dry oxidation in the presence of an oxygen containing gas in the substantial absence of chlorine, a dry oxidation in the presence of a gas comprising oxygen and chlorine, and a wet oxidation comprising chlorine. A second capacitor electrode is formed over the chlorine containing silicon oxynitride layer. In one implementation, a method of forming a capacitor comprises forming a first capacitor electrode.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: November 6, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Todd E. Smith
  • Patent number: 6313497
    Abstract: A semiconductor device has such a configuration that a contact hole is formed in a fourth inter-layer insulator film which covers an upper electrode of a capacitor, to expose part of the upper electrode; and below the contact hole, a trench covered by a capacitive insulator film formed in a trench is formed larger than the contact hole in width, to have therein a polycrystalline silicon film which constitutes the upper electrode.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: November 6, 2001
    Assignee: NEC Corporation
    Inventor: Shinya Iwasa
  • Patent number: 6313498
    Abstract: Nonvolatile memory cell and process in which a thin floating gate is formed with a rounded lateral edge and a thickness on the order of 100-1000 Å over a gate oxide in an active area on a silicon substrate. A tunnel oxide is formed adjacent to the rounded edge of the floating gate, and a control gate is formed with a lower portion next to the tunnel oxide and an upper portion overlying the floating gate. In some disclosed embodiments, the upper portion of the control gate completely overlies the floating gate, and in others it only partially overlies it.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: November 6, 2001
    Assignee: Actrans System Inc.
    Inventor: Chiou-Feng Chen
  • Patent number: 6313500
    Abstract: A split gate memory cell is described which is fabricated from two-polysilicon layers and comprises a silicon substrate having a source and a drain electrode and a storage node, a tunnel oxide on the substrate, a first control gate electrode and a floating gate electrode spaced from each other and fabricated from the same polysilicon layer and a second control gate electrode of a second poly material formed between and over the first control gate and floating gate and isolated therefrom by a dielectric layer therebetween.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: November 6, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Patrick J. Kelley, Chung Wai Leung, Ranbir Singh
  • Patent number: 6313501
    Abstract: Nonvolatile memory, cell array thereof, and method for sensing a data therefrom, the method including the steps of: selecting a flash memory cell having a first floating gate and a second floating gate, a first control gate and a second control gate, and a drain and a source; flowing a current through a first channel under the first floating gate and detecting a current flow through a second channel under the second floating gate, thereby sensing a color state of the second floating gate; flowing a current through the second channel and conducting level writings on the first floating gate, thereby forming different threshold voltages; measuring a cell current of the first channel under the first floating gate; comparing the measured cell current to a reference current, thereby sensing a level state of the first floating gate; and sensing information bits stored in the flash memory cell according to a color state of the second floating gate and a level state of the first floating gate.
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: November 6, 2001
    Assignee: Hyundai Electronic Industries Co., Ltd.
    Inventor: Wook Hyun Kwon
  • Patent number: 6313502
    Abstract: The invention proposes a simple method to lower the threshold voltage of UV erased EPROM and OTP memories. During the erasure, a voltage is applied to the control gate (10) or wordline (2) which is on-chip generated as a photovoltage by means of photodiode (12) irradiated by radiation (15) during erasure. Because the wordlines are coupled to further zones forming photosensitive pn-junctions in the semiconductor body, measures are taken to prevent that, due to charge transport across said junctions, the generated photovoltage is decreased too strongly.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: November 6, 2001
    Assignee: U.S. Philips Corporation
    Inventor: Franciscus P. Widdershoven
  • Patent number: 6313503
    Abstract: A metal nitride oxide semiconductor (MNOS) type memory using a threshold voltage variation (&Dgr;Vth) due to charging of a single electron when the width of a channel of the memory is set to be smaller than or equal to the Debye screen length (LD) of an electron, and a driving method thereof, are provided. The MNOS memory uses a threshold voltage variation (&Dgr;Vth) due to charging of a single electron occurring when the width of a channel is set to be smaller than or equal to the Debye screen length (LD) which depends on the impurity concentration of a semiconductor substrate.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: November 6, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jo-won Lee, Moon-kyung Kim, Byong-man Kim, Seok-yeol Yoon, Hyung-lae Roh
  • Patent number: 6313504
    Abstract: A vertical MOS semiconductor device in accordance with the present invention is provided with a semiconductor base; and a vertical MOS transistor having a well diffusion layer of a conductive type opposite to that of the semiconductor base, and a source diffusion layer of the same conductive type as that of the semiconductor base; wherein a channel length in a horizontal direction with respect to a main surface of the semiconductor base from a junction of the source diffusion layer to a junction of the well diffusion layer is set such that it is larger than a length at which a punch-through phenomenon takes place between the semiconductor base and the source diffusion layer and at which a minimum resistance value of the well diffusion layer is obtained. This arrangement makes it possible to reduce the size of the entire vertical MOS semiconductor device to 90% as compared with a conventional vertical MOS semiconductor device, without sacrificing a high breakdown voltage characteristic.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: November 6, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Kenichi Furuta, Yutaka Akiyama, Osamu Kawai
  • Patent number: 6313505
    Abstract: A method for making a ULSI MOSFET chip includes forming the gate of a transistor on a silicon substrate, covering the gate with a SiON protective layer, and then implanting a pre-amorphization high dose Si or Ge implant into the substrate. Next, dopant is pre-implanted into the substrate to promote subsequent formation of source and drain extensions, with the SiON layer protecting the gate from the pre-amorphization high dose Si or Ge and from the dopant. Undoped polysilicon and polygermanium is then deposited onto the substrate adjacent the gate at relatively low temperatures (600° C.) to establish elevated source and drain regions without excessively thermally stressing the chip. The SiON layer is removed from the gate, and the gate and elevated source and drain regions are implanted with dopant, followed by rapid thermal annealing to form the source and drain extensions in the substrate below the gate. The gate and elevated source and drain regions are then silicidized.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: November 6, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Bin Yu
  • Patent number: 6313506
    Abstract: The SOI-FET has source and drain zones of one conductivity type arranged on an insulator. A semiconductor zone of another conductivity type (“body”) is arranged between the source and drain zones. A trench is introduced into the semiconductor zone of the other conductivity type. The trench is filled with an electrode material, which is capacitively or directly coupled to the semiconductor zone of the other conductivity type.
    Type: Grant
    Filed: September 21, 1998
    Date of Patent: November 6, 2001
    Assignee: Infineon Technologies AG
    Inventor: Jenoe Tihanyi
  • Patent number: 6313507
    Abstract: The present invention provides an SOI device preventing the floating body effect, and a method for manufacturing the same. Disclosed is a method comprising the steps of: forming an isolation layer on a first silicon substrate; forming a conductive layer on the isolation layer and the first silicon substrate; forming a buried insulating layer on the conductive layer; bonding the second silicon substrate so as to contact with the buried insulating layer; exposing the isolation layer by removing backside of the first silicon substrate by selected thickness thereby defining a semiconductor layer; forming a transistor by forming a gate electrode, a source region and a drain region at selected portions of the semiconductor layer; etching a selected portion of the isolation layer so as to expose the conductive layer; and forming a body electrode to be contacted with the conductive layer within the isolation layer.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: November 6, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Jong-Wook Lee
  • Patent number: 6313508
    Abstract: A transistor of a second conductivity type is of an LMOS structure, and a transistor of a first conductivity type is of an LDMOS structure. The transistor of the first conductivity type has a drain base layer which functions in the same manner as a drain offset diffusion layer and is formed in a substrate separately from a source base diffusion layer. The transistor of the first conductivity type has a stably high breakdown voltage and a low on-state resistance as with the transistor of the second conductivity type.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: November 6, 2001
    Assignee: NEC Corporation
    Inventor: Kenya Kobayashi