Abstract: A ceramic electronic component includes electrodes each having a four layer structure including a first electrode layer made of an Ni—Ti alloy and constructed so as to adhere closely to the surface of a ceramic material defining a ceramic element, a second electrode layer made of at least one selected from the group consisting of Cu, Ag, and Au, disposed on the first electrode layer, a third electrode layer made of an Ni—Ti alloy, disposed on the second electrode layer, and a fourth electrode layer made of at least one selected from the group consisting of Cu, Ag, and Au, disposed on the third electrode layer. Lead terminals are bonded to the electrodes having the four layer structures via solder members, respectively.

Abstract: A predetermined amalgamation of electrodes formed or manufactured at least in part, by predetermined, sequential manufacturing operations into a balanced and shielding electrode structure. The balanced total electrode structure also uses a grouping of identically configured, and balanced positioned, shielding electrodes that are amalgamated in sequential combination with predetermined, complimentary balanced shielded electrodes groupings and other predetermined elements that are together, practicable to provide predetermined multiple energy conditioning functions operable upon portions of propagating energy as well simultaneously being operable to provide a common, voltage reference function operable for at least dynamic circuit operations.

Abstract: An object of the present invention is to provide an antimony-containing niobium sintered body for a capacitor having a small specific leakage current value, an antimony-containing niobium powder for use in the sintered body, and a capacitor using the sintered body. In the present invention, an antimony-containing niobium powder having an antimony content of preferably about 0.1 to about 10 mol % and an average particle size of preferably about 0.2 to about 5 &mgr;m is used. By using this antimony-containing niobium powder, a sintered body and a capacitor are constructed.

Abstract: An aluminum electrolytic capacitor includes a case, a sealant for sealing the case, a separator, a cathode, an anode, and an electrolyte sealed in the case, and an anode lead connected to the anode, wherein the cathode includes an aluminum foil, and a solid compound having a function of keeping the pH of the electrolyte constant further is provided in the case.

Abstract: An adjustable multi-positional display monitor unit for accommodating varied viewing positions. The display unit includes a swivel portion, a pivot portion and a screen. The swivel portion is rotatable relative to a reference surface about a first axis, which extends through the reference surface. The pivot portion has a proximal and distal region, the proximal region pivotally coupled to the swivel portion to accommodate pivot of the pivot portion relative to the swivel portion about a second axis which is normal to the first axis. The distal region is associated with a screen which is rotatable about a third axis which extends though a planar viewing surface of the screen so that the screen can be positioned for viewing from an upright, inverted and recumbent position regardless of the orientation of the reference surface.

Abstract: A portable workstation computer is disclosed. The computer includes a display assembly adapted to be mounted between a frontal concave member and a rearward concave member. A keyboard, mouse, and accessories may be stored in the frontal concave member. Processing, memory, and storage components are housed in the rearward concave member. The display assembly may be interposed between the frontal concave member and the rearward concave member in a briefcase configuration, forming a casing for the computer.

Abstract: An object of the present invention is to provide an information processing equipment which is excellent in the shock resistance, and has a strap and pen storing portion, and has a drip-proof ability.

Abstract: A display connector includes a body having a mounting portion on one surface, a detachably installed display member, a pair of rotation pins in the mounting portion, a pair of rotating fixing brackets for the rotation pins, a locking feature, an unlocking feature, and a rotating light emitter coupled to either of rotation pin with a laser diode array. Each diode in the array independently radiates light according to a driving signal. A light receiving module in the display faces the light emitting module when the display is mounted on the body, and has a photo diode array for receiving the output of the laser diode array. The picture signal is transmitted from the body to the rotatably-connected display using the light.

Abstract: A device for restricting the movement of a printed circuit board to which tactile switches are mounted. The device which prevents a relative movement of the printed circuit board with respect to a bracket to facilitate the installation of the printed circuit board while structuring the securing means for the circuit board so that a force is exerted that counters forces created by the activation of switches directly mounted to the main printed circuit board. The printed circuit board retaining device acts to maintain the printed circuit board in the appropriate location with respect to the supporting bracket while preventing the fracturing of tactile switches when an excess force is applied to the tactile switches.

Abstract: A hand-held, electronic, bi-directional, wireless electronic communication device having a physical configuration which includes a relatively large, constantly visible display and an alphanumeric keyboard that can be concealed until needed.

Abstract: A rack for receiving a memory storage device carrier having a periphery to blow air through the opening. The rack has a backplane, a first lateral rail and a second lateral rail for mounting a memory storage device extending perpendicularly from the backplane. At least one rail has a periphery defining an opening with a fan mounted with respect to the opening to blow air through the opening.

Abstract: A connection component is provided. The connection component includes (1) a first interposer having a first surface to which a microelectronic may be mounted and a second surface opposite from the first surface, (2) a second interposer that is more flexible than the first interposer and that is disposed under the second surface of the rigid interposer, and (3) a plurality of conductive parts that may be positioned in the first and second interposers and that may be exposed at the first surface of the first interposer, a bottom surface of the second interposer, or both the first and bottom surfaces. The electrically conductive parts may include leads. A socket assembly or a microelectronic element such as semiconductor chip may be mounted onto the first surface of the rigid interposer. The connection component may be mounted onto a support substrate.

Abstract: An insulation layer is formed on a ground layer. The insulation layer includes first and second regions for forming wiring layers. The impedance of a wiring layer formed on the second region is lower than that of a wiring layer formed on the first region. A signal line pattern is formed on the wiring layer on the first region of the insulation layer. A power supply plane is formed on the wiring layer on the second region of the insulation layer in order to feed power to the signal line pattern through a termination resistor connected to the signal line pattern.

Abstract: The tuner structure of the present invention includes: a circuit board on which electronic circuit components such as transistors and resistors have been mounted; a chassis angle; and a shield cover. In the tuner structure, a feedthrough capacitor for inputting/outputting a power, a control signal and the like is mounted to a metal plate disposed in parallel to the circuit board.

Abstract: A photosensitive polyimide resin 12 is exposed and developed via a computer-aided designed (CAD) pattern film 14 to form a pattern onto a mold base 11 by means of photoresisit method. A molded pattern 13 is thus formed to construct a mold 10. An optical panel 2 is formed by the use of the mold 10 with an optical pattern 3 comprising circular or rectangular dot holes or dot projections each of which is several &mgr;ms and arranged in high density which is a reversal of the molded pattern 13. The optical pattern 3 performs light guiding or diffusion of incident light in high luminance and with a high degree of uniformity, thereby achieving secondary illumination without having see-through of the optical pattern.

Abstract: A light source for illuminating an area includes a cold cathode light source, and input and an output, and a converter coupled to the light source. The converter changes the current from an input alternating current supply to a lamp alternating current supply suitable for operating the lamp, for example from utility line voltage and current and changing it to an oscillating direct current supply. A display case such as a refrigeration unit may include an alternating current supply and a light source for illuminating an area within the display case. A current converter is coupled between the alternating current supply and the light source for changing the current from the supply at one voltage and frequency to a second voltage and a second frequency. In one preferred form, the light source is a cold cathode lamp at about 8500 Kelvin to include more blue light.

Abstract: A glove permits a flashlight to be removably attached so that when a flashlight is secured to the glove its direction of illumination is in alignment with the direction of fire of a handgun held in a second hand of the user steadied by the first hand.

Abstract: A flat illuminator, which may have a replaceable battery power supply and with a sliding inner body forming an “on” and “off” switch.

Abstract: An artificial lighting apparatus for young plants that includes at least one electric track and a plurality of lamps. The lamps are detachably mounted on the electric track. Each of the lamps includes a plurality of first light emitting diodes, a plurality of second light emitting diodes and a mounting box. The first and second light emitting diodes are alternately arranged. The electric track supplies the lamps with power to light the first and second light emitting diodes. The driver provides the controlling capability on light quantity, quality, frequency and duty ratio.

Abstract: A lighting device has a light source and a light distributor arranged under it. Said light distributor has a distributor element which preferably consists of sheet metal and has an extensive main section with an incidence side facing the light source and a number of holes for the passage of light which widen in the direction away from the incidence side, and a collar for each of said holes. Preferably, a diffuser is arranged above the distributor element and possibly a diaphragm, preferably consisting of sheet metal, is arranged above said diffuser. The light distributor deflects and distributes light radiated downward through it, in such a way that said light makes at least a desired angle of, for example, at least 25° with a horizontal plane. The light distributor can be produced with a small height and economically and has a good antidazzle effect.

Abstract: A plasma display apparatus includes a plasma display panel, a circuit board mounting a drive circuit for driving the plasma display panel, a chassis structure provided on the backside of the plasma display panel for supporting the plasma display panel and for mounting the circuit board. In particular, the chassis structure comprises a first chassis member mounting the circuit board, and a second chassis member fixed on the backside of the plasma display panel, a plurality of support portions provided between the first and second chassis members for supporting the two chassis members and for forming a predetermined interval between the two chassis members.

Abstract: An illumination device formed as a light for a motor vehicle has at least one light emitting element which emits light producing an illumination intensity distribution, and at least one additional light source which emits a light supporting the production of higher illumination intensity value in at least one partial region of an illumination intensity distribution produced by the light exiting the illumination device.

Abstract: An electronically lighted sighting device for use in conjunction with an archery bow is disclosed. The sight includes an electronic circuitry with at least one switch, a plurality of LEDs and elongated fiber optic pins, and having one end of each fiber optic pin located in front of an LED and the other end extended and formed to act as an aiming point. A fiber optic pin transmits the light from the associated LED to the other end of the fiber optic pin or filament, the filament tip then acts as the bright aiming point. The electronic circuitry is powered by batteries and is programmed such that by actuating the switch the archer can select each of the LEDs, individually or collectively, for illumination, along with illumination intensity levels.

Abstract: A lighting device is provided. The lighting device has LED lamps and so forth with high directivity as light source. The lighting device of the present invention is capable of lighting more uniformly. Few labor for maintenance and inspection is necessary. Rich durability is provided therewith and it can be manufactured in low cost. The lighting device is constituted in such a way that a light source body such as LED lamp and so forth is disposed at an end portion of a cylindrical light transmitting member whose degree of transparency is transparent or translucent. The constitution causes the light to travel in the axial direction of the light transmitting member. Transparent or translucent island formation body is provided on the inside of internal surface of the light transmitting member. Islands of the island formation body are made to protrude perpendicular to the axial line of the cylindrical light transmitting member.

Abstract: In a power conversion device comprising an AC filter 2 for harmonic current suppression having a combination of at least some of a reactor, capacitor and resistance and a power conversion circuit 3 that converts AC power into DC power or DC power into AC power and is connected to an AC power source 1 through AC filter 2, by providing: voltage reference calculation means (unit) 5 that calculates and outputs a voltage reference corresponding to the voltage that is to be output by the power conversion device main unit; current detection means (unit) 4 that detects and outputs current flowing through a prescribed location between AC power source 1 and power conversion circuit 3; and voltage reference correction means (unit) 8 that uses the output from current detection means (unit) 4 as a voltage reference correction signal to correct the voltage reference that is output from voltage reference calculation means (unit) 5, resonance of the AC filter for harmonic current suppression is suppressed without employing a

Abstract: The object is to reliably detect a ground fault of a solar battery. To detect a ground fault position to take an efficient measure against the ground fault, DC power input from a solar battery is converted into AC power and supplied to a system. In a system interconnection inverter (utility connected inverter) having non-insulated input and output, the input voltage of a converter circuit and/or the intermediate voltage between the converter circuit and an inverter circuit are varied to control the potential to ground at each portion of the solar battery to a value other than a value close to zero.

Abstract: A power supply comprises a first power converter having respective input and output terminals, and a second power converter having respective input and output terminals. The output terminals of the first and second power converters are connected in series to provide a combined output voltage. A switch is connected to the input terminals of the first and second power converters. The switch has a first state by which the input terminals of the first and second power converters are connected in series, and a second state by which the input terminals of the first and second power converters are connected in parallel. A pulse width modulator (PWM) unit provides a drive signal to regulate current provided to the first and second power converters. A balance winding is coupled between the first and second power converters in order to share power between these two converters when their inputs are connected in series.

Abstract: An electronic voltage convertor designed to increase the voltage from a direct current power supply for use by low current electrical equipment, such as compact flourescent lamps. The electronic voltage convertor includes a circuit having an inner circuit and an outer circuit which are at least partially interconnected by a resistor. The inner circuit includes a transistor and a primary coil of a dual coil transformer, connected between the positive terminal and the ground of the direct current power supply. The outer circuit includes a diode, a secondary coil of the dual coil transformer, an electrolytic capacitor, and a plurality of standard capacitors. The primary and secondary coils are operatively associated such that the voltage across the primary coil is increased by the secondary coil before discharge from the circuit.

Abstract: In a magnetic random access memory circuit, the potential of all sense lines 121 to 124 are equalized, and the potential of all not-selected word lines 133, 135, 136 are equalized and the selected word line 134 is grounded so that a previously charged capacitor 114 is discharged by a current path passing from the capacitor 114 through a MOS transistor 118 maintaining the potential of the sense line 122 at a constant voltage lower than a break voltage, through the selected sense line 122, through the selected magneto-resistive element 142 and through the selected word line 134. Thus, a voltage applied to the magneto-resistive element is maintained at a level smaller than a voltage breaking the magneto-resistive elements or a voltage remarkably deteriorating the characteristics of the magneto-resistive elements because of a biasing effect when the tunnel magneto-resistive element is used, and on the other hand, a high precise and high speed reading can be realized.

Abstract: Included are a memory cell array 10, a sense amplifier 21 for determining a cell storage value by comparing a signal value read out from an addressed EEPROM cell with a reference value, a counter 23 for activating an error signal ERR when the count reaches a set value CNmax, and a control circuit 14 for repeating a write or erase operation on a selected cell in response to an automatic write or erase command until the storage value coincides with an expected value, loading the set value CNmax into the counter 23 prior to starting the repetitions when a test signal is active, incrementing the counter 23 at each repetition, and abnormally terminating the repetitions when the error signal is activated.

Abstract: The present invention provides a semiconductor memory device that performs a highly reliable data read operation at a high speed. This semiconductor memory device reads data stored in memory cells in accordance with a result of a comparison between a signal read out from the memory cells, which are connected to a word line, with a signal read out from a reference cell connected to a reference word line. This semiconductor memory device includes a load capacity adjustment circuit that adjusts the timing of starting up the gate of the reference cell in accordance with each location of the connection of the memory cells to the word line.

Abstract: A method for validating flash memory includes selecting for execution and executing, from a plurality of setup procedures available for the memory, a memory validation setup procedure setting respective values for a plurality of parameters that are also parameters set by execution of the other of the plurality of setup procedures. The method also includes determining that validation of a particular sector of the flash memory is desired and validating the particular sector of the flash memory, including examining the values of the plurality of parameters.

Abstract: The present invention relates to an array of flash memory cells whose unit cell includes a single transistor of MONOS/SONOS structure (Metal/poly-Silicon Oxide Nitride Oxide Semiconductor) and to data programming and erasing using the same. The array of the flash memory cells includes a plurality of flash memory cells arranged in a form of a matrix. The matrix includes a plurality of word lines arranged in one line direction and connected to gates of the flash memory cells is a row, a plurality of selection lines arranged in a direction perpendicular to the word lines and connected to the sources of the flash memory cells arranged in a column, and a plurality of bit lines arranged in a direction parallel to the selection lines and connected to the drains of the flash memory cells of the same column. To program and erase the cells, different biasing conditions are applied to the word lines, selection lines, bit lines, and the wells of the transistors.

Abstract: A flash memory having redundancy content addressable memory (CAM) circuitry is described. The flash memory is capable of substituting a second memory cell for an inoperative memory cell. The flash memory includes a primary array of memory cells, a redundant array of memory cells, and the redundancy CAM circuitry. The redundancy CAM circuitry includes a plurality of dual-ported CAM stages. Each CAM stage includes a CAM cell, a write data bus coupled to the CAM cell, and a read data bus coupled to the CAM cell. The CAM cell stores information regarding a location of an inoperative memory cell in the primary array. The inoperative memory cell requires a substitution with a second memory cell in the redundant array. The write data bus produces the information from the CAM cell responsively to a write select signal. The write select signal is indicative of a write operation to be performed at memory cell locations in the primary array.

Abstract: A method for programming a reference cell of a memory array includes the steps of programming the reference cell with large programming steps until a threshold voltage level of the reference cell is above an interim target level and programming said reference cell with small programming steps until the threshold voltage level is above a final target level.

Abstract: A NAND-cell type EEPROM includes an array of memory cells connected to bit lines. Each cell includes one transistor with a floating gate and a control gate electrode, wherein electrons are tunneled to or from the floating gate to write a data thereinto. A sense/latch circuit is connected to the bit lines, and selectively performs a sense operation and a latch operation of the write data. A program controller is provided for writing the data into a selected memory cell in a designated area, and for reading the data written in the selected cell to verify whether or not its resultant threshold voltage falls within an allowable range. If it is insufficient, the data is rewritten thereinto.

Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

Abstract: A semiconductor integrated circuit is disclosed, in which a memory is activated at high speed in commensurate with a high-speed logic circuit mounted with the memory in order to reduce the cost using a DRAM of a 3-transistor cell requiring no capacitor. A pair of data lines connected with a plurality of memory cells having the amplification function are set to different precharge voltage values, thereby eliminating the need of a dummy cell. The elimination of the need of the dummy cell unlike in the conventional DRAM circuit using a gain cell reduces both the required space and the production cost. A hierarchical structure of the data lines makes a high-speed operation possible. Also, a DRAM circuit can be fabricated through a fabrication process matched with an ordinary logic element.

Abstract: In a memory board 3 provided with: a printed wiring board 300 having a connector terminal 310; and memories 321 to 324 storing data used by an apparatus to which the printed wiling board 300 is attached, a memory controller 306 mediating data communication between the apparatus and the memories is provided. Based on stored setting information, the controller 360 converts the control content received from the main unit into the control content suitable for the access method specific to the memories 321 to 324, and performs read/write refresh.

Abstract: A control circuit comprises an external command recognition section for recognizing an external command, the external command being an operation command input from outside the control circuit, an internal ROM bank including a plurality of storage regions, the internal ROM bank being used to store an internal code for achieving operations specified by the external command recognized by the external command recognition section, an internal ROM selection section for selecting a required storage region from the plurality of storage regions of the internal ROM bank in accordance with the external command recognized by the external command recognition section, a program counter for selecting and indicating an address of an internal command to be executed from a plurality of addresses of internal commands stored in the internal ROM bank, an internal command register for storing the internal command read from the internal ROM bank, and an internal command execution section for executing the internal command stored in

Abstract: A layout of a sense amplifier configuration for a semiconductor memory is described. The layout has a plurality of read/write amplifiers, extending as strips in the form of rows one under the other, and having NMOS and PMOS transistors. At least one of the two driver transistors is disposed with its doping regions between the associated NMOS or PMOS transistors of the read/write amplifiers. A gate of the driver transistor is configured as a two-strip gate, in order to accelerate the signal evaluation in the sense amplifiers.

Abstract: A method for testing a multiplicity of word lines of a semiconductor memory configuration in a multiple word line wafer test is described. To prevent a pulling-up of inactive word lines which are at a negative voltage when the active word lines are ramped down, the inactive word lines are decoupled from the negative word line voltage and are connected to a high impedance shortly before the active word lines are ramped down.

Abstract: An improved method of manufacturing a capacitor structure for a ferroelectric random access memory (FeRAM) device on an active matrix having a first insulating layer comprising the steps of forming a buffer on the first insulating layer, a bottom electrode on the buffer, a capacitor thin film on the bottom electrode and a top electrode on the capacitor thin film. A second insulating layer is formed on the top electrode, the capacitor thin film and the first insulating layer, and then patterned and etched only once to form both a storage node contact hole and a cell plate contact hole. The capacitor structure is completed by forming a metal interconnection pattern on the second insulating layer and the contact holes to provide connection to the storage node and the cell plate.

Abstract: A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.

Abstract: A ferroelectric capacitor is horizontally disposed, in which opposite surfaces of a pair of capacitor electrodes are disposed along the surface of a semiconductor substrate, and an oxidative diffusion barrier film is formed on an upper end of the contact plug having a lower end connected to the diffusion region of a memory cell transistor during the manufacturing steps, after which under the condition where a top end of the contact plug is covered by the oxidative diffusion barrier film, a high-temperature annealing is performed so as to restore any damage applied to the ferroelectric capacitor that may be caused during the manufacturing steps thereof, followed by the removing step of the oxidative diffusion barrier film existing on the surface of the contact plug, and then followed by a forming step of a metallic wiring to obtain a ferroelectric memory product.

Abstract: A reconfigurable memory having M bit lines and a plurality of row lines, where M>1. The memory includes an array of memory storage cells, each memory storage cell storing a data value. The data value is read from or into the storage cells by coupling that data value to one of the bit lines in response to a row control signal on one of the row lines. A row select circuit generates the row control signal on one of the row lines in response to a row address being coupled to the row select circuit. The row select circuit includes a memory for storing a mapping of the row addresses to the row lines that determines which of the row lines is selected for each possible value of the row address. The memory includes a plurality of sense amplifiers, one such sense amplifier being connected to each of the bit lines for measuring a signal value on that bit line. A controller that is part of the memory tests the memory storage cells both at power up and run time to detect defective memory storage cells.

Abstract: A virtual channel DRAM arrangement is provided which can improve cell efficiency, reduce a layout area of a chip and increase a data processing speed, by unifying a data processing method.

Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank comprises of memory cells. The banks are provided with a supply voltage.

Abstract: A line memory control method for temporarily writing input image data into a line memory and reading out the image data written in the line memory on a block basis, comprising: a pre-processing step of reducing the data rate of the input image data; a writing step of successively writing the pre-processed image data into a line memory every line by using a first address; and a reading/writing step of reading out the image data on a line basis every block by using a second address different from the first address after said writing step is finished, and writing image data into a read-out block by using the second address.

Abstract: A semiconductor memory apparatus allowing a memory cell array (SARY) to be divided into a number of blocks (BLK0 to BLK11) that is not a factor of two is provided. Blocks (BLK0 to BLK11) may be arranged into a repeated group of blocks (BLK0 to BLK2, BLK3 to BLK5, BLK6 to BLK8, and BLK9 to BLK11). A group of blocks (BLK0 to BLK2) may have a bit map that can be symmetrical around the center of a center block (BLK1). The semiconductor memory apparatus can include a block selector (400) for selecting a block (BLK0 to BLK11) based on row addresses (X6 to X12). Block selector (400) can include block predecoders (410 and 420) and groups of decoders (4341 to 4343). Block predecoder (410) may select a block in a group of blocks. Block predecoder (420) may select a group of blocks. Blocks may be decoded without overly complicating circuitry.